Overview of

Flash Translation Layer

Jihong Kim
Dept. of CSE, SNU
 Layout of FTL

FTL Interface

FTL
Block Manager Manager Mapping Table
(Engine)

Data Garbage
Wear Leveler
Separator Collector

FTL Overview.2 Jihong Kim (SNU)

 Block Information in FTL
• Block Information FTL Interface

Block FTL

– Maintains status of blocks Manager

Manager
(Engine)
Mapping Table

• Status of a block Wear Leveler

Data Garbage
Separator Collector
– Free, Clean, Dirty, Dead
• Erasure Counts
– Page bitmap
• Denotes which page in a block is used or not
• Used page bit is set to ‘1’

FTL Overview.3 Jihong Kim (SNU)

 Mapping Table
• Address Translation
– Logical Block Address -> Physical Block
Address
• Various Mapping Techniques
– Block mapping FTL Interface
• Logical block vs. physical block FTL
Mapping
– Page mapping
Block Manager Manager
(Engine) Table

• Logical page vs. physical block Wear Leveler

Data
Separator
Garbage
Collector

– Hybrid mapping
• Block mapping + page mapping

FTL Overview.4 Jihong Kim (SNU)

 A Naive Solution: Direct Mapped
FTL
• 1:1 direct mapping between a logical page and a physical page
• A write to logical page N
– Read in the entire block with page N
– Erase the entire block
– Write to logical (i.e., physical) page N
• (+) No need for a complex FTL
• (-) Performance issue: very bad write performance
– Expensive read-modify-write operations
• (-) Reliability issue: a short flash lifetime
– Client workload controls wear out
• Repeated overwrites to the same data
– E.g., file system metadata  same block erasures
– Very high WAF
• Most FTLs are log structured
– Logging a write to the next free page
– Need a L2P mapping table
 Block Mapping
• Each table entry maps one block
Data
blocks
0
1
2
Logical Page offset 3
block number within a block
4
5
LBN 0 6
Logical page #11 00000010 11 LBN 1 7
LBN 2
LBN 3
8
9
10
11

12
13
14
15

FTL Overview.6 Jihong Kim (SNU)

 Overwrites in Flash Memory
• Block Mapping

 New write (2K): 0.2ms

 Overwrite (2K)
− 63 2K-reads = 6.3ms
Data Blocks: − 63 2K-writes = 12.6ms
block mapping
− 1 2K-write = 0.2ms
− 1 erase = 1.5ms

Free Blocks − Total = 20.6ms

FTL Overview.7 Jihong Kim (SNU)

 Page Mapping
• Each table entry maps one page
Physical data
blocks

0
1
4
LPN 0
14
LPN 1
LPN 2
LPN 3 10
LPN 4 5
LPN 5 6
LPN 6 7
LPN 7
LPN 8
LPN 9 2
LPN 10 8
LPN 11 11
LPN 12 13
LPN 13
LPN 14
LPN 15 15
9
3
12
FTL Overview.8 Jihong Kim (SNU)
 Page & Block Mappings
• Page mapping
– Pros
• Can map any logical page to any physical page
• Efficient flash page utilization
– Cons
• mapping table is large
– E.g., 16GB flash, 2KB flash page, requires 32MB SRAM
– As flash size increases, SRAM size must scale
– Too expensive!
• Block mapping
– Pros
• Mapping table size reduced by a factor of (block size / page size)
~ 64 times
– Cons
• Page number offset within a block is fixed
• Garbage collection overheads grow

FTL Overview.9 Jihong Kim (SNU)

 Hybrid Mapping FTLs
• Exploits both mapping schemes
– Page mapping
• Update blocks/ log blocks
– Block mapping
• Data blocks
• Garbage Collection Frequency
– Page level << hybrid <<< block level
• Memory Requirements
– Page level >>> hybrid > block level

FTL Overview.10 Jihong Kim (SNU)

 Hybrid Mapping FTL

Update Yes
Yes
request?

No

FTL Overview.11 Jihong Kim (SNU)

 Example of Hybrid Mapping
• Background
– 2 kinds of blocks
• Data block: block level managed block (most)
• Log block: page level managed block (a few)
– Temporary storage for small size writes to data blocks

Data Block Log Block

Write! valid
Data is written
valid to
valid
a log block.
valid

FTL Overview.12 Jihong Kim (SNU)

 Data Separation Techniques
• Motivation
– Data have different spatial
and temporal localities
– “Frequently updated data FTL Interface

are likely to be updated Block Manager

FTL
Manager Mapping Table

soon” (Engine)

Data
• Hot data identification has a Wear Leveler Separat
Garbage
Collector
or
critical impact on
– The performance (due to
GC)
– The lifespan (due to WL)

FTL Overview.13 Jihong Kim (SNU)

 Hot/Cold Data Separation
Technique
• Key Assumption
– Temporal locality of data updates
• Classification based-on data update frequency
– Hot: frequently updated data
– Cold: infrequently updated data

Yes Frequently No
updated data?

Hot Cold
FTL Overview.14block block Jihong Kim (SNU)
 Garbage Collection
• Get a free block by FTL Interface

reclaiming dirty/dead Block Manager

FTL
Manager
(Engine)
Mapping Table

blocks Garbage
Data
Wear Leveler
• GC Flow Separator Collector

– Select a victim block

– Move valid pages in the
victim block to a new
block
– Erase the victim block

FTL Overview.15 Jihong Kim (SNU)

 Example of Garbage Collection

Write data into logical block address 0

Address Translation
Address Translation Table
Overwrite X

Page 0
Valid page
Page 1
Invalid page
Page 2
Page 3 Free page
Block 0 Block 1

Garbage Collection
(3 copies and 1
erasure)

FTL Overview.16 Jihong Kim (SNU)

 Victim Selection Policy
• Random
– Selects randomly a victim block
• Greedy
– Selects the block including the least
number of valid pages
• Cost benefit
– Based on Greedy Policy=>(min cost)
– Consider data hotness
• Prefer cold data => (max benefit)
FTL Overview.17 Jihong Kim (SNU)
 Wear Leveler in FTL
• Main idea
– Allocates youngest
blocks
– Data Swapping
FTL Interface

FTL

• Hot data->young block Block Manager Manager

(Engine)
Mapping Table

• Cold data -> old block Wear Data Garbage

Separator Collector
Leveler
• Algorithms
– Hot-Cold Swapping
– Dual-Pool Algorithm

FTL Overview.18 Jihong Kim (SNU)

 Booting Sequence in FTL
• Initialize storage system parameter
• Load metadata in Memory
– Mapping Table
– Block Status Table
– Page Bitmap
– Bad Block List

FTL Overview.19 Jihong Kim (SNU)

 Build Metadata (1)
• Full Scanning
– Store metadata to spare area of each page
– Reload metadata in spare area at mounting
time
NAND flash memory

Spare Area

R
E
A
D

FTL Overview.20 Jihong Kim (SNU)

 Build Metadata (2)
• Snapshot-based approach
– Stores metadata snapshot to dedicated areas
in round-robin manner
– Reloads the latest metadata snapshot at
mounting time

The latest snapshot

FTL Overview.21 Jihong Kim (SNU)

 Mounting File System with FTL
In-memory metadata of file systems

root

Dentry Dentry
File System
Dentry Dentry

inode inode inode

Storage Systems
R
E Mapping Table
A
D
NAND flash
Sup memoryInod
Mapping inod Director inod
erblo e
Information e y entry e
ck table
FTL Overview.22 Jihong Kim (SNU)
 Overview of
NAND Flash Memory

Jihong Kim
Dept. of CSE, SNU
Content

 Three Basic Operations of NAND Flash Memory

 Program
 Read
 Erase

 Key Reliability Issues of NAND Flash Memory

 Endurance
 Data retention
 Read disturb

NAND Flash Overview.2

Jihong Kim (SNU)
Example: Paper as Memory

 Very old and very popular memory

 Pencil writing (as Store)
 Erase the written data (as Delete) Write
 Read data from paper

No Overwrites
c.f.) DRAM
Read

Erase

NAND Flash Overview.3

Jihong Kim (SNU)
NAND Flash Architecture
Buffer Memory
NAND
Chip

Controller

Plane 0 Plane 1
Block n-1
Block n-3
I/O 0
 Plane : unit of multi operation

Row decoder
~

Drivers
I/O 7
 Planes consist of multiple blocks
…

… …
in the row direction
Block 4
(SLC : 64 pages / MLC : 128 pages) Block 2
Block 0
 Planes consists of 8ea I/O group
Page Buffer & Drivers (4~8~16KB)
in the column direction Peripheral & Charge pump

NAND Flash Overview.4

Column decoder Jihong Kim (SNU)
NAND Flash Architecture

Peripheral Circuit (Column Decoder)

Sense Amp Sense Amp

Block m-2 Block m-1

…
…
W/L

Row Decoder
Page Page Page … Page Page Page Page … Page
0 1 2 N-1 0 1 2 N-1

Block 2 Block 3

Block 0 Block 1
B/L
Sense Amp Sense Amp

Peripheral Circuit (Column Decoder)

NAND Flash Overview.5

Jihong Kim (SNU)
 NAND Flash Architecture

Peripheral Circuit (Column Decoder) BL0 BLl-1

Sense Amp Sense Amp

Block m-2 Block m-1 Page N-1 WLN-1

…
…

W/L
Row Decoder
Page N-2 WLN-2
Page Page Page … Page Page Page Page … Page
0 1 2 N-1 0 1 2 N-1

Block 2 Block 3
Page 2 WL2
Block 0 Block 1 Page 1 WL1
B/L
Sense Amp Sense Amp Page 0 WL0
Peripheral Circuit (Column Decoder)

…
Data Spare
NAND Flash Overview.6
Jihong Kim (SNU)
Increasing NAND Capacity: Scaling

x2 Scaling
Flash Cell

NAND Block Scale-Downed Block

x4 more cells in the same-sized block!

7
Increasing NAND Capacity: Multi Leveling
Flash Cell

0 00 01

1 10 11
Single-Level Cell Multi-Level Cell
(SLC) (MLC)

x2 more data in the same-sized cell!

8
 3D NAND Flash Memory

x16 more cells in the same area

Shrinking processes, multi-leveling

<3D NAND flash memory>

<Scaling down in the planar NAND>
9 / 36
NAND Operation – SLC vs. MLC (1)

 Good for high capacity

 Bad for performance and reliability

10

0
Double density 00

01
1
11
Single Level Memory Cell (SLC) Multi-Level Memory Cell (MLC)

NAND Flash Overview.10

Jihong Kim (SNU)
NAND Operation – SLC vs. MLC (2)

 In order to reduce the bit per cost (or acquire the high capacity),
multi-level cell technology is introduced

NAND Flash Overview.11

Jihong Kim (SNU)
ISPP ?

NAND Flash Overview.12

Jihong Kim (SNU)
NAND Operation – ISPP (1)

 The difference in cell speed due to the process variation makes

difficult to control the cell Vth distribution

If high voltage is applied to

program NAND cell at one time
# of cells

Vth
slow cell medium cell fast cell

NAND Flash Overview.13

Jihong Kim (SNU)
NAND Operation – ISPP (2)

 How to control the cell Vth : Incremental Step Program Pulse

 Cell Vth width control using repeated program operation
 The smaller ISPP, the smaller cell Vth width (the lower BER)
 The smaller ISPP, the larger program loop (the larger program latency)

NAND Flash Overview.14

Jihong Kim (SNU)
NAND Operation – Read

 Check the current flow of the string

 VSEL > cell Vth  Cell transistor is turn-on  Current flow  Cell data is “1”
 VSEL < cell Vth  Cell transistor is turn-off  No current flow  Cell data is “0”

Select
WL level
(VSEL) VREAD
# of cells

On Off

Vth

15
NAND Flash Overview.15
Jihong Kim (SNU)
NAND Operation – Erase

 High voltage at substrate transfers electron from FG to substrate by

F-N tunneling

Vcg (>20V) Vcg (0V)

CG CG
0V e- e- e- e- e- e- 0V float FG float

e- e- e- e- e- e-
Vsub (0V) Vsub (>20V)

Program : FN tunneling Erase : FN tunneling

Off cell  Data “0” On cell  Data “1” 16

NAND Flash Overview.16
Jihong Kim (SNU)
Key Reliability Issues in Flash Memory
• Flash memory must maintain the integrity of the
stored data. The key concerns are:

• Data Retention

• NAND Endurance

• Read Disturbs
Data Retention

1 Year at 30 °C?
 Read Disturb Problem
• Read disturb occurs when a page is read in a block
Block 0
1111111 1111111 Read 1111111
1111111 1111111 1111111
1111000 Read 1111000 1111000
0000000 0000000 0000000 Read

Read Disturb
Data corruption

1111111 1111110
1111111 1111111
1111000 1111000
0000000 Read 0000000 Read

The maximum read count between successive

erasures is limited.
19
NAND Flash Reliability

Endurance Retention Read Disturb

A limited number of Data loss by leakage A limited number of

program/erase operations read operations

No
flow !!

NAND Flash Overview.20

Jihong Kim (SNU)
NAND Flash Reliability – Endurance

 Repeated program & erase operations wear-out NAND flash

because of tunnel oxide degradation
 High voltage in program & erase operation give a damage to tunnel oxide, and
then increase interface and oxide trap density
 The larger number of P/E cycles, the higher BER (Bit error rate)
 Tunnel oxide damage accelerates the reliability degradation, for example
retention error and read disturb error

CG
FG # of error pages
Program Erase

# of program / erase cycles

Interface & oxide trap in oxide
NAND Flash Overview.21
Jihong Kim (SNU)
NAND Flash Reliability – Retention

 The retention concept is the ability of a memory to keep a stored

information over time with no biases applied
 Thermal stress (= high ambient temperature) leads to charge loss which means
cell Vth shift to lower state
 Charge loss causes an increase in BER, eventually read failures
 The higher cell Vth, the larger charge loss

“All cell tend to be initial state”

Error probability
# of cell

Cell Vth [V] Time (month)

NAND Flash Overview.22
Jihong Kim (SNU)
NAND Flash Reliability – Read Disturb

 Read disturb is an unexpected soft-program phenomenon due to

repeated read operations
 VREAD (6~7V) which is applied to unselect W/L’s in read operation can cause a
soft-programming.
 Read stress increases with the read voltage and read operation time
 As P/E cycles increase, read disturb errors are accelerated

VREAD
“Unexpected disturb errors”
CG
FG e-
# of cell

e- e- e- e- e-

NAND Flash Overview.23

Jihong Kim (SNU)
 NAND Flash Trade-Off Overview

Endurance

∑∆𝑾𝒗𝒕𝒉
Perfor-
mance NAND Retention
Vth
Flash
Margin
Memory ∆𝑾𝒗𝒕𝒉
∆𝑾𝒗𝒕𝒉
Read
Capacity
Disturb
Tuning
Control
24 / 21
 Write Performance vs. Retention
Normal write
1 0 1 1 0 1 0 1 1 1 0 0 0 1 1 1

Fast write Data retention

1 0 1 1 0 1 0 1 1 1 0 0 0 1 1 1

Cannot distinguish the program state: Reliability ↓

Slow write

1 0 1 1 0 1 0 1 1 1 0 0 0 1 1 1

Still recognizable program state: Reliability ↑

25
Capacity vs. Write Performance
What happens in a NAND page-write

1 0 1 1 0 1 0 1 1 1 0 0 0 1 1 1

Program state variances

Program disturbances
(depending on cell characteristics)

With shrunk processes and multi-leveling

1) Precise voltage control for smaller grids

00 01 10 11 2) Multi-step writing
(e.g., ISPP – Incremental Step Pulse Program)

26
FTL: Address Mapping
Techniques
Part 1
Jihong Kim
Dept. of CSE, SNU
 Contents
• Introduction
• Page-level Mapping
• Block-level Mapping
• Replacement Block Scheme
• Hybrid Mapping

FTL Mapping Part 1 (Jihong Kim/SNU) 2

 S/W Architecture

Applications

Operating Systems

File System (for H.D.D)

Flash File Systems

Flash Translation Layer

Block Device Driver (MTD)

NAND Flash Memory

FTL Mapping Part 1 (Jihong Kim/SNU) 3

 Flash Translation Layer
• A software layer to make NAND flash emulate
traditional block devices (or disks)

FTL Mapping Part 1 (Jihong Kim/SNU) 4

 Remind: Roles of FTL
• For performance ▪ For Reliability
– Indirect mapping • Bad block management
(address translation) • Wear-leveling
– Garbage collection • Power-off recovery
– Over-provisioning • Error correction code
– Hot/cold separation (ECC)
– Interleaving over • ...
multiple channels/flash ▪ Other Features
chips/planes
• Encryption
– Request scheduling
• Compression
– Buffer management
• De-duplication
– …
• ...
FTL Mapping Part 1 (Jihong Kim/SNU) 5
 Mapping
• Mapping Granularity
– Page-level mapping – Block-level mapping

NAND flash block NAND flash block

FTL Mapping Part 1 (Jihong Kim/SNU) 6
 A simple page-mapped FTL
• Read operation Block 0
h
data blocks
Logical page #
i
Read a
c
LBA address c
Block 1
b
f g
d
f
b
Block 2
j
read d
Page-level a

mapping table
Block 3
f 1 3

block#page# Block 1024

free blocks

FTL Mapping Part 1 (Jihong Kim/SNU) 7

 A simple page-mapped FTL
• Write operation Block 0
h
data blocks
Logical page #
i
Writ a
c
LBA address e c
Block 1
b
f g
d
f
b
Block 2
Invalid j
d
Page-level a

mapping table f

f Block 3
12 3 update

block#page# Block 1024

free blocks

FTL Mapping Part 1 (Jihong Kim/SNU) 8

 A simple page-mapped FTL
• Garbage Collection Victi
free block
Block 0
h
m i
Writ a Erase
block c
LBA address e c
Block 1
b
f g
d
f
b
Block 2
j
Page-level d
a
mapping table f
c 1024 2
Block 3
f 2 3 update
h 1024 0
i 1024 1
free blocks
block#page# Block 1024
h
4. Copy
2.
1. Erase all
Select victim
the the blockblock
victim
valid data and
to free
free block i
c
data block
3. Update mapping table
block
FTL Mapping Part 1 (Jihong Kim/SNU) 9
 Page-level Mapping
• Can map any logical page to any physical page
• Efficient flash page utilization
• Small Garbage collection overhead

FTL Mapping Part 1 (Jihong Kim/SNU) 10

 Challenges in Page-level Mapping FTLs
• Mapping memory management
– Large memory requirement
• e.g., 128GB -> 32MB address entries * 4 Bytes per entry = 128 MB

– Long reconstruction time

NAND flash memory
Memor Spare Area
LBA y PBA PBA LBA
0 3 0 3
1 2 1 2 R
2 1 2 1 E
3 0 3 0 A
4 1024 D

1024 4

FTL Mapping Part 1 (Jihong Kim/SNU) 11

 Mapping Table Size Problem

With a 8-K page size:

32 TB-> 4 GB address entries * 4 Bytes per entry = 16 GB

Q: Can we do with a lot less than 16 GB?

FTL Mapping Part 1 (Jihong Kim/SNU) 12
 A Simple Block-mapped FTL
• Read operation Block 0
a
data blocks
Logical page #
b
Read c

LBA address
Block 1
a
d 3 b
c
d

Block 2
f
g
Block-level h

mapping table
Block 3
d 1

block# free blocks

FTL Mapping Part 1 (Jihong Kim/SNU) 13

 A Simple Block-mapped FTL
• Write operation Block 0
a
data blocks
Logical page #
b
Writ c

LBA address e
Block 1
a
d 3 b
c
d

Invalid Block 2
f
copy g
Block-level ah

mapping table
Block 3
d 31 a
update b
c
d
update
block#
free blocks

FTL Mapping Part 1 (Jihong Kim/SNU) 14

 A Simple Block-mapped FTL
• Garbage Collection New Free blocks
Block 0
a
b
Writ c Erase
LBA address e
Block 1
a
d 3 b
c Erase
d

Block 2
f
Block-level g
ah
mapping table

Block 3
d 3 a
update b
c
d
update

free blocks

FTL Mapping Part 1 (Jihong Kim/SNU) 15

 Block-level Mapping
• Requires a much smaller mapping table
• Page offset is fixed
• Low utilization

FTL Mapping Part 1 (Jihong Kim/SNU) 16

 Challenge in Block-level Mapping FTLs
• Poor small-random write performance
– Due to expensive copy operation when only a part
of block is modified
• Various schemes have been introduced
– Replacement block scheme
– Log block scheme
– Super block scheme
– FAST and LAST
– Etc.

FTL Mapping Part 1 (Jihong Kim/SNU) 17

 Replacement Block Scheme
• Idea
– A data block has a chain of write buffer blocks
called replacement blocks
– Mapping within a replacement block is managed
in block-level

FTL Mapping Part 1 (Jihong Kim/SNU) 18

 Replacement Block Scheme
• Replacement-block scheme
– Maintain write history between an original block
and an updated block.
– (e.g.) Write trace 1,
1: , 2,
2 3, 4 4,
3 4, 4 33, 4

1
2
3
Invalid 3
4
Invalid Invalid
4 4

Consecutive Programming Constraint

FTL Mapping Part 1 (Jihong Kim/SNU) 19
 Replacement Block Scheme
• Merge operation
– Is triggered when there is no free block for a
replacement block
– Gathers valid pages in a data block and write
buffer blocks (replacement blocks) to form a single
complete data block

FTL Mapping Part 1 (Jihong Kim/SNU) 20

 Merge Operation

Data Block Replacement Block 1 Replacement Block 2 New Block

FTL Mapping Part 1 (Jihong Kim/SNU) 21

 Replacement Block Scheme
• Problems
– Low utilization of replacement blocks
– Sequential traverse over replacement blocks during
reads and writes
– No consideration for sequential programming
constraint

FTL Mapping Part 1 (Jihong Kim/SNU) 22

 Hybrid Mapping
Page level mapping Block level mapping

- Logical page is mapped - Logical block is mapped

Characteristi
to physical page to physical block
c
- Large mapping table - Small mapping table
- Small management
- Efficient in handling small
Pros overhead for maintaining
size writes
translation information
- Large management
- Less efficient in handling
Cons overhead for maintaining
small size writes
translation information

Combination of the two different granularities for the better

performance
FTL Mapping Part 1 (Jihong Kim/SNU) 23
 Hybrid Mapping FTLs
• Exploits both mapping schemes
– Page mapping
• Update blocks/ log blocks
– Block mapping
• Data blocks
• Garbage Collection Frequency
– Page level << hybrid <<< block level
• Memory Requirements
– Page level >>> hybrid > block level

FTL Mapping Part 1 (Jihong Kim/SNU) 24

 Log Block Scheme
• Background
– 2 kinds of blocks
• Data block: block level managed block (most)
• Log block: page level managed block (a few)
– Temporary storage for small size writes to data blocks
Data Block Log Block

Write! valid
Data is written
valid to
valid
the log block
valid

FTL Mapping Part 1 (Jihong Kim/SNU) 25

 BAST
• BAST : Block Associative Sector Translation
• Key idea
– A certain log block is dedicated to only one data
block
– Mapping within a log block is managed in page-
level

FTL Mapping Part 1 (Jihong Kim/SNU) 26

 BAST
• Merge Operation (1)
– Full merge
Data Block Data Block
Free Block Log Block
valid

valid
valid valid
valid

valid
valid valid

Free blocks
FTL Mapping Part 1 (Jihong Kim/SNU) 27
 BAST
• Merge Operation (2)
– Partial merge
Data Block Data
Log Block
valid
valid
valid
valid
valid
valid
valid
valid

Free blocks
FTL Mapping Part 1 (Jihong Kim/SNU) 28
 BAST
• Merge Operation (3)
– Switch merge
Data Block Data
Log Block
Block
valid
valid
valid
valid
valid
valid
valid
valid

Free blocks
FTL Mapping Part 1 (Jihong Kim/SNU) 29
 BAST
• Good performance in sequential write
• But, frequent merge operation
– In random write patterns
– In complicated application

FTL Mapping Part 1 (Jihong Kim/SNU) 30

 References
• Rosenblum, M. and Ousterhout, J. “The design and implementation of a log-structured file
system,” ACM Transactions on Computer Systems, vol. 10, pp. 26-52, 1992.

• Chiang, M., Lee, P., and Chang, R. “Using data clustering to improve cleaning performance for
flash memory,” Softw. Pract. Exper., vol. 29, pp. 267-290, 1999.

• Kim, H., and Lee, S. “A New Flash Memory Management for Flash Storage System,” 23rd
International Computer Software and Applications Conference, 1999.

• Gal, E., and Toledo, S. “Algorithms and data structures for flash memories,” ACM Comput.
Surv., vol. 37, pp. 138-163, 2005.

• H. Kim et al, “BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash
Storage,” Proceedings of the 6th USENIX Conference on File and Storage Technologies, 2008.

FTL Mapping Part 1 (Jihong Kim/SNU) 31