 Discuss about Brief Overview of Programmable Logic Devices

 Discuss about Block Diagram for Keypad Scanner and Scanner Modules
 Explain how PLA with Three Inputs, Five Product Terms, and Four Outputs (Transistor
Level)
 Design of a Block Diagram for Parallel Binary Divider
 Explain about Implementation of a Full Adder Using a PAL.
 Design Example Partial State Graph in State Graphs for Control Circuits
 Design Behavioral Model for 4X4 Binary Multiplier using VHDL Code
 What are Simplified View of the Xilinx Spartan and Virtex Slice
 Write Behavioral Model for Dice Game Controller and its State Graph
 What are the different programming technologies for FPGAs?
 Write VHDL Code for Scanner
 Explain about FPGAS and One-Hot State Assignment
 Explain about Linked SM Charts for Dice Game
 Design VHDL Code for a Floating-Point Adder
 Explain about SM Chart and Operation Flow of the Multiplier and Pseudo code representing
the operation of the multiplier controller using microprogramming approach
 Design VHDL Code for Floating-Point Multiplier
 Design the Realization of Dice Game Controller
 Discuss about CPLD and draw the FLEX 10k Block Diagram
 Explain about Represent 13.45 in the IEEE Single Precision Floating-Point Representation
and IEEE Double Precision Floating-Point Representation
 General method for using BIST (Generic BIST Scheme) and block diagram of a Self-Test
Circuit for RAM with Signature Register, Four-Bit Linear Feedback Shift Register (LFSR)
 Draw the Flow Chart for Floating Point Multiplication with 2’s Complement Fractions/
Exponents and State Graph for Multiplier Control
 Discuss about scan path testing based on two-port flip-flops and Scan Test Configuration
with Multiple ICs
 Draw the Flow Chart for Floating Point Addition and Overview of a Floating-Point Adder
 Design IC with added boundary scan logic according to the IEEE standard and a typical
boundary scan cell
Designing with Programmable Logic Devices:

Read-Only Memories

Compute the size of the ROM required to implement an 8-to-3 priority encoder.
Programmable Logic Arrays
Programmable Array Logic

CPLD
Organization of FPGAs

Figure 3-26 shows the layout of a typical FPGA. The interior of FPGAs typically contains three elements that
are programmable: Programmable logic blocks Programmable input/output blocks Programmable routing
resources

four different basic architectures or topologies:

Matrix-based (symmetrical array) architectures

Row-based architectures

Hierarchical PLD architectures

Sea-of-gates architecture
FPGA Programming Technologies

 FPGAs use one of the following programming methods:

In some FPGAs, the programmable connections between different points are achieved by what is called an
“antifuse.” Contrary to fuse wires that blow open when high current passes through them, the “antifuse”
programming element changes from high resistance (open) to low resistance (closed) when a high voltage is
applied to it. Antifuses are often built using dielectric layers diffusion and polysilicon layers or by amorphous
silicon between metal layers.

There are different antifuse technologies; a popular one is the Via antifuse technology. Antifuse technology
has the advantage that the area consumed by the programmable switch is small. Another advantage is that
antifuse-based connections are faster than SRAM- and EEPROM-based switches. The disadvantage of the
antifuse technology is that it is not reprogrammable. It is a permanent connection; if an error or design
change necessitates reprogramming, a new device is required.

Comparison of Programming Technologies Table 3-8 compares

the characteristics of the major programming technologies used by FPGAs. Only the SRAM and EEPROM
programming technologies allow in-circuit programmability. In-circuit programmability means that an FPGA
can be reprogrammed without removing it from the board in which it is used. In-circuit programmability is
not possible in traditional EPROM-based devices, but EEPROM/flash technologies allow in-circuit
reprogrammability
Programmable Interconnects

ALU
State Graphs for Control Circuits
Behavioral Model for 4 X 4 Binary Multiplier
Keypad Scanner
Microprogramming
Linked State Machines
The Xilinx Configurable Logic Block

FPGAS and One-Hot State Assignment

A simple representation of a floating-point (or real) number (N) uses a fraction (F), base (B), and exponent
(E), where N

The designers of IEEE 754 desired a format that was easy to sort and hence adopted a sign-magnitude
system for the fractional part and a biased notation for the exponent
Floating-Point Multiplication
Floating-Point Addition
Testing Combinational Logic
Testing Sequential Logic
Scan Testing

Boundary Scan
Built-In Self-Test