Technology Trends,

Power Metrics and

Power Models
M. Poncino
 Outline

•Introduction
•Why power became a critical FOM
•Power and Energy metrics
•Power and Energy models

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Introduction
 Introduction
• Understanding technological issues is fundamental
to address the problems:
- It is technology that opens the way to better devices
• Faster, more features, longer lifetime, …
- Implications not just in electronics
• (e.g., automotive, smart grids, …)

• Many difficulties involved in the design of electronic

systems is not just in the manufacturing process itself
but also in the existence of too many non-idealities
- Consequence of silicon technology scaling

Don’t worry, this is not a technology course 

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 The building blocks
• Current dominant technology for digital circuits is CMOS
- possibly not “pure” (or “bulk”) CMOS
• Other technologies:
- Bipolar (e.g., TTL)
- Bi-CMOS - hybrid Bipolar, CMOS
- GaAs - Gallium Arsenide (for high speed)
- Si-Ge - Silicon Germanium (for high speed, RF)
- SOI – Silicon On Insulator (for low leakage)

• Used for different targets

- (high-speed, high-frequency, e.g., 5G)

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 Transistor Basics
• CMOS transistor (n-type)
- Basically, a switch SiO2 Gate
Insulator L
D (oxide)
W
Source Drain
G
n+ n+
channel

S p substrate

• Technology characterized by the value of L

(channel length feature size)
- Today’ mainstream standard production has L=10-7 nm
- Single devices with L of 1-2 nms already demonstrated

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Why Power has become
a critical FOM
 CMOS Scaling
• CMOS was the winning technology because of its nice
property of scalability
- i.e. geometric scaling most figures of merit scale accordingly
after each generation
- Scaling is “easily” supported by manufacturing

• Scaling is not perfect however as we will see…

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 “Constant Field” (Dennard) Scaling

Transistor
Parameter Value Scaled Value
Gate
Transistor
αL,
Transistor Transistor Isolation
Source Drain

Dimensions L, W, Tox αW,

αTox
Electron Flow
STI n+ n+ STI
p
Conventional Silicon Substrate
Voltage V αV

All Features Reduce in Width and

Gate Capacitance C αC
Thickness

Shorter Distance for Electron Flow

Current I αI
Produce Faster Transistors
Propagation time t αt
STI n+ Electron Flow n+ STI
(~CV/I)
p
Power (VI) P α2P
Density d/α2
Scale factor α<1
d
Power density P/A P/A
9
 “Constant Field” (Dennard) Scaling

Transistor
Parameter Value Scaled Value
Gate
Transistor
αL,
Transistor Transistor Isolation
Source Drain

Dimensions L, W, Tox αW,

STI n+
Electron Flow

p
n+ STI
Faster,
Voltage
smaller, V
αTox
αV
Conventional Silicon Substrate

All Features Reduce in Width and

Thickness
less power
Gate Capacitance C αC
Current I αI
Shorter Distance for Electron Flow
Produce Faster Transistors
consuming
Propagation time
(~CV/I)
t αt
STI n+ Electron Flow n+ STI
p
Power (VI) P α2P
Density d/α2
Scale factor α<1
d
Power density P/A P/A
10
 Scaling = Moore’s Law?
• Not exactly…
• Moore’s law is an empirical pre-CMOS law!
- In 1965, Gordon Moore predicted that transistors would
continue to shrink, allowing:
- Doubled transistor density
every 18-24 months
- Doubled performance
every 18-24 months
• History has actually shown
that Moore was right…

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 Reality vs Moore’s law
2005 ITRS Product Technology Trends -
Functions per Chip
1.E+03
Flash Bits/Chip (Gbits)
Single-Level-Cell (SLC )
Average Industry 1970-2020
“Moore’s Law”: 2x
1.E+02
Flash Bits/Chip (Gbits)
Multi-Level-Cell (MLC)
Functions/chip per 2 years
[ Giga (10^9) - bits, transistors ]
Product Functions/Chip

1.E+01 MPU GTransistors/Chip -

high-performance (hp)

1.E+00 MPU GTransistors/Chip -

cost-performanc (cp)

1.E-01 DRAM Bits/Chip (Gbits)

Average Industry
1.E-02 "Moores Law"
1995 2000 2005 2010 2015 2020
Year of Production

Source: ITRS Roadmap 2005 2005 - 2020 ITRS Range

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 CMOS scaling – the reality
The end of Dennard Scaling

• Traditional scaling relies on the fact that the supply

voltage (Vdd) scales according to the scaling factor
• This not possible, unfortunately, as threshold voltage Vth
cannot scale arbitrarily!
• Vdd–Vth determines the performance (current)!

Vdd–Vth
ΔVth: Vth variation
margin for Vth
variation is necessary
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 CMOS scaling – the reality
• Traditional scaling relies on the fact that the supply
voltage (Vdd) scales according to the scaling factor
RECAP: Delay
• This not possible, of a CMOS Gate is
unfortunately…
d ≈
- kT/q does not scale (26mV)
2C V /K(V
- Threshold voltage VLth cannot
-V
dd scale dd th )2

• Vdd–Vth determines the performance (current)!

Vdd–Vth
ΔVth: Vth variation
margin for Vth
variation is necessary

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 VDD (no more) scaling

5V plateau Evolution of VDD (LSTP)

5
Regular Decrease in 10 years
4 From 5V to 1.2V (x 0.7 per node)

3
Volt

0.9-1V plateau ???

2 1.2V plateau
1.1V
1
700 500 350 250 180 120 90 65 45 32
0
1980 1992 1995 1998 2000 2002 2004 2007 2010 2015
Year of production (ITRS)
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 Effects of Scaling –
Full vs. Fixed-Voltage scaling
Parameter Relation Full Fixed-Voltage
IDSAT scaling is constant forScaling
constant voltage scaling
Scaling
W, L, tox α.
1/α and W by 1/α
since Cox scales by 1/α
Vdd, Vt 1/α 1
Area/device WL 1/α2 1/α2
Cox 1/tox α α
Cgate CoxWL 1/α 1/α
Isat CoxWV 1/α 1
Current Density Isat/Area α α2
Ron V/Isat 1 1
Intrinsic Delay RonCgate 1/α 1/α
P IsatV 1/α2 1
Power Density P/Area 1 α2
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 Summary – effects of (device) scaling

• Scaling improves:
- Speed
- Density (area)
- Power, if Vdd also scales
• Under the experienced Vdd flattening of
current technologies:
- Power does not scale
- Power/current densities increase!
- “Predictability” decreases

“Power-constrained” CMOS scaling!

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 Limits of scaling?
• There are of course physical limits to the
scaling of CMOS
- E.g., the minimum distance between Si atoms (0.3nm)
• Death of CMOS has been proclaimed many times…
…. Theory leaves a lot of margin for scaling!

• However, CMOS scaling will be very likely limited by

economical factors…

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 Rising Fab Cost
• Exponential increase of fab cost!
• The average cost of a leading-edge fab (300mm wafers)
reached the $15-$20 billion mark in 2020
- Some countries with GDP ~$20bn or less:
Iceland, Moldova, Montenegro, Mongolia, Senegal, Bosnia,
Georgia, Albania, Armenia, Jamaica, …
• Update as technology scales further

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 Rising Fab Cost
•

orange band = companies that can afford to build a fab that makes chips out of 300mm silicon wafers.
green band = companies that can afford to build chips with a 2015 manufacturing process
Updated 2023 figures estimate that there are only 8
semiconductor companies currently able to afford such a cost.
22
 Power issues
• Projecting power consumption
- Will soon get to KW?
- Yes, if we do not use power reduction solutions
• Projections of a 2001 paper… 100kW !!!

today

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Power issues

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 Do not underestimate power density!
• Non-decreasing power with decreasing area increases
power density
• Who cares?
- Important for thermal issues
• heat flux density is W/m2
• And temperature affects (static) power

High perf.
Cores are here
(100-1000 W/cm2)

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 Do not underestimate power density!
• The famous “dark silicon” issue…
- Cannot use all HW simultaneously…
• An example [adapted from S. Borkar]:
- A high-performance core with 500 W/cm2 on a 2cm x 2cm die
- P = 2kW !
- If die power (Thermal Design Power, TDP) has to be limited to
200W, only 10% of the devices in the core can switch at any time
(assuming that nothing else dissipates power!!!)

• Last, but not least, higher temperatures negatively

affect reliability
- Any reliability mechanism exponentially depedent on T
(Arrhenius’ law)
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 In conclusion
• Technology is primary reason for which power
consumption of devices has become an issue
- Designers worried about power long before the always-
connected scenario…

• More recently, other drivers made power even more

important

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 In this course
• Focus on power/energy from a system perspective

• We will NOT learn how to design components that

are energy-efficient but rather how to use them in
an energy efficient way

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 Power:
Models & Metrics
Massimo Poncino
 Outline

• Why low-power?
• Where does the power go?
• Power metrics
• Power consumption sources and relative models

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Why low power?
 Why Worry about Power?
 Total Energy of Milky Way Galaxy: 1059 J

 Minimum switching energy for

digital gate (1 electron@100 mV):
1.6 10-20 J (limited by thermal noise)
 Upper bound on number of digital operations: ~6 1078

 Operations/year performed by 1 billion 100 MOPS

computers: 3 1024
 Energy would be “consumed” in 180 years!!!
 assuming a doubling of computational requirements every year
(Moore’s Law).

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 Why low-power?
• “Obvious” drivers for low power:
- User perception (more battery duration, lighter devices, etc.)
- Cost (lower energy bill)

• Some other less intuitive drivers:

- Technological
- Market
- Economical
- Environmental

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 Why low-power (1) ?
• Technology drivers:
- Difficult to pack devices with high power consumption
• Manufacturing and operating challenges
- Battery technology does not match the speed of silicon technology (no
battery Moore’s law…)
16x Chip power requirements:
35-40% per year.
Improvement (compared to year 0)

14x

12x
Linear scale!!!
10x

8x
Battery evolution:
6x 10-15% per year.
4x

2x
1x

0 1 2 3 4 5 6
Time (years)

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 Why low-power (2) ?
• Market drivers:
- A larger fraction of the market includes battery-powered devices
- Low power translates into “better” products
• More functionalities per Watt

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 Why low-power (3) ?
• Economical drivers:
- Not just a side-effect of market drivers
- High-power devices are most costly!
• E.g., fans, packages
• Example:
BGA Normalized cost vs. power
BGA
Ceramic

max cost
Metal
min cost

Organic Source: STM Corporate Packaging

Baseline
0 1 2 3 4 5 6
Normalized cost

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 Why low-power (4) ?
• Environmental drivers: sustainability
• Link between power and CO2 (Carbon Footprint, CF, CO2 grams)
through the carbon intensity (CI)
CF = energy x CI
- CI [CO2-g /kWh] strongly dependent on how energy is generated!
• https://ourworldindata.org/grapher/carbon-intensity-electricity
- Example 2022: CIBotswana= 795 (top), CIUS = 368 CIItaly= 373 CIFrance= 85 CINorway= 25

2000 2022

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 Why low-power (4) ?
• Example: Google search
- In 2008 US physicist Alex Wissner-Gross claims that a Google search on
a desktop computer produces about 7g of CO2
• Google disputed the figure claiming a search produced only
0.2g of carbon dioxide
- In 2018 an estimate from British environmental consultancy put it
between 1g and 10g of CO2 per search.

1 Wh = 3600 J
• Huge impact of 1 Wh = CI/1000 = 0.373g (Italy)
AI-enhanced operations!
- [source A. De Vries, 2023] ~1g CO2 (2022)

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 Why low-power (4) ?
• Just for a comparison: car emission
- Typical compact size car with 20,000 km/year
- 100 CO2 g/km is the typical “eco” mark = 2 tons /year
• @60km/h => 1 minute/km = 1.5 g/s

• 1 second of driving ~equals 1 ChatGPT (complex?) query

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 Where does
the power go?
 Where does the power go?
• Difficult to answer due to many reasons
- Depends on the system
- Depends on the workload
- Depends on what type of breakdown we care about
• Coarse vs. fine-grain:
- “System” components vs. hardware components?
- {Core, memory, I/O, fans,…} vs. {cache, ALU, FPU, register bank,…}

• Let’s see some examples….

42
 Where does the power go? (1)
• Laptop PC

Source: T. Rosing

Src: Mahesri et al., U of Illinois, 2004

Source Bose, Hot Chips 2005,

43
 Where does the power go? (3)
• Wireless sensor node:
- Mica motes
• Microcontroller: 7.4 MHz, 8 bit
• Memory: 4KB data, 128 KB program

Source: Harvard Sensor Labs

44
 What consumes power?
• Case of a smartphone
Source: J. Sharkey, Google IO

45
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 So, who is the biggest power eater?
• Using a single breakdown plot makes sense ONLY for
very application-specific devices
- e.g., car navigator, e-book, MP3 player…
- But such “single-task” devices have disappeared
• Only very simple sense-compute-transmit IoT devices
have such behavior

• Not meaningful for a (minimally) programmable and

multi-function device, e.g., a smartphone

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 Typical energy breakdown 47

Smartphone
• Samsung Galaxy S3 – S4
- Average energy drain breakdown of 1520 users (classified
by activity rate)

X. Chen et al., “Smartphone Energy Drain in the Wild: Analysis and Implications”, ACM SIGMETRICS 2015

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 Example on I-Phone
• Workload 1: internet phone

Total ~ 800mW

Source: Kim et al., 2011 Korean Conf. on Science & Tech

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 Example on I-Phone
• Workload 2: social networking

Total ~ 150mW

Source: Kim et al., 2011 Korean Conf. on Science & Tech

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 Example on I-Phone
• Workload 3: Video streaming

Total ~ 300mW

Source: Kim et al., 2011 Korean Conf. on Science & Tech

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 Example on I-Phone
• Workload 4: Gaming

Total ~ 400mW

Source: Kim et al., 2011 Korean Conf. on Science & Tech

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 Example on I-Phone
• Workload 5: Navigation

Total ~ 300mW

Source: Kim et al., 2011 Korean Conf. on Science & Tech

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 Example on I-Phone
• Putting them all together

Source: Kim et al., 2011 Korean Conf. on Science & Tech

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 The importance of workload
• Maybe “where does the power go?”
is the wrong question!
• What the system does is probably at least as important…
- Power is operation-dependent

• Workload is the keyword…

- Power breakdown (and optimization) should be “averaged”
over various possible workloads
• A weighted average:
- what I do the most in my system?
- what is the absolute value of total power for a given
workload?

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 So, where does the power go?
• Power is an “average” quantity:
targeting the most critical component will affect total
power the most
- Different target architectures imply different
dominating “parts”
• Shooting at the power hungry portions requires
power reduction on every type of resource
- Cores
- Caches/memories
- Interconnects
- Devices
- Analog
- …

55
Power Metrics

56
 Power Metrics
• Often a misconception about these two metrics…
• Power is the rate at which energy is consumed
• Energy is the amount of power consumed

P(t) Peak Power

Avg. Power
Energy
t

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 Power vs. Energy
• Often a misconception about these two metrics…
• Power is the rate at which energy is consumed
• Energy is the amount of power consumed

Energy

Power

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 Power vs. Energy
• You can use a transformation that reduces power but not
energy or viceversa.

P P Modified
original (higher power,
Modified lower energy)
(lower power, original
energy?)

t t

Using a metric such as energy per operation

fixes the issues due to variable time scale

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Power Consumption
Models
 Power components in digital CMOS

•Three sources:
- Switching power: Pswitching Dynamic
- Short circuit power: PSC

- Leakage currents: Pleakage Static

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 Switching Power

• Due to charging and discharging of output

capacitances
Power Supply Vdd
Stored
Time Voltage Charge Energy
Non linear.
VDD Non storing
element.
t =0 v(t) = 0 0 0
CVDD
1
v(t) t =T v(t) =VDD CVDD
2

2
VDD
Supplied ENERGY= C· VDD2
| |
t
t =0 T

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 Switching Power
• Switching power of a CMOS gate:

Pswitching = aSW · ½ · CL · VDD2 · fCK

- fCK = Clock frequency.
- CL = Output load capacitance.
- aSW = Switching activity factor.

• Switching activity:
- Represents the average number of transitions of
a signal during a clock cycle
• Ceff = aSW · CL is the effective capacitance of a node

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 Switching power
Power Reduction Strategies:
Average Power consumed by the circuit is:

Pswitching =  eff DD clk eff DD ⋅ f clk

i
C i
⋅ V 2
⋅ f =C ⋅ V 2

CLOCK f
Decrease: VOLTAGE

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 Short-Circuit Power
• Power consumed due to non ideality of the
transitions (non-zero rise/fall times)
VDD
VDD-|VTHp|

VTHn
1
Esc = (t 2 − t1 ) ⋅ I sc − MAX ⋅ VDD
2 SCI

Isc

1
Psc = aSW ⋅ (t 2 − t1 ) ⋅ I sc − MAX ⋅VDD ⋅ f clock
2
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 Static Power
• Static currents are those due to non-idealities
(“leakage”) of a transistor and occurring when it
is not switching
• Many types of static currents!
• Subthreshold current (Isub) is the most (only?)
relevant one GATE
SOURCE IG DRAIN

Igs Igb Igd

IS ID
Isub
IGIDL
Ijbs IGISL Ijbd
Iii

BULK IB
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 Sub-threshold Leakage power

Pleakage = Ileakage · VDD

• Considering sub-threshold current only:

W 2  VGS − VTHN    V DS 
I = µ 0 C ox V exp • 1 − exp − 
DS , Subth L t  nV    Vt 
 t    

Simplified Dependence:
Ids,subth = k e–Vth
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 Sources of power consumption
• In summary
- Dynamic power is mostly (>95%) switching power
but for special cases where signals are deteriorated

Pdynamic ≡ Pswitching
- Static power is mostly (>90%?) sub-threshold
• We will consider essentially sub-threshold leakage currents

Pstatic ≡ Psub-threshold

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 Leakage and technology node
• MYTH: Leakage is an issue only for deeply scaled
technologies
• TRUTH: True for power but energy?
- Duty cycle of operations is essential when evaluating
energy!!!!

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 Static vs. Dynamic power &
IoT workloads
• MCU workloads are dominated by idle time…!
- Small computational tasks (sensing, processing, actuating)
- Often long duty cycles
• Duty cycle D = Tactive/T
- No larger than 10-2, often 10-4/10-5

• Idle power of a MCU/CPU is a fundamental parameter!!!

• Notice that there are different types of ‘idleness’,
depending on what is disabled
• Ex: CC2650
- Idle/standby/shutdown currents = 0.5mA/1uA/0.15uA
- The lower, the longer the time to resume to active!
(14 μs /151 μs / 1015 μs)

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Example: STM32L4R5

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 Importance of duty cycle
Tactive T Tidle ~= Tactive

Tidle

Tactive Tidle ~10x Tactive

T
Tidle

• Relevance of static power ∝ the ratio Tidle/Tactive

• Example: 1/100 duty cycle (idle=99%)
- Pactive = 10mW
- Pidle=100µW (1/100) Eactive = Eidle!
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