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EECS 6611

Mixed-Signal Microsystem Design

Chapter 5: D/A Converters

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Overview
• Why first DACs?
• Simpler Architecture than ADCs → Not easier to design (almost the opposite)
• Not as many architectures → Pretty much one architecture with some variance.
• Not as many performance regimes
• In terms of non-idealities:
• Basic ones are very easy to describe, More advanced ones are very hard to describe
• ADCs have DACs in them, so…

• D/A conversion is accomplished through the division/multiplication of a reference voltage, current or

charge
• Architectures: (1) Thermometer, (2) Binary weighted, (3) Segmented
• Static performance → Limited by component matching
• Dynamic performance → Limited e.g. by timing errors, "glitches"
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Resistor String DAC

Simple, inherently monotonic

Small area up to ~8 bits

• See e.g. Pelgrom, JSSC 12/1990

Unsuitable for high-resolution, high-speed designs

• Higher resolution → higher R and C

Scalability (2N switches and resistors)

Variable output impedance depending on the

selected tap.

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Thermometer DAC

• Example shows switched current source

realization

Guaranteed to be monotonic

Need large encoder with 2B-1 outputs

• Impractical for large B (high resolution)

• For 10bit, 1023 current sources

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Thermometer DAC Principle

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Binary Weighted DAC

No encoder needed

Monotonicity is not guaranteed

• Consider transition 100000…. to 011111….

• 2B-1 source must match sum of others to within 1 LSB
to make transition monotonic

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Binary Weighted DAC Principle

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Segmented DAC

• Something in between
• Combine the best of both worlds.

• Binary weighted section with Bb bits

• Thermometer section with, Bt = B-Bb bits

• Typically Bt ~ 4-8

• Reasonably small encoder

• Easier to achieve monotonicity

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Segmented DAC (2-2)

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Static Errors (DNL and INL)

• What may cause DNL and INL in a DAC?
• Mostly due to unit element mismatch

• Systematic Errors
• Contact and wiring resistance (IR drop)
• Finite current source output resistance
• Process gradients
• Edge effects in unit element arrays

• Systematic errors can be mitigated by proper layout and

switching sequence design
• See e.g. [Lin, JSSC 12/98], [Van der Plas, JSSC 12/99]

• Random Errors: simply cannot combat them

• Lithography is not prefect, randomness in etching, etc.
• Often Gaussian distribution (central limit theorem)
• More info: C. Conroy et al., “Statistical Design Techniques for D/A
Converters,” IEEE JSSC, pp. 1118-28, Aug. 1989.
E.g. [Lin, JSSC 12/98], [Van der Plas, JSSC 12/99]

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Gaussian Distribution
• There are maybe 10s of different random variations
• Assuming they all are random (Gaussian) We combine all of them.

• This is nice to know, but in the end, I want to know how many of these DACs are going to “work”
• So, we need to integrate the density

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Yield

C : confidence interval
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Example
• Measurements show that the current in a production of a lot of current sources follows a Gaussian distribution
with σ = 0.1 mA and μ = 10 mA
• What fraction of current sources is within ±3% (or ± 0.3%) of the mean?

• “Coefficient of variation”

• Fraction of current sources within 3%

• C = 3 → 99.73%

• Fraction of current sources within 1%

• C = 1 → 68.27%

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DNL of Thermometer DAC

Real step

Ideal step

• σ(DNL) for each code is simply σ(ΔI), which is equal to previously

defined σu of unit elements
• If current varies by 50% ➔ my DNL=0.5LSB

• Example
Each step is independent of other steps.
• Say we have unit elements with σu = 1% and want 99.73% of all converters to
meet the spec.

• Which DNL specification value should go into the datasheet?

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DNL Yield Example

• First cut solution
• For 99.73% yield, need C = 3
• σDNL = σu = 1%
• 3 σDNL = 3%
• DNL specification for a yield of 99.73% is ±0.03 LSB
• What is wrong with this calculation?

• Not quite right

• Must keep in mind that a converter will meet specs only if all codes meet DNL spec, i.e. DNL(k) <
DNLspec for all k.
• A converter with more codes is less likely to have all codes meet the specification
• Let's see if this is significant

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DNL Yield Example

• Let's say there are N codes, and assume that all DNL(k) values are independent, then
• P(all codes meet spec) = P(single code meets spec) N

• P(all codes meet spec)1/N = P(single code meets spec)

• Lets look at two examples N=64 (~6 bits) and N=4096 (~12 bits)
• 0.99731/64 = 0.999995311…

• 0.99731/4096 = 0. 99999992674682…

• Can calculate modified confidence intervals using Matlab

• For N=64, C = sqrt(2)*erfinv(0.99731/64) = 4.09

• For N=4096, C = sqrt(2)*erfinv(0.99731/4096) = 4.97

• Refined result for 99.97% yield

• N=64: DNL spec should be ±0.0409 LSB

• N=4096: DNL spec should be ±0.0497 LSB

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DNL Yield Example

• Getting a more accurate yield estimate for the preceding example wasn't all that hard
• Unfortunately things won't always be that simple
• E.g. in a segmented DAC, DNL(k) are no longer independent

• The "typical" DAC designer tends to rely on simulations rather than trying to formulate "exact" yield
equations
• Get rough estimate using simple (often optimistic) expressions

• Run "Monte Carlo" simulations in Matlab to find actual yield or to center specs

• Still important to have a qualitative feel for what may cause discrepancies

• A more elaborate example in your homework.

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INL

Ideal output = k*average

A and B are random variables.

1 LSB - A: sum of the first k currents
- B: sum of the remaining currents.

correlated
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INL
• For a quotient of random variables

[Dennis E. Blumenfeld, Operations Research Calculations Handbook, Online:

http://www.engnetbase.com/ejournals/books/book_summary/toc.asp?id=701]
• After identifying the means (μ), variances (σ2) and covariance (cov) needed in the above
approximation, it follows that

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INL

• Standard deviation of INL is maximum at mid-scale (k=N/2)

• For a more elaborate derivation of this result see

[Kuboki et al., IEEE Trans. Circuits & Systems, 6/1982]

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Achievable Resolution

• Example: σINL= 0.1 LSB

σu B
1% 8.6
0.5% 10.6
0.2% 13.3
0.1% 15.3
• How about yield?
• Two solutions:
• Do the math
• G. I. Radulov et al., "Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch," IEEE TCAS II, pp. 146-
150, Feb. 2007.
• Good rule of thumb
• For high target yield (>95%), the probability of "all codes meet INL spec" is very close to "worst code meets INL spec"

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DNL/INL of Binary Weighted DAC

• INL same as for thermometer DAC. Why?

• DNL is not same for all codes, but depends on transition

• Consider worst case: 0111 … → 1000 …

• Turning on MSB and turning off all LSBs

• Example
• B = 12, σu = 1% → σDNL = 0.64 LSB !!!
• Much worse than thermometer DAC (0.03LSB to 0.05LSB)
• Btw, this was the worst-case code.

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σDNL (4-bit Example)

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Simulation Example
A random MATLAB run
- Gaussian distribution for all the elements
- Arrange the elements in binary weighted DAC

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Another Random Run

• Peak DNL not at mid-scale!

• Important to realize that this is just one single statistical outcome…
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Multiple Simulation Runs (100)

Looks familiar?

[Lin & Bult, JSSC 12/1998] EECS6611 - Hossein Kassiri 26

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DNL/INL of Segmented DAC

• INL Example: B=Bb+Bt=4+4=8

• Same as in thermometer DAC

• DNL
• Worst case occurs when LSB DAC turns off and
one more MSB DAC element turns on

• Essentially same DNL as a binary weighted DAC

with Bb+1 bits

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Comparison

Worst case

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Example (B=12, σu=1%)

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DAC INL/DNL Summary

• We should emphasize that all of the above is true with the assumption of
Gaussian error.
• i.e., I have removed all the systemic errors and only have random ones.

• Systematic errors and correlations are usually also important, but can be mitigated by
proper layout and switching sequence design

• See e.g. [Lin, JSSC 12/98], [Van der Plas, JSSC 12/99]

• INL is independent of DAC architecture and requires element matching

commensurate with overall DAC precision

• DAC architecture has significant impact on DNL

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Dynamic DAC Errors

• Finite settling time and slewing
• Finite RC time constant
• Signal dependent slewing

• Feedthrough
• Coupling from switch signals to DAC output
• Clock feedthrough

• Glitches due to timing errors

• Current sources won’t switch simultaneously

• Dynamic DAC errors are generally hard to model!

• References
• Gustavsson, Chapter 12
• Doris, van Roermund, Leenaerts, Wide-Bandwidth High Dynamic Range D/A Converters, Springer 2006.
• T Chen and G.G.E. Gielen, "The analysis and improvement of a current-steering DAC's dynamic SFDR," IEEE Trans. Ckts. Syst. I, Jan.
2006.

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Glitch Impulse
• DAC output waveform depends on timing
• Consider binary weighted DAC transition 0111… →1000…

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Glitch Impulse
• Worst case glitch impulse (area): ∝ Δt 2B-1
• 2B-1 is the MSB value

• LSB area (pulse energy): ∝ T (sampling/update period of the DAC)

• Need Δt 2B-1 << T which implies Δt << T/2B-1

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Commercial Example

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Current Reference Generator

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Circuit Examples

[T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, “An 80-MHz 8- bit CMOS D/A Converter,” IEEE J. of
Solid-State Circuits, pp. 983-988, Dec. 1986.]

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Circuit Examples

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Basic Differential Pair Switch

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Commonly Used Techniques

• Retiming
• Latches in (or close to) each current cell

• Latch controlled by global clock to ensure that current cells switch simultaneously (independent of decoder
delays)

• Make before break

• Ensure uninterrupted current flow, so that tail current source remains active

• Low swing driver

• Drive differential pair with low swing to minimize coupling from control signals to output

• Cascoded tail current source for high output impedance

• Ensures that overall impedance at output nodes is code independent (necessary for good INL)

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Example Current Cell Implementation

[Barkin & Wooley, JSSC 4/2004]

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High Performance DAC Examples

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High Performance DAC Examples

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Alternative DAC Realizations

• Examples
• Resistor string DAC
• Charge redistribution DAC

• Performance typically not as high as in current steering DACs

• Mostly used for auxiliary functions, or as a building block within an A/D converter

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Binary Weighted Charge Redistribution DAC

• Can redistribute charge onto OTA + feedback capacitor to mitigate gain error due to C p
• Will discuss this in more detail later.

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