Problems 53

x 0 1 1 0 0

y 0 0 1 1 0

AND: x ? y 0 0 1 0 0

OR: x 1 y 0 1 1 1 0

NOT: x9 1 0 0 1 1

FIGURE 1.5
Input–output signals for gates

A
A F 5 ABC B G5A1B1C1D
B
C C
D
(a) Three-input AND gate (b) Four-input OR gate

FIGURE 1.6
Gates with multiple inputs

instantaneously. The low level represents logic 0 and the high level logic 1. The AND
gate responds with a logic 1 output signal when both input signals are logic 1. The OR
gate responds with a logic 1 output signal if any input signal is logic 1. The NOT gate
is commonly referred to as an inverter. The reason for this name is apparent from the
signal response in the timing diagram, which shows that the output signal inverts the
logic sense of the input signal.
AND and OR gates may have more than two inputs. An AND gate with three inputs
and an OR gate with four inputs are shown in Fig. 1.6. The three-input AND gate
responds with logic 1 output if all three inputs are logic 1. The output produces logic 0
if any input is logic 0. The four-input OR gate responds with logic 1 if any input is logic
1; its output becomes logic 0 only when all inputs are logic 0.

PROBLEMS
(Answers to problems marked with * appear at the end of the text.)
1.1 List the octal and hexadecimal numbers from 5010 to 6410. Using A, B,C, and D for the last
four digits, list the numbers from 1110 to 3010 in base 14.
1.2* What is the exact number of bytes in a system that contains (a) 16K bytes, (b) 32M bytes,
and (c) 2G bytes?
1.3 Convert the following numbers with the indicated bases to decimal:
(a)* (1203)4 (b)* (5243)6
(c) (9922)14 (d) (248)9
54 Chapter 1 Digital Systems and Binary Numbers

1.4 What is the largest binary number that can be expressed with 12 bits? What are the equiva-
lent decimal, octal, and hexadecimal numbers?
1.5* Determine the base of the numbers in each case for the following operations to be correct:
(a) 67/5 = 11 (b) 15 * 3 = 51 (c) 123 + 120 = 303.
1.6* The solutions to the quadratic equation x 2 - 13x + 22 = 0 are x = 7 and x = 2. What is
the base of the numbers?
1.7* Convert the hexadecimal number CA5E to binary, and then convert it from binary to octal.
1.8 Convert the decimal number 253 to binary in two ways: (a) convert directly to binary;
(b) convert first to hexadecimal and then from hexadecimal to binary. Which method is
faster?
1.9 Express the following numbers in decimal:
(a)* (10101.101)2 (b)* (64.8)16
(c)* (261.44)8 (d) (51DE.C)16
(e) (110011.001)2
1.10 Convert the following binary numbers to hexadecimal and to decimal: (a) 1.00011,
(b) 1000.11. Explain why the decimal answer in (b) is eight times that in (a).
1.11 Perform the following division in binary: 101010 , 100.
1.12* Add and multiply the following numbers without converting them to decimal:
(a) Binary numbers 1101 and 110.
(b) Hexadecimal numbers D0 and 1F.
1.13 Perform the following conversion problems:
(a) Convert decimal 45.125 to binary.
(b) Calculate the binary equivalent of 3.33 out to four places. Then convert from binary
to decimal. Find the error percentage.
(c) Convert the binary result in (b) into hexadecimal. Then convert the result to decimal.
Is the answer the same?
1.14 Obtain the 1’s and 2’s complements of the following binary numbers:
(a) 11100010 (b) 00011000
(c) 10111101 (d) 10100101
(e) 11000011 (f) 01011000
1.15 Find the 9’s and the 10’s complement of the following decimal numbers:
(a) 65,234,035 (b) 56,783,223
(c) 87,000,367 (d) 99,999,000
1.16 (a) Find the 8’s complement of (2360)8.
(b) Convert (2360)8 to binary.
(c) Find the 2’s complement of the result in (b).
(d) Convert the answer in (c) to octal and compare with the answer in (a).
1.17 Perform subtraction on the given unsigned numbers using the 10’s complement of the
subtrahend. Where the result should be negative, find its 10’s complement and affix a minus
sign. Verify your answers.
(a) 7,523 - 4.567 (b) 230 - 1,204
(c) 224 - 712 (d) 2,390 - 945
 Problems 55

1.18 Perform subtraction on the given unsigned binary numbers using the 2’s complement of
the subtrahend. Where the result should be negative, find its 2’s complement and affix a
minus sign.
(a) 11001 - 10010 (b) 1100 - 111100
(c) 10101 - 11011 (d) 1100011 - 10001
1.19* The following decimal numbers are shown in signed-magnitude form: + 9,286 and +801.
Convert them to signed-10’s-complement form and perform the following operations
(note that the sum is + 10,627 and requires five digits and a sign).
(a) ( + 9,286) + ( +801) (b) ( + 9,286) + ( - 801)
(c) ( - 9,286) + ( +801) (d) ( -9,286) + ( -801)
1.20 Convert decimal + 49 and +29 to binary, using the signed-2’s-complement representation
and enough digits to accommodate the numbers. Then perform the binary equivalent of
( + 29) + ( - 49), ( - 29) + ( + 49), and ( -29) + ( - 49). Convert the answers back to deci-
mal and verify that they are correct.
1.21 If the numbers ( +9,742)10 and ( +641)10 are in signed-magnitude format, their sum
is ( + 10,383)10 and requires five digits and a sign. Convert the numbers to signed-10’s-
complement form and find the following sums:
(a) ( + 9,742) + ( + 641) (b) ( +9,742) + ( - 641)
(c) ( -9,742) + ( +641) (d) ( -9,742) + ( - 641)
1.22 Convert decimal 9,045 and 337 to both BCD and ASCII codes. For ASCII, an even parity
bit is to be appended at the left.
1.23 Represent the unsigned decimal numbers 609 and 516 in BCD, and then show the steps
necessary to form their sum.
1.24 Formulate a weighted binary code for the decimal digits, using the following weights:
(a)* 5, 2, 1, 1 (b) 6, 3, 2, 1
1.25 Represent the decimal number 6,428 in (a) BCD, (b) excess-3 code, (c) 2421 code, and
(d) 6311 code.
1.26 Find the 9’s complement of the decimal number 6,248 and express it in 2421 code. Show
that the result is the 1’s complement of the answer to (c) in Problem 1.25. This demon-
strates that the 2421 code is self-complementing.
1.27 Assign a binary code in some orderly manner to the 52 playing cards. Use the minimum
number of bits.
1.28 The message “Pass 0.12” is to be sent via communication line. For this, each character of
the message should be encoded into a seven-bit ASCII code including the period and the
space. Each ASCII encoded character should be then encrypted by adding binary 101 to
it. Write the expression for the message sent.
1.29* Decode the following ASCII code:
1000011 0101110 1000010 1000001 1000010 1000010 1000010 1000111 1000101.
1.30 The following is a string of ASCII characters whose bit patterns have been converted into
hexadecimal for compactness: 47 2E 5C 42 CF CF CC C5. Of the eight bits in each pair of
digits, the leftmost is a parity bit. The remaining bits are the ASCII code.
(a) Convert the string to bit form and decode the ASCII.
(b) Determine the parity used: odd or even?
56 Chapter 1 Digital Systems and Binary Numbers

1.31* How many printing characters are there in ASCII? How many of them are special char-
acters (not letters or numerals)?
1.32* What bit must be complemented to change an ASCII letter from capital to lowercase and
vice versa?
1.33* The state of a 16-bit register is 1000011101011001. What is its content if it represents
(a) Four decimal digits in BCD?
(b) Four decimal digits in the excess-3 code?
(c) Four hexadecimal digits in the Gray code?
(d) Two ASCII characters with even parity bit as the left-most bit in each byte?
1.34 (a) List the ASCII code for the 10 decimal digits with an even parity bit in the leftmost
position.
(b) Repeat (a) with odd parity.

REFERENCES
1. Cavanagh, J. J. 1984. Digital Computer Arithmetic. New York: McGraw-Hill.
2. Mano, M. M. 1988. Computer Engineering: Hardware Design. Englewood Cliffs, NJ: Pren-
tice-Hall.
3. Nelson, V. P., H. T. Nagle, J. D. Irwin, and B. D. Carroll. 1997. Digital Logic Circuit
Analysis and Design. Upper Saddle River, NJ: Prentice Hall.
4. Schmid, H. 1974. Decimal Computation. New York: John Wiley.
5. Katz, R. H. and Borriello, G. 2004. Contemporary Logic Design, 2nd ed., Upper Saddle
River, NJ: Prentice-Hall.

WEB SEARCH TOPICS

2’s complement
ASCII
BCD addition
BCD code
Binary addition
Binary codes
Binary logic
Binary numbers
Computer arithmetic
Error correction
Excess-3 code
Gray code
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Parity bit
Radix complement
Shaft encoder
Storage register
92 Chapter 2 Boolean Algebra and Logic Gates

Some CAD systems include an editing program for creating and modifying schematic
diagrams on a computer screen. This process is called schematic capture or schematic
entry. With the aid of menus, keyboard commands, and a mouse, a schematic editor can
draw circuit diagrams of digital circuits on the computer screen. Components can be
placed on the screen from a list in an internal library and can then be connected with
lines that represent wires. The schematic entry software creates and manages a database
containing the information produced with the schematic. Primitive gates and functional
blocks have associated models that allow the functionality (i.e., logical behavior) and
timing of the circuit to be verified. Verification is performed by applying inputs to the
circuit and using a logic simulator to determine and display the outputs in text or wave-
form format.
An important development in the design of digital systems is the use of a hardware
description language (HDL). Such a language resembles a computer programming
language, but is specifically oriented to describing digital hardware. It represents logic
diagrams and other digital information in textual form to describe the functionality
and structure of a circuit. Moreover, the HDL description of a circuit’s functionality
can be abstract, without reference to specific hardware, thereby freeing a designer to
devote attention to higher level functional detail (e.g., under certain conditions the cir-
cuit must detect a particular pattern of 1’s and 0’s in a serial bit stream of data) rather
than transistor-level detail. HDL-based models of a circuit or system are simulated to
check and verify its functionality before it is submitted to fabrication, thereby reducing
the risk and waste of manufacturing a circuit that fails to operate correctly. In tandem
with the emergence of HDL-based design languages, tools have been developed to
automatically and optimally synthesize the logic described by an HDL model of a cir-
cuit. These two advances in technology have led industry to an almost total reliance on
HDL-based synthesis tools and methodologies for the design of the circuits of complex
digital systems. Two HDLs—Verilog and VHDL—are widely used by design teams
throughout the world, and are standards of the Institute of Electrical and Electronics
Engineers (IEEE). Verilog and VHDL are introduced in Section 3.9, and because of
their importance, we include several exercises and design problems based on them
throughout the book. Additionally, we introduce selected features of System Verilog,
an important and more recent language, in Chapter 8. Since Verilog is embedded in
System Verilog we delay our presentation of System Verilog until a foundation has
been laid in Verilog.

PROBLEMS
Answers to problems marked with * appear at the end of the text.
2.1 Demonstrate the validity of the following identities by means of truth tables:
(a) DeMorgan’s theorem for three variables: (x + y + z)′ = x′y′z′ and (xyz)′ = x′ +
y′ + z′
(b) The distributive law: x + yz = (x + y)(x + z)
(c) The distributive law: x(y + z) = xy + xz
 Problems 93

(d) The associative law: x + (y + z) = (x + y) + z

(e) The associative law: x(yz) = (xy)z
2.2 Simplify the following Boolean expressions to a minimum number of literals:
(a)* xy + xy′ (b)* (x + y)(x + y′)
(c)* xyz + x′y + xyz′ (d)* (x + y)′(x′ + y′)′
(e) (a + b + c′)(a′ b′ + c) (f) a′bc + abc′ + abc + a′bc′
2.3 Simplify the following Boolean expressions to a minimum number of literals:
(a)* xyz + x′y + xyz′ (b)* x′yz + xz
(c)* (x + y)′(x′ + y′) (d)* xy + x(wz + wz′)
(e)* (yz′ + x′w)(xy′ + zw′) (f) (x′ + z′)(x + y′ + z′)
2.4 Reduce the following Boolean expressions to the indicated number of literals:
(a)* x′y′z′ + y + xy′z′ to two literals
(b)* x′y(x′ + z′) + x′y + xyz to three literals
(c)* (x + yz)′ + (x + y′z′)′ to one literal
(d)* (w′ + x)(w + y)(x′ + y)(w + xyz) to four literals
(e) wxy′z′ + wy′ + wx′y′z′ to two literals
2.5 Draw logic diagrams of the circuits that implement the original and simplified expressions
in Problem 2.2 (c), (e), and (f).
2.6 Draw logic diagrams of the circuits that implement the original and simplified expressions
in Problem 2.3 (a), (c), and (f).
2.7 Draw logic diagrams of circuits that implement the original and simplified expressions in
Problem 2.4 (a), (c), and (e).
2.8 Find the complement of F = x′y + yz′; then show that FF′ = 0 and F + F′ = 1.
2.9 Find the complement of the following expressions:
(a)* xyz + x′y′z′ (b) (x + y′)(y + z′)(z + x′)
(c) w′x′ + w(x + y + z)
2.10 Given the Boolean functions F1 and F2, show that
(a) The Boolean function E = F1 + F2 contains the sum of the minterms of F1 and F2.
(b) The Boolean function G = F1F2 contains only the minterms that are common to F1
and F2.
2.11 List the truth table of the function:
(a)* F = x′z′ + xy + yz (b) F = a′b′c′ + a′bc + ab′c′ + abc
2.12 We can perform logical operations on strings of bits by considering each pair of corres-
ponding bits separately (called bitwise operation). Given two eight-bit strings A = 11001010
and B = 10010011, evaluate the eight-bit result after the following logical operations:
(a)* AND (b) OR (c)* XOR (d)* NOT A (e) NOT B
2.13 Draw logic diagrams to implement the following Boolean expressions:
(a) F = (u + x′)(y′ + z)
(b) F = (u ⊕ y)′ + x
(c) F = (u′ + x′)(y + z′)
(d) F = u(x ⊕ z) + y′
(e) F = u + yz + uxy
(f) F = u + x + x′(u + y′)
94 Chapter 2 Boolean Algebra and Logic Gates

2.14 Implement the Boolean function

F = x′y + xy′ + xz

(a) With AND, OR, and inverter gates.

(b)* With OR and inverter gates.
(c) With AND and inverter gates.
(d) With NAND and inverter gates.
(e) With NOR and inverter gates.
2.15* Simplify the following Boolean functions T1 and T2 to a minimum number of literals:

A B C T1 T2
0 0 0 0 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 0 0
1 1 1 1 1

2.16 The logical sum of all minterms of a Boolean function of n variables is 1.

(a) Prove the previous statement for n = 3.
(b) Suggest a procedure for a general proof.
2.17 Obtain the truth table for the following four-variable functions, and express each function
in sum-of-minterms and product-of-maxterms form:
(a)* (ac + b)(ab + d) (b) (a′ + c′ + d′)(ab + cd)
(c) (b + c′d′)(a + bc′) (d) a′b′c′ + acd + ab′d′ + b′cd
2.18 For the Boolean function

F = w′xy + w′yz + wy′z + w′y′z + xy

(a) Obtain the truth table of F and represent it as the sum of minterms.
(b) Draw the logic diagram, using the original Boolean expression.
(c)*Use Boolean algebra to simplify the function to a minimum number of literals.
(d) Obtain the function F as the sum of minterms from the simplified expression and
show that it is the same as the one in part (a).
(e) Draw the logic diagram from the simplified expression, and compare the total number
of gates with the diagram of part (b).
2.19* Express the following function as a sum of minterms and as a product of maxterms:

F(A, B, C, D) = AB′ + BC + ACD′

2.20 Express the complement of the following functions in sum-of-minterms form:
(a) F(w, x, y, z) = Σ(1, 5, 7, 11, 12, 14, 15)
(b) F(x, y, z) = Π(2, 4, 5)
 Problems 95

2.21 Convert each of the following to the other canonical form:

(a) F(x, y, z) = Σ (2, 3, 5, 7)
(b) F(A, B, C, D) = Π(1, 2, 3, 5, 8, 13)
2.22* Convert each of the following expressions into sum of products and product of sums:
(a) (w + xy′)(x + y′z)
(b) xy + (w′ + y′z′)(z′ + x′y′)
2.23 Draw the logic diagram corresponding to the following Boolean expressions without sim-
plifying them:
(a) A′B + A′B′C + B′C
(b) (w′ + x)(x + y)(w + z′)
(c) (A + B)(B′ + C′) + AD
(d) w′x′y′ + wx(y + z)
2.24 Find the dual of the expression: x′y + (x + z)(x + y′).
2.25 By substituting the Boolean expression equivalent of the binary operations as defined
in Table 2.8, show the following:
(a) The inhibition operation is neither commutative nor associative.
(b) The exclusive-OR operation is commutative and associative.
2.26 Show that a positive logic NAND gate is a negative logic NOR gate and vice versa.
2.27 Write the Boolean equations and draw the logic diagram of the circuit whose outputs are
defined by the following truth table:

Table P2.27
f1 f2 a b c
1 1 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
1 0 1 0 0
0 1 1 0 1
1 0 1 1 1

2.28 Write Boolean expressions and construct the truth tables describing the outputs of the
circuits described by the logic diagrams in Fig. P2.28.
a
y1
a
b
b
c
c y
d y2
d
e
e
f
(a) (b)
FIGURE P2.28
96 Chapter 2 Boolean Algebra and Logic Gates

2.29 Determine whether the following Boolean equation is true or false.

a′d′ + b′c′ + c′d′ = (a′ + c′)(b′ + d′)(c′ + d′)

2.30 Write the following Boolean expressions in sum of products form:

(w + x + y)(x′ + y′ + z′)
2.31 Write the following Boolean expression in product of sums form:
ab + bc + a′b′c′
2.32* By means of a timing diagram similar to Fig. 1.5, show the signals of the outputs f and g in
Fig. P2.32 as functions of the three inputs a, b, and c. Use all eight possible combinations
of a, b, and c.

a b c

FIGURE P2.32

2.33 By means of a timing diagram similar to Fig. 1.5, show the signals of the outputs f and g in
Fig. P2.33 as functions of the two inputs a and b. Use all four possible combinations of a
and b.

a b

FIGURE P2.33

REFERENCES
1. Boole, G. 1854. An Investigation of the Laws of Thought. New York: Dover.
2. Dietmeyer, D. L. 1988. Logic Design of Digital Systems, 3rd ed., Boston: Allyn and Bacon.
3. Huntington, E. V. Sets of independent postulates for the algebra of logic. Trans. Am. Math.
Soc., 5 (1904): 288–309.