Galgotias College of Engineering and Technology

1, Knowledge Park-II, Greater Noida, Uttar Pradesh, 201310

BEC 302-DIGITAL SYSTEM DESIGN

IMPORTANT TOPICS

CO’S IMPORTANT TOPIC

CO1 1. Boolean algebra and Demorgans theorem,
2. SOP & POS forms,
3. Canonical forms, Karnaugh maps up to 5 variables,
4. Tabulation method.
CO2 1. Multiplexers, de-multiplexers,
2. encoder, decoder,
3. circuit realization using Multiplexers,
4. BCD adder, Comparator
CO3 1. Flip flop conversion, Master-Slave JK FF,
2. counters (especially UP/Down counter),
3. Universal shift register,
4. State diagrams, state reduction,
5. Analysis of clocked sequential circuits, Design of clocked sequential
circuits
CO4 1. TTL NAND gate, noise margin, propagation delay, fan-in, fan-out,
2. CMOS families,
3. FPGA,
4. logic implementation using programmable devices (PLA,PAL,PROM)
CO5 1. ADC Types: dual slope, successive approximation, counting type,
flash type ADC,
2. DAC: Weighted resistor, R- 2R ladder
 Galgotias College of Engineering and Technology
1, Knowledge Park-II, Greater Noida, Uttar Pradesh, 201310

BEC 302-DIGITAL SYSTEM DESIGN

IMPORTANT QUESTIONS

CO’S IMPORTANT QUESTIONS

CO1 1. Simplify the following switching functions using Karnaugh map
method and realize expression using gates F(A,B,C,D) =
Σ(0,3,5,7,8,9,10,12,15).
2. Simplify the following switching functions using Quine McCluskey's
tabulation method and realize expression using gates F(A,B,C,D) =
Σ(0,5,7,8,9,10, 11, 14,15).
3. Reduce the expression using 5-VARIABLE K-MAP method F(x1, x2,
x3, x4, x5) = ∑m (0, 2, 4, 5, 6, 7, 8, 10, 14, 17, 18,
21, 29, 31) + ∑d (11, 20, 22).
4. Simply the following Boolean expression in (i) sum of product (ii)
product of sum using k-map AC’+B’D+A’CD+ABCD
5. Reduce the following using tabulation method:
F=m2+m3+m4+m6+m7+m9+m11+m13.
6. Find the minimum SOP expression using K-map for the function:
f= ∑m (7, 9, 10, 11, 12, 13, 14, 15) and realize the minimized
function using only NAND gates.
7. Prove the following (A+B) ((AC)’+C) (B’+AC)’=A’B.
CO2 1. Design 2-bit magnitude comparator.
2. Implement the following Boolean functions with a multiplexer:
F(w,x,y,z)= ∑(2,3,5,6,11,14,15)
3. Construct a 5 to 32 line decoder using 3 to 8 line decoders and 2 to 4
line decoder.
4. Design a 4-bit adder / Subtractor using logic gates and explains its
operation.
5. Design the Binary to Gray code convertor, BCD to Excess-3
6. Design a combinational circuit to perform BCD addition.

7. Using 8 to 1 multiplexer, realize the Boolean function: T = f(w, x, y,

z) = Σ(0,1,2,4,5,7,8,9,12,13)
8. Explain priority encoder and its need.

CO3 1. Design a binary counter using T flip flops to count in the following
sequences:
(i) 000, 001, 010, 011, 100, 101, 111, 000

(ii) 000, 100, 111, 010, 011, 000

2. Design three bit synchronous up counter with T flip flop and draw the
diagram.
3. A sequential circuit with two D flip-flops A and B, one input x and
one output z is specified by the following next-state and output
equations:
A(t+1)= A′+B, B(t+1)=B′x, z=A+B′
 i) Draw the logic diagram of the circuit
ii) Draw the state table
iii) Draw the state diagram of the circuit
4. Explain the difference between a state table, characteristics table and
excitation table.
5. Explain master slave flip flop & universal shift register.
6. What are the steps in the analysis and design of asynchronous
sequential circuits? Explain with an example.
7. Explain Universal Shift Register with the help of logic diagram.
8. Design the 3-bit down counter using T flip flop

CO4 1. Implement the following two Boolean functions with a PLA

F1=AB′+AC+A′BC′ F2=(AC+BC)′
2. a) Explain the architecture of FPGA.
b) Explain the TTL NAND gate principle of operation and list out the
advantage.

3. Design full adder using PROM

4. Implement the following functions
F1(A,B,C,D)=∑m (1,3,4,5,9,11,12,14),
F2(A,B,C,D)=∑m(1,3,4,6,9,11,12,14,15) ,
F3(A,B,C,D)=∑m(0,2,4,6,8,12),
F4(A,B,C,D)=∑m (2,3,8,9,12,13) using PAL.
5. A computer uses RAM chips of 1024*1 capacity.
6. How many chips are needed and how should their address lines be
connected to provide a memory capacity of 1024 bytes.
How many chips are needed to provide a memory capacity of
16kbytes? Explain in words how the chips are to be connected.
7. With the help of a neat diagram, explain the working of any two of
below:
i. A CMOS Inverter.
ii. A Two input CMOS NAND gate.
CO5 1. Why Dual slope ADC having less performance than other ADC.
Explain the operation for 3-bit data.
2. Design N-Bit binary weighted resister DAC and explain the concept
for 2-bit data.
3. Why Successive Approximation ADC having high performance than
other ADC. Explain the operation for 3-bit data with algorithm.
4. Design N-Bit R-2R ladder DAC and explain the concept for 3-bit
data.
5. Design N-Bit Parallel or Flash ADC and explain the concept for 3-bit
data.
6. Design the counter type ADC & derive the equation of Vo.