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Assignment1

The assignment requires students to implement a specified Boolean function using various logic gate configurations, including NAND and NOR gates, as well as SUM of Products and Product of Sums. Each group must demonstrate their work on January 21, 2025, with grading based on correctness, design quality, and organization. Students must upload a report detailing their design process, a diagram, and a photo of the breadboard circuit as a single PDF file.

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4 views

Assignment1

The assignment requires students to implement a specified Boolean function using various logic gate configurations, including NAND and NOR gates, as well as SUM of Products and Product of Sums. Each group must demonstrate their work on January 21, 2025, with grading based on correctness, design quality, and organization. Students must upload a report detailing their design process, a diagram, and a photo of the breadboard circuit as a single PDF file.

Uploaded by

subhamyadav1921
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CS224: Assignment 1

Weightage: 5%

Date of Demonstration: 21st January 2025 Lab Timing (2PM-5PM)

Problem Statement:

Implement the following Boolean function using Breadboard, ICs and Hookup Wires. You are allowed to
any gate ICs.

1. F(A, B, C, D) = ∑ (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) using only 2-input NAND gates for Groups 1 to 8
2. F(A, B, C, D) = ∑(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) using only 2-input NOR gates for Groups 9 to 16
3. F(A, B, C, D) = ∑(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) using SUM of Product implementation for Groups 17 to 24
4. F(A, B, C, D) = ∑(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) using Product of SUM implementation for Groups 25 to 31

Guidelines:

• All the member of the group need to be present at the time of Demonstration of the assignment.
All the absent members will be awarded 0 marks for the assignment. Please show your ID card at
the time of demonstration (as it is difficult to remember faces of all the 123 students of your
batch).
• Grading will be based on (a) Correctness, (b) Quality of design, (c) Wire optimization, (d) Optimum
number of chip used, (e) Cleanliness in design (Wire and Chips should be organized to look good),
(f) Use of proper Comment/Naming/Labeling of the wires and (g) Questionnaire and explanation.
• Please show a clear diagram of your design to the Tas.

Support:

• Breadboard and required ICs will be issued my Mr. Hemanta Nath (Hardware Lab in Charge). You
are not allowed to take Breadboard out of the Hardware Lab. You have to carry out the entire
Breadboard Assignment in the Lab.

Upload:
Upload a report (i) describing the process to obtained the design, (ii) a clear diagram of the design
(hand drawn is fine) (ii) a picture of the circuit in the breadboard that you have done. Submit is as a single
PDF file.

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