Node Architecture

The Processor Subsystem

 The processor subsystem
 interconnects all the other subsystems and some additional
peripheries
 its main purpose is to execute instructions pertaining to sensing,
communication, and self-organization
 It consists of
 processor chip
 nonvolatile memory - stores program instructions
 active memory - temporarily stores the sensed data
 internal clock
 Microcontroller
 Structure of microcontroller
 integrates the following components:
 CPU core
 volatile memory (RAM) for data storage
 ROM, EPROM, EEPROM, or Flash memory
 parallel I/O interfaces
 discrete input and output bits
 clock generator
 one or more internal analog-to-digital converters
 serial communications interfaces
 Microcontroller
 Advantages:
 suitable for building computationally less intensive, standalone
applications, because of its compact construction, small size, low-
power consumption, and low cost
 high speed of the programming and eases debugging, because of the
use of higher-level programming languages
 Disadvantages:
 not as powerful and as efficient as some custom-made processors
(such as DSPs and FPGAs)
 some applications (simple sensing tasks but large scale deployments)
may prefer to use architecturally simple but energy- and cost-efficient
processors
 Digital Signal Processor
 The main function:
 process discrete signals with digital filters
 filters minimize the effect of noise on a signal or enhance or modify
the spectral characteristics of a signal
 while analog signal processing requires complex hardware
components, digital signal processors (DSP) requires simple adders,
multipliers, and delay circuits
 DSPs are highly efficient
 most DSPs are designed with the Harvard Architecture
 Digital Signal Processor
 Advantages:
 powerful and complex digital filters can be realized with commonplace
DSPs
 useful for applications that require the deployment of nodes in harsh
physical settings (where the signal transmission suffers corruption due
to noise and interference and, hence, requires aggressive signal
processing)
 Disadvantage:
 some tasks require protocols (and not numerical operations) that
require periodical upgrades or modifications (i.e., the networks should
support flexibility in network reprogramming)
 Application-specific Integrated Circuit
 ASIC is an IC that can be customized for a specific application
 Two types of design approaches: full-customized and half-
customized
 full-customized IC:
 some logic cells, circuits, or layout are custom made in
order to optimize cell performance
 includes features which are not defined by the standard
cell library
 expensive and long design time
 half-customized ASICs are built with logic cells that are available in the
standard library
 in both cases, the final logic structure is configured by the end user -
an ASIC is a cost efficient solution, flexible, and reusable
 Application-specific Integrated Circuit
 Advantages:
 relatively simple design; can be optimized to meet a specific customer
demand
 multiple microprocessor cores and embedded software can be
designed in a single cell

 Disadvantage:
 high development costs and lack of re-configurability
 Application:
 ASICs are not meant to replace microcontrollers or DSPs but to
complement them
 handle rudimentary and low-level tasks
 to decouple these tasks from the main processing
subsystem
Field Programmable Gate Array (FPGA)
 The distinction between ASICs and FPGAs is not always clear
 FPGAs are more complex in design and more flexible to program
 FPGAs are programmed electrically, by modifying a packaged part
 programming is done with the support of circuit diagrams and
hardware description languages, such as VHDL and Verilog
Field Programmable Gate Array (FPGA)
 Advantages:
 higher bandwidth compared to DSPs
 flexible in their application
 support parallel processing
 work with floating point representation
 greater flexibility of control
 Disadvantages:
 complex
 the design and realization process is costly
 Comparison
 Working with a micro-controller is preferred if the design goal
is to achieve flexibility
 Working with the other mentioned options is preferred if
power consumption and computational efficiency is desired
 DSPs are expensive, large in size and less flexible; they are
best for signal processing, with specific algorithms
 FPGAs are faster than both microcontrollers and digital signal
processors and support parallel computing; but their
production cost and the programming difficulty make them
less suitable
 Comparison
 ASICs have higher bandwidths; they are the smallest in size,
perform much better, and consume less power than any of the
other processing types; but have a high cost of production
owing to the complex design process
 Communication Interfaces
 Fast and energy efficient data transfer between the
subsystems of a wireless sensor node is vital
 however, the practical size of the node puts restriction on system
buses
 communication via a parallel bus is faster than a serial transmission
 a parallel bus needs more space
 Therefore, considering the size of the node, parallel buses are
never supported
 Communication Interfaces
 The choice is often between serial interfaces :
 Serial Peripheral Interface (SPI)
 General Purpose Input/Output (GPIO)
 Secure Data Input/Output (SDIO)
 Inter-Integrated Circuit (I2C)
 Among these, the most commonly used buses are SPI and I2C
 Serial Peripheral Interface
 SPI (Motorola, in the mid-80s)
 high-speed, full-duplex synchronous serial bus
 does not have an official standard, but use of the SPI interface should
conform to the implementation specification of others - correct
communication
 The SPI bus defines four pins:
 MOSI (MasterOut/SlaveIn)
• used to transmit data from the master to the slave when a
device is configured as a master
 MISO (MasterIn/SlaveOut)
 SCLK (Serial Clock)
• used by the master to send the clock signal that is needed to
synchronize transmission
• used by the slave to read this signal synchronize transmission
 CS (Chip Select) - communicate via the CS port
 Inter-Integrated Circuit
 Every device type that uses I2C must have a unique address
that will be used to communicate with a device
 In earlier versions, a 7 bit address was used, allowing 112
devices to be uniquely addressed - due to an increasing
number of devices, it is insufficient
 Currently I2C uses 10 bit addressing
 I2C is a multi-master half-duplex synchronous serial bus
 only two bidirectional lines: (unlike SPI, which uses four)
 Serial Clock (SCL)
 Serial Data (SDA)
 Inter-Integrated Circuit
 Since each master generates its own clock signal,
communicating devices must synchronize their clock speeds
 a slower slave device could wrongly detect its address on the SDA line
while a faster master device is sending data to a third device
 I2C requires arbitration between master devices wanting to
send or receive data at the same time
 no fair arbitration algorithm
 rather the master that holds the SDA line low for the longest time wins
the medium
 Inter-Integrated Circuit
 I2C enables a device to read data at a byte level for a fast
communication
 the device can hold the SCL low until it completes reading or sending
the next byte - called handshaking
 The aim of I2C is to minimize costs for connecting devices
 accommodating lower transmission speeds
 I2C defines two speed modes:
 a fast-mode - a bit rate of up to 400Kbps
 high-speed mode - a transmission rate of up to 3.4 Mbps
 they are downwards compatible to ensure communication with older
components
 Comparison
SPI I2 C
2 lines reduce space and simplify circuit layout;
4 lines enable full-duplex transmission
Lowers costs
Addressing enables multi-master mode; Arbitration is
No addressing is required due to CS
required
Allowing only one master avoids conflicts Multi-master mode is prone to conflicts
Hardware requirement support increases with an Hardware requirement is independent of the number of
increasing number of connected devices -- costly devices using the bus
The master's clock is configured according to the
Slower devices may stretch the clock -- latency but
slave's speed but speed adaptation slows down the
keeping other devices waiting
master.
Speed depends on the maximum speed of the slowest
Speed is limited to 3.4 MHz
device
Heterogeneous registers size allows flexibility in
Homogeneous register size reduces overhead
the devices that are supported.
Combined registers imply every transmission should Devices that do not read or provide data are not
be read AND write forced to provide potentially useless bytes
The absence of an official standard leads to Official standard eases integration of devices since
application specific implementations developers can rely on a certain implementation