boost
boost
AIM: To design dc-dc boost converter by step-by-step mathematical modelling using MATLAB/SIMULINK.
Description VALUE
NOMINAL POWER RATING AT CCM 500W
INPUT VOLTAGE 100V
OUTPUT VOLTAGE 250V
SWITCHING FREQUENCY 5 kHz
PEAK TO PEAK RIPPLE OF INDUCTOR 20%
CURRENT
PEAK TO PEAKRIPPLE OF CAPACITOR 2%
VOLTAGE
D=1-(Vin/Vout)
3. Switching Frequency:
Select the desired switching frequency (fs) for the boost converter. This frequency affects the
component values and overall performance.
4. Inductor Selection:
Determine the inductance value (L) based on the desired ripple current (ΔI) and switching
frequency (fs). The ripple current depends on the load and allowable current ripple.
𝛥𝐼 =(Vin) D
L∗fs
For boundary condition:
IL|min = IL-( ΔIL/2 ) = 0
For R=125Ω
𝐼O = 2𝑎𝑚𝑝
𝑠𝑜 𝛥𝐼L = 1A
and L = 12mH
5. Capacitor Selection:
Calculate the capacitor value (C) based on the desired output voltage ripple (ΔV) and switching
frequency (fs). The output voltage ripple depends on the load and allowable voltage ripple.
𝛥Vo=(Io*DT)/C
C = 48uF
1/(1-D)= 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛
2. Inductor Current (IL):
IL(t)=IC(t)-IO
IL|min=IL-( ΔIL/2 )
IL|min=IL+( ΔIL/2 )
4. Switching Losses:
D ∗ R ∗ (1 − 𝐷)2
𝐿𝑐 =
2 ∗ fs
critical inductance is 1.2mH. Since, L is chosen as 12mH which is greater than the critical inductance, the converter always
operates in continuous conduction.
Critical Capacitance:
(ΔVo/2) = Vo
𝐷
𝐶𝑐 =
2 ∗ 𝑓𝑠 ∗ 𝑅
Based on values in Table 1, critical capacitance is 0.48uF. Since, C is chosen as 48uF which is greater than the critical
capacitance, the converter always operates in continuous conduction.
CIRCUIT DIAGRAM
MATHEMATICAL MODELLING
Mathematical modelling of a boost converter involves deriving the differential equations that describe the
behaviour of the inductor and capacitor in both the ON and OFF states of the switches. Here is a detailed
explanation of the mathematical modelling process:
1. ON State Modelling:
𝑉𝑠
Output voltage is equal to the capacitor voltage, i.e., 𝑉𝑜𝑢𝑡(𝑎𝑣𝑔) = 𝑉𝑐 =
1−𝐷
∆𝑉𝑜𝑢𝑡 2
𝑉𝑜𝑢𝑡,𝑟𝑚𝑠 = √𝑉𝑜𝑢𝑡,𝑎𝑣𝑔 2 +
2 ∗ √3
𝑉𝑜𝑢𝑡
𝐼𝑜𝑢𝑡(𝑎𝑣𝑔) =
R
𝑉𝑜𝑢𝑡
𝐼𝐿(𝑎𝑣𝑔) =
R ∗ (1 − D)
3. Simulated Mathematical Model of Boost converter:
4. Output waveforms.
ANALYSIS:
By observing the above waveforms we are get nearly the value that we got in our paper calculation of
mathematical model of boost converter. In this we are considering every elements of the circuit is ideal
and so we are getting calculations near to the values we calculated.
For given design parameters we calculated the respective R,L,C and that values are giving the correct
waveshape that we are expecting and so this indicates our design is correct.
During Transients, ouptput voltage and output current are getting initial spike and settling to stead state
with some ripple which is very small that we can neglect usually as we do small ripple approximation in
our pen and paper.
NON IDEALITIES:
CASE 1: Inductor alone is practical element where other elements are Ideal
On state:
VL + iL.rL = Vin
Ic= -IO
Off state:
Ic=IL-IO
𝑉𝑑𝑐
Output voltage is equal to the capacitor voltage, i.e., 𝑉𝑜𝑢𝑡 = 𝑉𝑐 = 𝑟
1−𝐷+
𝑅(1−𝐷)
∆𝐼𝐿
𝐼𝐿,𝑚𝑎𝑥 = 𝐼𝐿,𝑎𝑣𝑔 +
2
∆𝐼𝐿
𝐼𝐿,𝑚𝑖𝑛 = 𝐼𝐿,𝑎𝑣𝑔 −
2
TRANSIENT CONDITION:
ANALYSIS:
Due to this non ideality we can observe that drop in inductor due to resistance give visible drop in the output voltage
and this affect the output current also which we can see in the waveforms.
• The change due to parasitic inductor in gain vs duty cycle graph is shown above we can observe
gain drop for respective duty cycle with increase of resistance.
Vo VS D:
• We can observe similar change as like gain vs d graph, this is because input voltage is anyway constant so the
changes are only due to output voltage.
IL VS D:
• As duty cycle increases current through inductor also increases, this is what through formula also we
are expecting. Parasitic resistance cause drop of current for respective duty cycle.
ideal rL=0.5ohm rL=1ohm
Efficiency Eff Eff1 Eff2
Power loss Ploss Ploss1 Ploss2
Power output Po Po1 Po2
Po Vs Efficiency:
• The change due to parasitic inductor in output power(Po)vs Efficiency graph is shown above we can
observe there is drop of efficiency for respective power as we increase the parasitic resistance.
Ploss VS Po:
• Power loss will increase with increase in inductor parasitic resistance for respective output power which we
observe in above graph.
CASE 2: Capacitor alone is non ideal whereas every other elements are ideal.
On state:
VL = - Vout
Ic = -Io
Off state:
VL = Vin - Vout
Ic=IL-IO
Vout=Vc+icrc
where Ic is capacitor current, rc is the equivalent series resistance of the output capacitor.
𝑉𝑜𝑢𝑡
𝐼𝑜𝑢𝑡 =
R
∆𝐼𝐿
𝐼𝐿,𝑚𝑎𝑥 = 𝐼𝐿,𝑎𝑣𝑔 +
2
∆𝐼𝐿
𝐼𝐿,𝑚𝑖𝑛 = 𝐼𝐿,𝑎𝑣𝑔 −
2
Efficiency/Power loss
As ESR of capacitor increases, there is very minimal drop in the output voltage and therefore a small reduction
of efficiency. However, beyond a duty cycle, the output voltage is not boosted and hence efficiency reduces
drastically
With above equations we are forming an mathematical model for a given non ideality condition
TRANSIENT CONDITION:
ANALYSIS:
Here we can observe that output voltage and capacitor voltage are not same. Output voltage is higher
than a capacitor voltage and capacitor current also reduced a little which we can observe in waveforms
The change due to parasitic capacitor in gain vs duty cycle graph is shown above we can observe as
voltage drop increases with increase of resistance which impacted the graph.
Vo vs D:
• We can observe similar change as like gain vs d graph, this is because input voltage is anyway constant so the
changes are only due to output voltage
IL VS D:
• As duty cycle increases current through inductor also increases, this is what through formula also we
are expecting. Parasitic resistance cause drop of current for respective duty cycle .
ideal rc=2ohm rc=3ohm
Efficiency Eff Eff1 Eff2
Power loss Ploss Ploss1 Ploss2
Power output Po Po1 Po2
Po vs Efficiency:
• The change due to parasitic capacitor in output power(Po)vs Efficiency graph is shown above we
can observe there is drop of efficiency for respective power as we increase the parasitic resistance.
Ploss VS Po:
• As we can observe above that drop increases for respective power with the increase of parasitic
resistance of capacitor.
CASE 3:
both switch and diode are considered to be non ideal and rest all elements are ideal
On state:
VL = - Vout -ilrsw-Vsw
Ic = -Io
Off state:
Ic=IL-IO
𝑉𝑜𝑢𝑡
𝐼𝑜𝑢𝑡 =
R
∆𝐼𝐿
𝐼𝐿,𝑚𝑎𝑥 = 𝐼𝐿,𝑎𝑣𝑔 +
2
∆𝐼𝐿
𝐼𝐿,𝑚𝑖𝑛 = 𝐼𝐿,𝑎𝑣𝑔 −
2
With above equations we are forming mathematical model for given non ideality
TRANSIENT CONDITION:
ANALYSIS:
Here we can see that output voltage get decreased due to drops which in turn affects output current and also we can
observe that diode voltage and switch voltage are non-zero when on state which implies practical behaviour of it
which we observe in above waveforms.
Gain vs D:
• By observing above gain vs duty cycle graph there is a drop in gain for respective duty cycle while increasing
the on voltage and resistance of switch and diode.
Vo vs D:
• We can observe similar change as like gain vs d graph, this is because input voltage is anyway constant so the
changes are only due to output voltage
IL VS D:
• Duty cycle increases current through inductor also increases. ON voltage and resistance of switch
and diode cause drop of current for respective duty cycle which we can observe in above graph.
ideal Vsw, vd=1v, Vsw, vd=2v,
rsw, rd=0.1ohm rsw, rd=0.2ohm
Efficiency Eff Eff1 Eff2
Power loss Ploss Ploss1 Ploss2
Power output Po Po1 Po2
Po VS Efficiency:
• By observing above graph, Efficiency drop for respective (Po)output power by increasing the on
voltage and resistance of both switch and diode.
Ploss VS Po :
• Power loss(Ploss) for respective output power(Po) will increase with increase in ON voltage and
resistance of both diode and switch which we can observe in above graph.
Conclusion:
In this simulation , we have seen Ideal behaviour of boost converter by considering every elements
ideal for particular design values and included non idealities one by one.
In each case we analysed the waveforms and understood the behaviour of converter with each non-
ideality separately with same set of values through waveforms and in practical case we have all these
non idealities in our converter circuit.