Embedded System Unit 4
Embedded System Unit 4
RISC CISC
Lesser no. of instructions Greater no. of Instructions
Instruction Pipelining and increased execution Generally no instruction pipelining feature
speed
Orthogonal Instruction Set (Allows each instruction Non Orthogonal Instruction Set (All instructions
to operate on any register and use any addressing are not allowed to operate on any register and
mode) use any addressing mode. It is instruction
specific)
Operations are performed on registers only, the Operations are performed on registers or
only memory operations are load and store memory depending on the instruction
Large number of registers are available Limited no. of general purpose registers
Programmer needs to write more code to execute a . A programmer can achieve the desired
task since the instructions are simpler ones functionality with a single instruction which in
turn provides the effect of using more simpler
single instructions in RISC
Single, Fixed length Instructions Variable length Instructions
Less Silicon usage and pin count More silicon usage since more additional
decoder logic is required to implement the
complex instruction decoding.
With Harvard Architecture Can be Harvard or Von-Neumann Architecture
o PLDSs do not require long lead times for prototype or production-the PLDs are already on a distributor‟s
self and ready for shipment
o PLDs do not require customers to pay for large NRE costs and purchase expensive mask sets
o PLDs allow customers to order just the number of parts required when they need them. allowing them to
control inventory.
o The manufacturers able to add new features or upgrade the PLD based products that are in the field by
uploading new programming file