VLSI TECHNOLOGY (20ECE31 )

Dr.P.Anuradha
Associate Professor
ELECTRONICS & COMMUNICATION ENGINEERING
Chaitanya Bharathi Institute of Technology (A)

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Syllabus

UNIT-II : Silicon Wafer Preparation: Electronic Grade Silicon, CZ and FZ Methods of Single Crystal Growth, Silicon
Shaping, Mechanical Operations, Chemical Operations.
Wafer-Cleaning Technology: Introduction, basic concepts of wafer cleaning, Wet-cleaning technology, Dry-cleaning
technology.

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Silicon Wafer Preparation
1. Preparation of MGS and EGS
2. Crystal Growth and Doping
3. Ingot Trimming and Surface Grinding
4. Ingot slicing
5. Etching
6. Polishing
7. Wafer Cleaning

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Raw material and Purification
• The Integrated circuits are fabricated with silicon. To fabricate devices, silicon must be in
crystalline form without any defects.
• Fortunately, Silicon is a very abundant material, representing about 25.7% of the earth’s crust.
• Naturally occurring minerals containing silicon are very impure, however, which means that the
silicon must be refined as well as be converted into the crystalline form.
• This is usually a multistage process, beginning with a quartzite, a type of sand.
• Chemically quartzite is SiO₂.
• The first step in the refining process is to convert that quartzite to Metallurgical-grade silicon
(MGS) which is around 98-99% pure.
• The MG-Si is further purified through a chemical process called the Siemens process, where it
is reacted with hydrogen chloride (HCl) to form trichlorosilane (SiHCl₃). This compound is then
purified through distillation and reduced to high-purity silicon (around 99.9999%) using
hydrogen is called Electronic-Grade Silicon (EG-Si) .

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5
Raw material preparation

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Electronic-Grade Silicon (EGS)

• EGS, a poly crystalline material of high purity, is the raw material for the
preparation of single crystal silicon.
• EGS is one of the purest materials routinely available.
• The major impurities are boron, carbon, and residual donors - are critical
in affecting the electrical properties of silicon.
• Pure EGS generally requires that doping elements be in the parts per
billion (ppb) range, and carbon be less than 2 parts per million (ppm).
These properties are usually evaluated on test ingots rather than measured
on the material itself.
Electronic-grade silicon (EGS)
• To obtain Electronic Grade Silicon (EGS), which is the pure silicon used
as the base material for semiconductor devices, a multistep process is
involved. This process is crucial because the purity of silicon significantly
impacts the performance of integrated circuits (ICs) and other
semiconductor devices.
• The first step in the refining process is to convert quartzite to MGS.
• This process usually takes place in a furnace in which a mixture of the
quartzite and carbon ( in the form of coal, coke, and wood chips) is
heated to temperatures approaching 2000 °C is shown in figure 1.
• The power source for the furnace is electric, provided by submerged
electrodes, which arc and heat the charge (the mixture of silica and carbon).
• A number of reactions takes place in the furnace, the overall result of
which is that liquid silicon is drawn off and CO is given off as a gas as
shown below.
• Significant amounts of electric power are required to drive this process.
Figure 1 : Schematic of a submerged electrode arc furnace for the
production of MGS
Figure 1 : Schematic of a submerged electrode arc furnace for the
production of MGS
• The MGS that results is about 98%pure, with aluminium and iron being
two dominant impurities.
• It is estimated that for the production of one metric ton (1,000 kg) of MGS
requires 2500 - 2700 kg quartzite, 600 kg charcoal, 600 - 700 kg coal or
coke, 300 - 500 kg wood chips, and 500,000 kWh of electric power.
• Currently, approximately 0.5million metric tons of MGS are produced per
year, worldwide.
• Most of the production (70%) is used for metallurgical applications (e.g.,
aluminium-silicon alloys) from whence its name is derived.
• To convert the MGS to EGS, several steps are required.
• In the first of these the MGS reacts with gaseous HCl, usually by grinding the MGS to a
fine powder and then reacting it in the presence of a catalyst at elevated temperatures.

• This reaction takes place in a fluidized bed at a nominal temperatures at 300 °C using a
catalyst.
• This process can form any of a number of SiHCl (silyl chloride) compounds (such as
SiH4 – silane, SiH3Cl – chlorosilane, SiH2Cl – dichlorosilane, SiHCl3 -trichlorosilane, and
SiCl4- silicon tetrachloride).
• The formation of SiHCl3 is most commonly used today. SiHCl3 is liquid at room
temperature , so it can be purified by fractional distillation.
• In this process, the SiHCl3 is boiled along with the impurities it contains and separated
by its boiling point.
• After this process, the SiHCl3 is extremely pure and is ready to be converted back to
purified polysilicon.
• This is accomplished in a large chemical vapor deposition (CVD) reactor using
following equation.
•

• This reaction is conducted in the type of system shown in figure 2.

• A thin silicon rod is used as the nucleation surface, on which the silicon deposits.
• Since the rod is not a single crystal, polysilcon is deposited. The rod is heated by
passing an electric current through it.
• The polysilcon, which is deposited, may be several meters long and several hundred mm
in diameter.
• The overall deposition can take many days.
• Finally, the resulting polysilcon is broken up into pieces to load into crucibles for
Czochralski crystal growth.
Figure 2 : Schematic of a CVD reactor used for EGS production
Electronic-grade silicon (EGS)
• Figure illustrates entire EGS preparation process starting with MGS and including
the feedback or recycling of reaction by-product's to achieve high overall process
efficiency.
 Crystal Growth

This process is used to convert polycrystalline silicon to single crystalline silicon.

Crystallization takes place if molten silicon is allowed to a seed crystal which is a
single crystalline silicon with a high purity used as the starting material for crystal
growth.
Two established process used for crystal growth are:
• Czochralski crystal growth (CZ process)
• Float Zone crystal growth (FZ process)
 Czochralski crystal growth (CZ process)
• The vast majority of the commercially grown silicon is Czochralski silicon due
to the better resistance of the wafers to thermal stress, the speed of
production, and the low cost.
• The industrial standard crystals range in diameter from 75 to 200 mm, are
typically one meter long and have < 100> orientation.
• Czochralski silicon is often used in the electronics industry to make
semiconductor devices such as integrated circuits.
• The Czochralski method is named after J. Czochralski, who determined the
crystallisation velocity of metals by pulling mono and poly crystals out of a
melt held in a crucible.
CZ Method
CZ Method
The various components of the process are:

• a furnace, which includes a fused-silica crucible, a graphite susceptor, a

rotation mechanism (counter-clockwise as shown), a heating element,
and a power supply;

• a crystal-pulling mechanism, which includes a seed holder and a rotation

mechanism (Clockwise); and

• an ambient control, which includes a gas source (such as argon), a flow

control and an exhaust system.
CZ Method
• The process begins with a silicon seed crystal and high-purity polycrystalline
silicon, which serves as the raw material.
• In pieces of EGS (polycrystalline silicon) are placed in a silica (SiO2) quartz
crucible and heated to its melting point (about 1414°C) in a controlled
environment, usually in an inert atmosphere or vacuum.
• The seed crystal, which is a small piece of single crystal silicon, is dipped into
the molten silicon.
• The seed is then slowly pulled upwards while rotating, and the temperature
is carefully controlled. As the seed is withdrawn, the molten silicon solidifies
on the seed crystal, forming a larger single crystal.
• The rate of pulling and the temperature gradients are crucial for controlling
the diameter of the crystal.
• The crystal is typically grown in a cylindrical shape, and its diameter can be
adjusted by varying the pulling speed and the temperature of the melt.
CZ Method
•During the growth process, dopants (such as boron, phosphorus, arsenic, or
antimony) can be added to the melt to control the electrical properties of the
silicon. This results in the creation of p-type or n-type silicon.
•Once the crystal is grown, it is cooled and then shaped into wafers. The
cylindrical crystal is sliced into thin wafers, which are then polished to create
the smooth surface needed for integrated circuit fabrication.
• The CZ process is widely used because it produces high-quality single-crystal
silicon, which is essential for the fabrication of electronic devices.
• The size and purity of the silicon wafers produced through this process are
critical for modern semiconductor technology, as they influence the
performance and yield of integrated circuits.
Crystal Growth: CZ Method.

https://www.youtube.com/watch?v=skRmyhSOu28&list=PPSV
STRENGTHS OF CZ WAFERS
Cost-Effectiveness: CZ wafers are generally more cost-effective to produce than FZ wafers.
The Czochralski process allows for higher throughput, reducing manufacturing costs and
making CZ wafers more economically viable for mass production.
Versatility in Dopant Incorporation: CZ wafers offer greater versatility in introducing dopants
during the crystal growth process. This flexibility makes it easier to customize the electrical
properties of the wafer according to specific requirements.
Widespread Industry Adoption: CZ wafers have been the industry standard for several
decades, resulting in well-established manufacturing processes and infrastructure. This
widespread adoption contributes to the availability of CZ wafers in various specifications and
sizes.
WEAKNESSES OF CZ WAFERS
Lower Purity: Compared to FZ wafers, CZ wafers may have a higher impurity content. This
lower purity can be a limiting factor for certain applications, particularly those demanding
ultra-high purity silicon.
Crystal Defects: The Czochralski process can introduce crystal defects such as dislocations
and stacking faults. While advancements in manufacturing have reduced these defects, they
till exist to a greater extent compared to FZ wafers.
Crystal Growth: FZ Method
• Float-zone silicon is a high-purity alternative to crystals grown by the Czochralski process.
• Concentrations of light impurities, such as carbon and oxygen, are extremely low.
• Another light impurity, nitrogen, helps to control micro defects and also brings about an
improvement in the mechanical strength of the wafers. It is now being intentionally added
during the growth stages.
• The float Zone (FZ) method is based on the zone-melting principle and was invented by
Theuerer in 1962. Fig. 2.2 shows a schematic setup of the process.
• The production takes place under a vacuum or in an inert gaseous atmosphere.
• Similar to the Czochralski process, the FZ process begins with a high-purity polycrystalline
silicon rod and a single crystal seed.
Figure 2.2: Schematic setup for the Float Zone (FZ) process
• The polycrystalline silicon rod is held vertically, and a radio frequency (RF) induction coil is
used to generate heat. This coil moves along the length of the silicon rod, melting a small
region of the rod at a time. This melted region is referred to as the "float zone.“
• The single crystal seed is attached to the bottom of the rod, and as the coil moves upward,
the molten silicon solidifies onto the seed, forming a single crystal as it moves along.
• As the induction coil moves upward, the float zone also moves, allowing the molten silicon
to travel up the rod. The silicon solidifies as it cools, forming a single-crystal structure that
extends the length of the rod.
• This process eliminates many of the impurities present in the original polycrystalline
silicon, as impurities tend to remain in the molten zone and can be concentrated in one
end of the rod, which is later removed
•If required, dopants can be introduced during the process to control the electrical
properties of the silicon, similar to the CZ process. However, the FZ process is particularly
advantageous for producing very high-resistivity silicon, as it does not involve a quartz
crucible, which can introduce oxygen impurities.

•The result is a single-crystal silicon rod with very low impurity levels, particularly oxygen,
which is much lower than that in CZ silicon. The rod is then sliced into wafers for use in
semiconductor manufacturing.
Advantages of the FZ Process:
•High Purity: The FZ process results in extremely low levels of impurities, particularly oxygen,
because it avoids contact with a crucible. This is critical for high-performance devices like
power electronics and solar cells.
•High Resistivity: FZ silicon can achieve higher resistivity than CZ silicon, making it ideal for
certain types of semiconductor devices where this property is essential.
•Defect Control: The FZ process allows for better control over crystal defects, leading to
higher-quality silicon wafers.
Applications:
•The FZ process is commonly used for applications that require ultra-pure silicon, such as in
high-voltage power devices, advanced solar cells, and radiation detectors.
•It's also used in some research and development settings where material purity is
paramount.
•While the FZ process is more expensive and slower than the CZ process, its ability to
produce silicon with superior electrical properties makes it indispensable for certain
specialized applications in the semiconductor industry.
Silicon Shaping
• Ingot trimming
• Surface grinding
• Ingot Slicing
• Wafer Lapping
• Etching
• Polishing
 Silicon Shaping
• After the single crystal is obtained, this needs to be further processed to
produce the wafers. For this, the wafers need to be shaped and cut.
• Silicon is a hard, brittle material. Industrial-grade diamond is the most suitable
material for shaping and cutting silicon, although Silicon carbide (SiC) and
aluminum oxide (Al₂O₃) and have also been used.
• Conversion of silicon ingots into polished wafers requires
• six machining operations to convert silicon ingots into polished wafers,
• two chemical operations and
• one or two polishing operations
• A finished wafer is subject to a number of dimensional tolerance, dictated by the
needs of the device fabrication technology.
 Shaping operations
• The first operation is ingot trimming which removes the seed and tang ends from the ingot.
Cutting is conveniently done as a manual operation using circular saw.
• The next operation is a surface grinding that defines the diameter of the material.
• Silicon ingots are grown slightly oversized because the automatic diameter control in crystal
growing cannot maintain the needed diameter tolerance and crystals cannot be grown
perfectly round.
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After the orientation and resistivity checks, one or more flats are required along
the length of the ingot.
There are two types of flats.
• Primary flat and secondary flats.
• These are key reference marks that help identify the wafer's crystallographic
orientation, type of doping (p-type or n-type), and resistivity range.
• These flats are ground into the edge of the silicon wafer during the ingot
shaping process.
• The primary flat is the largest and most significant flat edge on the wafer. It
serves as the primary reference mark for wafer orientation during various
stages of processing and manufacturing.
• The secondary flat is a smaller flat edge, used in conjunction with the primary
flat to provide additional information about the wafer's properties, such as
doping type and resistivity range.
Ingot Slicing: after grinding the ingot is ready to be sliced into wafers.
Slicing determines four important wafer parameter's.
• Surface orientation
• Thickness
• Tapper
• Bow(curvature)

Surface orientation is determined by cutting several wafers, measuring the orientation by X-

ray method and then setting the saw until the orientation is achieved.
The wafer thickness is essentially fixed by slicing, although the final value depends on
subsequent shaping operations. Thicker wafers are better able to withstand the stresses of
subsequent thermal processes (epitaxy, oxidation, and diffusion).
Taper: This refers to the slight variation in thickness from one side of the wafer to the other.
Slicing must minimize taper to maintain uniformity across the wafer.
Bow (Curvature): Slicing affects the wafer's curvature or bow, which needs to be minimized to
ensure flatness and uniformity in subsequent processing steps.
Wafer Lapping : wafers must be defect free and damage free. Whenever cutting a
wafer, having lots of damages on the surface of the wafer. So rough polishing it with
conventional, abrasive, slurry-lapping to remove majority of surface damage to create flat
surface.

Surface of the wafers must be Lapping is primarily used to remove surface damage caused
by the slicing process and to achieve a uniform thickness across the wafer. It also helps in
reducing surface roughness.
Wafer edge rounding or Edge Profiling
The purpose of Edge rounding is
• Produce rounded wafer edge that is tougher and more resistant to chipping during
handling.
• Minimize edge surface roughness.
• Minimize depth of damage on edges.
Etching
Due to shaping operations, the surface and edges of the wafer get damaged and
contaminated. This can be removed by chemical etching.
Some of the commonly used solutions are mixture of HF (Hydrofluoric Acid), HNO₃ (nitric
acid), and CH₃COOH (Acetic Acid).

Chemical etching of wafer is basically of two types.

• Acid etching
• Alkali etching
Acid Etching

• Acid etching is usually done in an acid bath with a mixture of hydrofluoric acid, nitric acid,
and acetic acid in the ratio of 4:1:3.

• In acid etching the dimensional uniformity is not maintained for larger wafer, so alkali
etching is preferred for larger wafers.

Alkali Etching
• In alkali etching a mixture of sodium hydroxide (NaOH) and water or KOH(potassium
hydroxide) and water is used.
• A typical formulation uses KOH(potassium hydroxide) and H20 is a 45% wt. solution (i.e.
45% KOH and 55% H20) at 900°C to achieve an etch rate of 25 pm/min for {100} surfaces.
• Alkali etching is limited by reaction rate and is orientation dependent and in this wafer do
not have to be rotate in the solution
 Polishing
• Polishing is the final step. Its purpose is to provide a smooth, specular surface on which
device features can be photoengraved.
 Polishing
• The process involves a polishing pad is made of artificial fabric, such as a polyester felt,
polyurethane laminate.
• Wafers are mounted on a wafer holder, pressed against the pad under high pressure , and
rotated relative to the pad.
• A mixture of polishing slurry and water dripped on to the pad, does the polishing (which is
both chemical and mechanical process). The porosity of the pad is a factor in carrying slurry to
the water for polishing. The slurry is a colloidal suspension of fine SiO2 particles in an aqueous
solution of sodium hydroxide. Under the heat generated by friction, the sodium hydroxide
oxidizes the silicon with the OH radical . This is the chemical step.
• In the mechanical step the silica particles in the slurry abrade the oxidized silicon away.
• Polishing rate and surface finish are complex functions of pressure, pad properties, rotation
speed, slurry composition, and pH of the polishing solution.
• After polishing, wafers are chemically cleaned with acid, base, and/or solvent mixtures to
remove slurry residue (and wax), and readied for inspection.
• Polished wafers are subjected to a number of measurements that are concerned with
cosmetic, crystal perfection, mechanical, and electrical attributes.
 Wafer-Cleaning Technology: Introduction
• In the IC processing of silicon wafers it is usually necessary to maintain the purity and
perfection of the material.
• Wafer-cleaning technology is a critical step in semiconductor manufacturing, ensuring that
wafers are free of contaminants, which is essential for the production of high-quality
integrated circuits (ICs).
• The cleaning process removes particles, organic residues, metallic contaminants, and native
oxides from the wafer surface.

Types of Contaminants

• Particles: Dust, residues from previous processing steps, or material dislodged from
equipment.
• Organic Contaminants: Residues from photoresist, oils, or solvents.
• Metallic Contaminants: Metals that could come from the environment or from previous
processing.
• Native Oxides: Thin layers of oxide that form naturally on silicon surfaces when exposed to air.
Common Cleaning Techniques
• Wet Cleaning or chemical cleaning: Prior to use, silicon wafers are usually cleaned chemically
to remove organic films, ionic and heavy metals.
• RCA Wet Cleaning process: process removes organic, ionic and heavy metal contaminants.
• consists of two sequential cleaning steps – SC1 and SC2
• Preliminary cleanup: Piranha solution: A mixture of sulfuric acid and hydrogen peroxide
(H₂SO₄+H₂O₂): It's highly effective for removing organic residues.

• SC1 (Standard Clean 1): A mixture of ammonium hydroxide, hydrogen peroxide, and water
(NH₄OH+H₂O₂) : It removes organic materials and particles.
HF Dip: Hydrofluoric acid is used to remove native oxides from the wafer surface.
• SC2 (Standard Clean 2): A mixture of hydrochloric acid, hydrogen peroxide, and water HCl-
H₂O₂): It removes ionic and metallic contaminants.
Dry Cleaning
• Uses gases or plasma to remove contaminants without liquid chemicals.
• Plasma Cleaning: Involves exposing the wafer to a plasma that reacts with the contaminants
to remove them.
• UV/Ozone Cleaning: Uses ultraviolet light to generate ozone, which oxidizes and removes
organic contaminants.