Injibara University

College of Engineering and Technology

Subject:
Course Code:

Molla K.(MSc)

1/29/2025 1
 Chapter- 6

Advanced Microprocessor 8086

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 8086 Microprocessor
Overview
 First 16- bit processor released by
 Instruction is a command to the MP to
INTEL in the year 1978
perform the given a given operation the
 Originally HMOS, now manufactured
specific data.
using HMOS III technique
 Addressable memory space is organized in
 Approximately 29, 000 transistors, 40
to two banks of 512 kb each; Even (or
pin DIP, 5V supply lower) bank and Odd (or higher) bank.
 Does not have internal clock; external  Uses a separate 16 bit address for I/O
asymmetric clock source with 33% duty mapped devices  can generate 216 = 64 k

cycle addresses.
It has two operation modes:
 20-bit address to access memory  can
Max mode: it is a multiprocessor system.
address up to 220 = 1 megabytes of
Min mode: it is a single processor system.
memory space.

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 Intel 8086/8088 Internal Architecture

 Architecture provides what ever the building blocks of circuits for the
computer.
 It is divide into two independent functional units. These are:
Bus Interface Unit(BIU)
Execution Unit (EU) or Internal Architecture

 All general purpose registers of the 8086 MP can be used for arithmetic
and logic operation.
 These all general registers can be used as either 8 bit or 16-bit registers.
 Intel 8086 Internal Architecture

Bus Interface Unit (BIU)

BIU fetches instructions from memory.
Execution Unit (EU)
It reads data from I/O ports,
EU executes instructions that have
 Writes data to memory.
already been fetched by the BIU.
 Writes data to the I/ O ports. It has 3 functions unit:
BIU and EU functions separately.
Instruction Pointer
 Segment Register and
 Instruction Queue which perform theses tasks.

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Con’d
Bus Interface Unit (BIU)

Dedicated Adder to generate 20

bit address

Four 16-bit segment registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

 Additional registers, called segment

registers, generate memory addresses
when combined with other registers in
the microprocessor.
 The segment registers stores the
starting addresses of a segment.
 To get the exact location of data or
instruction within a segment, an offset
value (or displacement) is required.

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 Con’d
Bus Interface Unit (BIU)

Segment Registers

8086’s 1-megabyte memory

is divided into segments of
up to 64K bytes each.

Programs obtain access to code

The 8086 can directly address four
and data in the segments by
segments (256 K bytes within the 1 M
changing the segment register
byte of memory) at a particular time.
content to point to the desired
segments.

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 Con’d Bus Interface Unit (BIU)

Code Segment Register

Segment 16-bit
Registers
The code segment is a section of memory that holds the code
(programs and procedures) used by the microprocessor.
CS contains the base or start of the current code segment; IP contains
the distance or offset from this address to the next instruction byte
to be fetched.
BIU computes the 20-bit physical address by logically shifting the
contents of CS 4-bits to the left and then adding the 16-bit contents
of IP.
That is, all instructions of a program are relative to the contents of
the CS register multiplied by 16 and then offset is added provided by
the IP.

SR: The memory space 1MB of 8086 is segmented into 4-

blocks each block is specified by register. with max size 64kb.

Assume: CS= 1000H , IP= 2345H, PA= S*10+IP= 12345H.

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 Con’d Bus Interface Unit (BIU)

Segment Data Segment Register

Registers 16-bit
The data segment is a section of memory that contains most
data used by a program.
Points to the current data segment; operands for most instructions
are fetched from this segment.
The 16-bit contents of the Source Index (SI) or Destination Index (DI)
or a 16-bit displacement are used as offset for computing the 20-bit
physical address.
The number of address lines in 8086 is 20, 8086 BIU will send
20-bit address, so as to access one of the 1MB memory locations.
A segment is a logical unit of memory that may be up to 64
kilobytes long.
Each segment is made up of connecting memory locations. It is an
independent, separately addressable unit.
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 Con’d Bus Interface Unit (BIU)

Segment Stack Segment Register

Registers
16-bit
In 8086, the main stack register is called stack pointer(SP). The stack
segment register (SS) is usually used to store information about the
memory segment that stores the call stack of currently executed
program.
The stack segment defines the area of memory used for the stack.
Points to the current stack.
The 20-bit physical stack address is calculated from the Stack Segment
(SS) and the Stack Pointer (SP) for stack instructions such as PUSH and
POP.
In based addressing mode, the 20-bit physical stack address is
calculated from the Stack segment (SS) and the Base Pointer (BP).
Assume: CS= 1000H , IP= 2345H, PA= S*10+IP= 12345H.

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 Con’d Bus Interface Unit (BIU)

Segment
Registers Extra Segment Register
16-bit
Points to the extra segment in which data (in
excess of 64K pointed to by the DS) is
stored.
String instructions use the ES and DI to
determine the 20-bit physical address for
the destination.

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 Con’d Bus Interface Unit (BIU)

Segment
Instruction Pointer
Registers
16-bit
Always points to the next instruction to be
executed within the currently executing code
segment.
So, this register contains the 16-bit offset address
pointing to the next instruction code within the
64Kb of the code segment area.
Its content is automatically incremented as the
execution of the next instruction takes place.
It is the 16-bit register that keeps the address of
memory location of coming instruction to be
executed.
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Con’d Bus Interface Unit (BIU)

Instruction queue

A group of First-In-First-Out (FIFO)

in which up to 6 bytes of
instruction code are pre fetched
from the memory ahead of time.
This is done in order to speed up
the execution by overlapping
instruction fetch with execution.
This mechanism is known as
pipelining.
BIU performs its operation
parallel with execution unit,
BIU fetches instruction Byte
while execution unit executing
operations.

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Execution Unit (EU)

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 Con’d Execution Unit (EU)
 EU decodes and executes instructions.
 A decoder in the EU control system
translates instructions.
 To tell where to fetch instruction data
from

16-bit ALU for performing

arithmetic and logic operation

Four general purpose

registers(AX, BX, CX, DX);
Pointer registers (Stack
Pointer, Base Pointer); Some of the 16 bit registers can be used as two 8 bit

and Index registers (Source registers as :

Index, Destination Index) AX can be used as AH and AL

BX can be used as BH and BL
each of 16-bits
CX can be used as CH and CL
DX can be used as DH and DL
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 Con’d Execution Unit (EU)

EU Registers Accumulator Register (AX)

Consists of two 8-bit registers AL and AH, which can
be combined together and used as a 16-bit register
AX.
AL in this case contains the low order byte of the
word, and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting/
outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX
or AL.
This accumulator used in arithmetic, logic and data
transfer operations.

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 Con’d
Execution Unit (EU)
EU Registers
Base Register (BX)
Consists of two 8-bit registers BL and BH,
which can be combined together and used as a
16-bit register BX.
BL in this case contains the low-order byte of
the word, and BH contains the high-order byte.
This is the only general purpose register whose
contents can be used for addressing the 8086
memory.
All memory references utilizing this register
content for addressing use DS as the default
segment register.
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 Con’d Execution Unit (EU)
EU Registers Counter Register (CX)
Consists of two 8-bit registers CL and CH, which can
be combined together and used as a 16-bit register CX.
When combined, CL register contains the low order
byte of the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use
the contents of CX as a counter.

Example:
The instruction LOOP START automatically decrements
CX by 1 without affecting flags and will check if [CX] =
0.
If it is zero, 8086 executes the next instruction;
otherwise the 8086 branches to the label START. 18
 Con’d
Execution Unit (EU)
EU Registers Data Register (DX)
Consists of two 8-bit registers DL and DH, which can
be combined together and used as a 16-bit register
DX.
When combined, DL register contains the low order
byte of the word, and DH contains the high-order
byte.
Used to hold the high 16-bit result (data) in 16 X 16
multiplication or the high 16-bit dividend (data) before
a 32 ÷ 16 division and the 16-bit reminder after
division.

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 Con’d Execution Unit (EU)

EU Registers  Stack Pointer (SP)

SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during
execution of instructions that involve the stack segment
in the external memory. SP is offset for stack segment.
SP contents are automatically updated (incremented/
decremented) due to execution of a POP or PUSH
instruction.
SP’s offset :Last word stored in stack. To access the
storage of the stack.
Top of Stack(TOS) SS: SP
Base Pointer (BP)
BP offset for stack segment in base addressing mode.
BP contains an offset address in the current SS, which is
used by instructions utilizing the based addressing mode.
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 Con’d
Execution Unit (EU)
EU Registers Source Index (SI) and Destination Index (DI)

Used in indexed addressing.

Instructions that process data strings use
the SI and DI registers together with DS
and ES respectively in order to distinguish
between the source and destination
addresses.

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 Con’d Execution Unit (EU)
Auxiliary Carry Flag Carry Flag

Flag Register This is set, if there is a carry from the

lowest nibble, i.e, bit three during
This flag is set, when there is
a carry out of MSB in case of
addition, or borrow for the lowest addition or a borrow in case
nibble, i.e, bit three, during of subtraction.
subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Trap Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit Causes the 8086 to recognize
is ‘0’, the string is processed beginning from the lowest external maskable interrupts;
address to the highest address, i.e., auto incrementing mode. clearing IF disables these
Otherwise, the string is processed from the highest address interrupts.
towards the lowest address, i.e., auto incrementing mode. 22
 8086 Microprocessor Architecture
8086 registers categorized into 4 groups
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose 16 bit AX, BX, CX, DX
register
8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag 16 bit Flag register

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 8086 Microprocessor Registers and Special Functions

Architecture
Register Name of the Special Function
Register
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access memory
data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data) for string
operations

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 Pipelining
 Pipelining is the process of accumulating instruction from the processor through a
pipeline.
 It allows storing and executing instructions in an orderly process.
 It is also known as pipeline processing.
 Pipelining is a process of arrangement of hardware elements of the CPU such that
its overall performance is increased.
 It is one way of improving the overall processing performance of a processor
 The classic five stage pipeline
• Instruction fetch.
• Instruction decode.
• Execute.
• Memory access.
• Writeback. 25
 Cache Memory
 Cache is the temporary memory officially termed CPU cache memory.
 Cache memory is intended to give memory speed approaching that of the fastest
memories available, and at the same time provide a large memory size at the price of less
expensive types of semiconductor memories
 Cache is local memory that exists in the data path between the processor and main
memory.
 A cache will hold a collection of data that has been recently referenced and has a high
probability of being requested by the processor

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 cont

• The cache contains a copy of portions of main memory.

• When the processor attempts to read a word of memory, a check is made to
determine if the word is in the cache

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 Memory Management (MMU)
o Memory is a system or process that stores what we acquire for future use.
o The memory has three basic functions: encoding, storing, and retrieving
information.
o Memory management is the process of controlling and coordinating a computer's main
memory.
o It ensures that blocks of memory space are properly managed and allocated so the
operating system, applications and other running processes have the memory they need
to carry out their operations.
o A MMU is a computer hardware component that handles all memory and
caching operations associated with the processor.
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 Virtual Memory System
o Virtual Memory is a computer concept where the main memory is
broken up into a series of individual pages.

o The virtual memory is a memory management technique that allows the users to
execute programs larger than the actual physical memory.
o Virtual memory is the partition of logical memory from physical memory.
o The partition supports large virtual memory for programmers when only
limited physical memory is available.
o Virtual Memory is a device used by the operating system to run
processes that exceeds the available RAM size.
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 Summary
 Register is very small amount of fast memory , that is built in the CPU in
order to speed up the operation.
 Register is very fast and efficient than the other memories like RAM, ROM
and external memory etc.
 That is why the register s occupied the top of the position in the memory
hierarchy model. It is nothing but it is a collection of flip-flops

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