Transistor 2
Transistor 2
2
DC Biasing Circuits
base-bias circuits
emitter-feedback bias circuits
emitter-bias circuits
collector-feedback bias circuits
voltage-divider bias circuits
3
VRE = IE.RE
VRC = IC.RC
Vcc = Ic.Rc + VCE + IE.RE
Vcc= Ic.Rc + Vc
Vc = Vcc- Ic.Rc
Vc = VCE + IE.RE
VE = IE.RE
VB = VBE + IE.RE
VB = 0.7 +IE.RE
4
Fig 7.6-8 Optimum Q-point with
amplifier operation.
IC
IC(sat)
IB = 50 A IB
I C βI B
IB = 40 A
IC(sat)/2 Q-Point IB = 30 A
IB = 20 A
IB = 10 A
IB = 0 A
VCE
VCC/2 VCC
VCE VCC I C RC
5
Base bias
VCC - VRB - VBE = 0
VCC - IBRB - VBE = 0
VBE =0.7V
VCC VBE
IB
RB
I C βI B
VCE VCC I C RC
6
7
8
Emitter-feedback bias
-VCC + IBRB + VBE + IERE = 0
IB
IC
9
Emitter-feedback bias
11
12
Circuit Stability of
Emitter-Feedback Bias
T β IC IE VRE
VRB IB IC IE VRE
VRB IB IC
13
Emitter bias.
IE = I C + I B ≅ IC 14
VEE + VRB + V + V = 0
BE RE
15
16
17
18
Collector-Feedback Bias
I E = I C + I B ≅ IC
19
20
21
22
Circuit Stability of
Collector-Feedback Bias
T β IC VRC Vc VRB
IB IC VRC Vc
VRB IB IC VRC Vc VRB IB IC
23
VOLTAGE-DIVIDER BIAS
1)
24
25
26
27
28
2)
29
30
31
32
33