NETAJI SUBHAS UNIVERSITY OF TECHNOLOGY

NEW DELHI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
(EAST)

DCS Practical File

Made By : ANIMESH GUPTA

Roll No: 2021UEA6545
Batch: ECAM-1

Submitted To: Dr. CS Vinitha

Digital Circuits and Systems (EAEPC08)
 EXPERIMENT-1
AIM: To simulate and synthesize basic logic gates

APPARATUS: Xilinx Project ISE software

THEORY:
The basic logic gates are the building blocks of more complex logic circuits. These logic gates
perform the basic Boolean functions, such as AND, OR, NAND, NOR, NOT, X-OR, X-NOR. Fig.
below shows the circuit symbol, Boolean function, and truth table. It is seen from the image
below that each gate has one or two binary inputs, A and B, and one binary output, C. The small
circle on the output of the circuit symbols designates the logic complement. A gate can be
extended to have multiple inputs if the binary operation it represents is commutative and
associative, as is the case in AND, OR, NAND and NOR gates.

i.) AND GATE:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A
dot (.) is used to show the AND operation i.e. A.B or can be written as AB

ii.) OR GATE:
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.

iii.) NOT GATE:

The NOT gate is an electronic circuit that produces an inverted version of the input at its output.
It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A.
This is also shown as A' or A with a bar over the top, as shown at the outputs.

iv.) NOR GATE:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of
all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small
circle on the output

v.) NOR GATE:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output.
PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.

CODE AND SIMULATION:

OR GATE
AND
NOT

NAND
NOR
 EXPERIMENT-2

AIM: To simulate and synthesize a half adder and half subtractor

APPARATUS: Xilinx Project ISE software

THEORY:

A half adder is a combinational logic circuit that performs the addition of two input data bits, A
and B. The operation results in two output bits: the sum bit, S, and the carry bit, C. The truth
table of a half-adder is:

From the truth table, the logical expressions are deduced as follows:
S=A⊕B
C=A.B
A half subtractor is a combinational circuit that performs the subtraction of two input data bits,
A and B (A-B). The operation results in two output bits: the sum bit, D, and the borrow bit, B.
The truth table of a half-subtractor is:

From the truth table, the logical expressions are deduced as follows:
S=A⊕B
C=A’.B
PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.

CODE AND SIMULATION:

Half Adder
Half Subtractor
 EXPERIMENT-3
AIM: To simulate and synthesize a full adder

APPARATUS: Xilinx Project ISE software

THEORY:

A full-adder is a combinational logic circuit that adds two input data bits, A and B, and a carry-in
bit, Cin. It is an improvement over the half-adder which does not take the carry-in bit from its
previous stage into account. The truth table of a full-adder is:

S=A⊕B⊕Cin

Cout=AB+(A⊕B)Cin
PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.

CODE AND SIMULATION:

 EXPERIMENT-4
AIM: To simulate and synthesize a parallel adder

APPARATUS: Xilinx Project ISE software

THEORY:

Parallel adders are made when full adders are placed in parallel and can add multiple-digit
numbers. The carry-out from a full adder serves as the carry-in for the higher-order full adder.
The above circuit represents a 4-bit ripple carry adder which performs the addition of two 4-bit
numbers, A=A 3A2A1A0 and B=B3B2B1B0.

The Full adder can add single-digit binary numbers and carries. The largest sum that can be
obtained using a full adder is (11)2 ie. 3.

PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.
CODE AND SIMULATION:
 EXPERIMENT-5
AIM: To simulate and synthesize a 2:4 Decoder

APPARATUS: Xilinx Project ISE software

THEORY:

The combinational circuit that changes the binary information into 2N output lines is known as
Decoders. The binary information is passed in the form of N input lines. The output lines define
the 2N-bit code for the binary information.

The truth table is as follows:

A B Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

The 2 to 4 decoder has two inputs A 0 and A 1, and four outputs Y3, Y2, Y1 & Y1. One of these four
outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’. The boolean functions of
the outputs will be:

Y3=E.A1.A0
Y2=E.A1.A0'

Y1=E.A1'.A0

Y0=E.A1'.A0'

PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.
CODE AND SIMULATION:
 EXPERIMENT-6
AIM: To simulate and synthesize a 4:1 Multiplexer

APPARATUS: Xilinx Project ISE software

THEORY:

A Multiplexer, also called mux, is a combinational circuit that has a maximum of 2n data
inputs, ‘n’ selection lines and a single output line. One of these data inputs will be
connected to the output based on the values of selection lines.

A 4x1 Multiplexer has four data inputs I 3, I2, I1 & I0, two selection lines S1 & S0 and one
output Y

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
 1 1 I3

The boolean expression derived from the table is:

Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.

CODE AND SIMULATION:

 EXPERIMENT-7
AIM: To simulate and synthesize an SR Latch

APPARATUS: Xilinx Project ISE software

THEORY:
A Latch, also referred to as bistable-multivibrator, is a storage device that holds data using the
feedback lane.
The SR latch is a special type of asynchronous device which works separately for control
signals. It depends on the S-states and R-inputs. The SR latch is designed by connecting two
NOR gates with a cross loop connection. The SR latch can also be designed using the NAND
gate.

PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.

CODE AND SIMULATION:

 EXPERIMENT-8
AIM: To simulate and synthesize a JK Flip Flop

APPARATUS: Xilinx Vivado software

THEORY:

The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry. The
invalid or illegal output condition occurs when both of the inputs are set to 1 and are
prevented by the addition of a clock input circuit. So, the JK flip-flop has four possible
input combinations, i.e., 1, 0, "no change" and "toggle". The symbol of the JK flip flop is
the same as SR Bistable Latch except for the addition of a clock input.

Present Inputs Present State Next State

J K Qt Qt+1
0 0 0 0
0 0 1 1
 0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

The simplified expression for the next state Qt+1 is:

Q(t+1)=JQ(t)′+K′Q(t)

PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.
CODE AND SIMULATION:
 EXPERIMENT-9
AIM: To simulate and synthesize registers (SISO, SIPO AND PISO)
APPARATUS: Xilinx Project ISE software

THEORY:
A group of flip flops that are used to store multiple bits of data and the data is moved
from one flip flop to another is known as Shift Register. The bits stored in registers shift
when the clock pulse is applied within and inside or outside the registers. To form an
n-bit shift register, we have to connect n number of flip flops. So, the number of bits of
the binary number is directly proportional to the number of flip flops. The flip flops are
connected in such a way that the first flip flop's output becomes the input of the other
flip flop.

SISO

In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. In SISO, a single
bit is shifted at a time in either right or left direction under clock control.

Initially, all the flip-flops are set in "reset" condition i.e. Y3 = Y2 = Y1 = Y0 = 0. If we pass
the binary number 1111, the LSB bit of the number is applied first to the Din bit. The D3
input of the third flip flop, i.e., FF-3, is directly connected to the serial data input D3. The
output Y3 is passed to the data input d2 of the next flip flop. This process remains the
same for the remaining flip flops. The block diagram of the "Serial IN Serial OUT" is
given below.
PISO
In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and the
outcome comes serially. A four-bit "Parallel IN Serial OUT" register is designed below.
The input of the flip flop is the output of the previous Flip Flop. The input and outputs
are connected through the combinational circuit. Through this combinational circuit, the
binary input B0, B1, B2, B3 are passed. The shift mode and the load mode are the two
modes in which the "PISO" circuit works.

SIPO
In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop,
and outputs are fetched in a parallel way. The data is passed bit by bit in the register,
and the output remains disabled until the data is not passed to the data input. When the
data is passed to the register, the outputs are enabled, and the flip flops contain their
return value.

PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.

CODE AND SIMULATION:

SISO
SIPO

PISO
 EXPERIMENT-10
AIM: To simulate and synthesize MOD16 counter

APPARATUS: Xilinx Project ISE software

THEORY:
A counter is a special type of sequential circuit used to count the pulse or a collection of
flip flops where the clock signal is applied. The counter is one of the widest applications
of the flip flop. Based on the clock pulse, the output of the counter contains a predefined
state. The number of the pulse can be counted using the output of the counter.

i.) Asynchronous Counters:

In the Asynchronous counter, the present counter's output passes to the input of the
next counter. So, the counters are connected like a chain. The drawback of this system
is that it creates the counting delay, and the propagation delay also occurs during the
counting stage.

ii.) Synchronous Counters:

In the synchronous counter, the same clock pulse is passed to the clock input of all the
flip flops. The clock signals produced by all the flip flops are the same as each other.
Below is the diagram of a 2-bit synchronous counter in which the inputs of the first flip
flop, i.e., FF-A, are set to 1. So, the first flip flop will work as a toggle flip-flop. The output
of the first flip flop is passed to both the inputs of the next JK flip flop.

MOD-16 (Up-Down)
PROCEDURE:
1. After opening the software, create a new project.
2. Select RTL file, name it and select the directory to save it in
3. Set language to VHDL simulator to mixed.
4. Add a new design source and enter the port mappings in it.
5. Write the VHDL code in the architecture.
6. Make a new simulation source and add the test bench to it. Run the simulation.
7. Select the type (hexadecimal, binary, etc.), force value, starting
after time offset and cancel after time offset.
8. Analyze the waveform and do its RTL analysis.

CODE AND SIMULATION: