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Microprocessor and Microcontroller

Prepared by

S.Mamtha
Assistant Professor
EEE/CIT

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Pin diagram of 8085 microprocessor

8085 Pindiagram
Figureshows8085pinconfigurationandfunctional8085MicroprocessorPinDiagramrespectively.
Thesignalsof8085can be classifiedintoseven groupsaccordingtotheirfunctions.

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a)Pinconfiguration b)Functionalpindiagram

 DataandAddressbus
 A8–A15Addressbus-it carriesthemost significant8-bitsofmemoryI/Oaddress.
 AD7-AD0,(Multiplexed Address/data bus).It carries the least significant 8-bit address and data
bus.Thesepins servethe dual purposeof transmitting lowerorderaddressand databyte. During1stclock
cycle, these pins act as lower half of address. In remaining clock cycles, these pins act as databus

 Controlandstatussignals
Thesesignalsareused toidentifythenature ofoperation.Thereare3controlsignaland3statussignals.
 ThreecontrolsignalsareRD,WR&ALE.

 RD−ThissignalindicatesthattheselectedIOormemorydeviceistobereadandisreadyforacceptingdataavai
lableon thedatabus.

 WR−ThissignalindicatesthatthedataonthedatabusistobewrittenintoaselectedmemoryorIO location.

 ALE−Itisapositivegoingpulsegeneratedwhenanewoperationisstartedbythemicroprocessor.Whenthepu
lsegoeshigh,itindicatesaddress.Whenthe pulsegoesdown itindicatesdata.

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 Threestatus signalsareIO/M,S0&S1.

 S1&S0

S0and S1are calledStatus Pins.Theytell thecurrentoperation whichisin progressin8085.

 IO/M

ThissignalisusedtodifferentiatebetweenI/Oand Memoryoperations, i.e.

 whenitishighindicates I/Ooperationand
 whenitislowthenitindicatesmemoryoperation.

Thesesignalsare used toidentifythetypeofcurrentoperation.

ControlandStatusSignals

Machine IO/M S1 S0 Control

Cycle signals
Opcode 0 1 1 RD=0
Fetch
Memory 0 1 0 RD=0
Read
Memory 0 0 1 WR=0
Write
I/ORead 1 1 0 RD=0

I/OWrite 1 0 1 WR=0

InterruptAck 1 1 1 INTA=0
nowledge

Halt Z 0 0 RD,WR=z
andINTA=1
Hold Z X X RD,WR=z
andINTA=1
Reset Z X X RD,WR=z
andINTA=1

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 Powersupply
Thereare2 powersupply signalsVCC&VSS.

 VCCindicates+5v power supply and

 VSSindicates groundsignal.

 Clocksignals
Thereare3clock signals,i.e. X1,X2,CLKOUT.

 X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set frequency
oftheinternal clockgenerator.Thisfrequencyisinternally divided by2.

 CLKOUT−Thissignalisusedasthesystemclockfordevicesconnectedwiththemicroprocessor.

 Interrupts&externallyinitiatedsignals
Interrupts are the signals generated by external devices to request the microprocessor to perform a
task.There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We will
discussinterruptsin detail in interrupts section.

 INTA−It isaninterrupt acknowledgmentsignal.

 RESET IN − This signal is used to reset the microprocessor by setting the program counter
tozero.

 RESETOUT−Thissignalisusedtoresetalltheconnecteddeviceswhenthemicroprocessorisreset.

 READY − This signal indicates that the device is ready to send or receive data. If READY
islow,then theCPUhas towait forREADYto gohigh.

 HOLD − This signal indicates that another master is requesting the use of the address and
databuses.

 HLDA(HOLDAcknowledge)−ItindicatesthattheCPUhasreceivedtheHOLDrequestandit will
relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD signal isremoved.

 SerialI/Osignals
Thereare2serial signals,i.e. SIDand SODand thesesignalsareusedforserialcommunication.
 SOD(Serialoutputdataline)− TheoutputSODisset/resetasspecified bytheSIM instruction. 
 SID (Serial input data line) − The data on this line is loaded into accumulator whenever a
RIMinstructionis executed.

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 FiveHardwareInterruptsin8085
 TRAPisanon-maskableinterrupt
 RST7.5isanedge triggered interrupt.
 RST6.5isamaskableandlevel triggeredinterrupt
 RST5.5isamaskableandlevel triggeredinterrupt
 INTRisanon-vectoredinterrupt
************************************************************************************************
Explainthe memoryorganizationof8085
**************************************************************************************
3. MemoryOrganization(R/WMemory):
Memory is an essential component of a microcomputer system. It stores binary instructions and data
forthe microprocessor. There aretwo types of memory: Read/Write Memory(R/WM) and Read-only
Memory(ROM).The8085has 16 addresslines. That meansit canaddressupto216=64Kbytes.

Fig:Memorychip with8registers

Tocommunicate withmemory,theMPU shouldbeableto:

1. identifiesthememorylocation (withaddress)
2. Generatestimingandcontrolsignal
3. Datatransfertakes place.
TheMPUuses theCSlinetoselectthechip,andtheR/Wlineto controldataflow.

Fig:Interfacing8085withR/W memory

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Fig:Interfacing8085withROM

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HowtheMPU writesintoandReadfrommemory?

 Towriteabyteinto amemorylocationfrom8085 MPU

1. Places the 16-bit address on the address bus of the memory location where a byte is to be
storedThisaddressisdecodedtoselectthememory chip,andthememory register is identified.
2. Placesthebyte onthedata bus.
3. Sendsthecontrol signal( toenablethe inputbuffersof thememoryandthenstores thebyte.

 Toreadfrommemory, thestepsaresimilar.
1. The MPU places the 16-bit address on the address bus and sends the control signal to enable
theoutputbufferofthememory chip.
2. Theinterfacinglogicof thememorychipdecodestheaddressandselectstheappropriate memory
register.
3. Thememorychip placesthedatabyte onthe databus,andtheMPUreadsthedata byte.

****************************************************************************
ExplainI/OInterfacingin8085.
*****************************************************************************
4. 8085InterfacingwithI/Odevices
There are various communication devices like the keyboard, mouse, printer, etc. So, we need to
interfacethe keyboard and other devices with the microprocessor by using latches and buffers. This type of
interfacing isknownas I/Ointerfacing.
MicroprocessorneedstoIdentifyI/Odeviceswithbinarynumber.I/Odevicescanbeinterfacedinthree
steps.
1. Identifythememory location(withaddress).
2. Generatetimingandcontrolsignal.
3. Datatransfertakes place.

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Thetechniques usedforI/Ointerfacingare
1. Memorymapped I/O
2. I/Omapped I/OorPeripheralmapped I/O

1. Memory-MappedI/O
 In memorymappedI/O,eachdevice has anaddress justlikeamemorylocation.
 Thememorymap(64K)issharedbetweenI/Odeviceandsystemmemory. 
 InstructionsSTA/.LDAand MOVareusedfordatatransfer.
 Deviceisidentifiedby16-bitaddress (Spacerangesfrom0000H–FFFFH).

2. PeripheralMappedI/O
 256inputdevice and256.outputdevice canbeconnected.
 IthasseparatenumberingschemeforI/Odevices. 
 InstructionsIN&OUTareusedfordatatransfer.
 Deviceisidentifiedby8-bitaddress (Spaceranges from00H–FFH).

DeviceSelectionandDataTransfer

Datatransfersteps

 Fordatatransferfrominputdevicetoprocessor thefollowingoperations areperformed

1. TheMPUplacesan8-bitdevice addressonaddressbusthendecoded.
2. TheMPUsendsacontrolsignal (IORor IOW)toenabletheI/O device.
3. Dataare placedonthedatabusfortransfer.

 Datatransferfromprocessortooutputdevicethefollowingoperationsareperformed.
Tosenddata toO/Pdevice:-
1. TheMPUplacesthedevice address(outputportno.)ontheaddress bus.

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2. TheMPUplacesdataondatabus.
3. TheMPUenablestheoutputdeviceusingthe controlsignal(IOW).
4. TheO/Pdevicelatches anddisplaysdata(ifO/P=LED).Theotherperipheralsthatarenotenabledremainin
ahigh impedancestate called (tri-state).

ComparisonbetweenMemory mappedI/OandPeripheral mappedI/O

Memorymapped I/O I/Omapped I/O

It uses16bitaddress Ituses8bitaddress
MemoryrelatedinstructionsMOV,LDASTAXare I/Orelated instructionsINandOUT areused
used
Datatransferbetween anyregisterandI/O Datatransferbetween accumulatorandI/O
Morehardware isneededtodecode16bitaddress Lesshardwareisneededtodecode8bitaddress
Memorymap64K isshared 256I/Pdevices &256O/Pdevicesareshared.

**************************************************************************************************
WriteshortnotesonDatatransferconcept
******************************************************************************************
DataTransferConcepts

 The8085microprocessorisaparalleldevice.Thatmeansittransferseightbitsofdatasimultaneouslyovereight
datalines (parallel I/Omode).

 Howeverinmanysituations,theparallelI/Omodeiseitherimpracticalorimpossible.Forexample,paralleldataco
mmunication over along distancebecomesveryexpensive.

 Similarly,paralleldatacommunicationisnotpossiblewithdevicessuchasCRTterminalorCassettetapeetc

Typesof Datatransferscheme

DatatransferbetweenmicroprocessortomemoryandmicroprocessortoI/OdevicesisexplainedinthefollowingwaysThedat
atransfercanbeclassifiedinto

1. Paralleldatatransfer
2. Serialdatatransfer

I. Paralleldatatransfer

ParalleldatatransferschemeisfasterthanserialI/Otransfer.inparalleldatatransfer8-bitdatasendalltogetherwith 8
parallel wire. Itis furtherdivided into

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 ProgrammedI/O
 InterruptI/O
 DMA
ProgrammedI/O :

 HeretheprocessorhastocheckwhethertheI/OdeviceisreadyornotthroughtheReadysignaloftheI/Odevice.
 Ifthe ready signalishighthenitwillsendthe datatotheI/Odevice.
 OtherwiseitwillcontinuouslychecktheReadysignal.
 TheprocessorisbusyincheckingtheReadysignal.
 Thedrawbackiswastageof time.

InterruptI/O:

 InthismethodtheI/OdevicewillinterrupttheProcessorthroughtheINTRsignaltoindicatetotheprocessorthat
itis ready to accept thenext data.
 Thentheprocessor willsendtheINTAsignal.
 Thentheprocessor stopsitsnormalexecutionand starttransferringthedata tothe I/Odevice.
DMA:
 UsingDMAI/OdevicecandirectlytransferthedatatotheMemoryusingtheAddressandDatabusesofProcessor.
II. SerialdataTransfer

 SomeoftheexternalI/0devicesreceiveonlytheserialdata.NormallyserialcommunicationisusedintheMulti
processorenvironment.
 InserialI/Omodetransferasingle bitofdataonasinglelineatatime.ForserialI/O datatransmission mode, 8-
bit parallel word is converted to a stream of eight serial bit using parallel-to-serialconverter.
 Similarly, in serial reception of data, the microprocessor receives a stream of 8-bit one by one
whicharethenconvertedto8-bitparallelwordusingserial-to-
parallelconverter.8051hastwopinsforserialcommunication.
 SID-SerialInput data.
 SOD-SerialOutputdata

************************************************************************************************
Explain the interrupt structure of 8085.(Dec 2013, April 2015,Dec 2015,June 2014,June
2016)Explaintheinterruptsof8085withitstypeswithinterruptserviceroutine.(April2018,Dec2018)
******************************************************************************************

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5. Interruptsin8085
Interr
uptDe
finitio
n:
1. Interrupt is the mechanism by which the processor is made to transfer control from its current
programexecution to another program having higher priority. The interrupt signal may be given to the
processorbyany external peripheraldevice

2. Interrupts are the signals generated by the external devices to request the microprocessor to perform
atask.Thereare 5 interruptsignals, i.e.TRAP, RST7.5, RST6.5,RST5.5,and INTR.

Typesof interrupt

Interruptareclassifiedintofollowinggroupsbased ontheirparameter.

VectorandNon-Vector interrupt

 Vectorinterrupt−Inthistypeofinterrupt,theinterruptaddressisknowntotheprocessor.Forexample:RST7.5,
RST6.5, RST5.5, TRAP.

 Theaddresstowhichprogramcontrolistransferredare

 Name Vectoredaddress

 TRAP 0024(4.5X0008)

 RST5.5 002C(5.5 X0008)

 RST6.5 0034(6.5 X0008)

 RST7.5 003C(7.5 X0008)

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 Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the processor
so,theinterruptaddressneedstobesentexternallybythedevicetoperforminterrupts.Forexample: INTR.

MaskableandNon-Maskable interrupt

 Maskableinterrupt−Inthistypeofinterrupt,wecandisabletheinterruptbywritingsomeinstructionsinto
theprogram.Forexample:RST7.5,RST6.5, RST5.5.

 Non-
Maskableinterrupt−Inthistypeofinterrupt,wecannotdisabletheinterruptbywritingsomeinstructionsint
o theprogram.Forexample:TRAP.

The „EI‟ instruction is a one byte instruction and is used to Enable the maskable
interrupts.The„DI‟ instructionisa
onebyteinstructionandisusedtoDisablethemaskableinterrupts

SoftwareandHardwareInterrupt

 Software interrupt − In this type of interrupt, the programmer has to add the instructions into
theprogram to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1,
RST2,RST3,RST4, RST5, RST6,andRST7.

 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP,RST7.5,RST6.5, RST5.5, INTA.

Note−NTAisnotaninterrupt,itisusedbythemicroprocessorforsendingacknowledgement.TRAPhasthehighestpriority,the
n RST7.5andsoon.

Priorityofinterrupt

Interrupt Priority

TRAP 1

RST7.5 2

RST6.5 3

RST5.5 4

INTR 5

InterruptServiceRoutine(ISR)
Asmallprogramoraroutinethatwhenexecuted,servicesthecorrespondinginterruptingsourceiscalledanISR.

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Figure:Interruptserviceroutineprocedure

1. It allowstheexternaldevices tointerruptthenormal programexecutionofthe microprocessor.

2. When microprocessor receives interrupt signal, it temporarily stops current program and starts
executingnewprogramindicatedby theinterrupt signal.
3. Interruptsignalsaregeneratedbyexternalperipheraldeviceslikekeyboard,sensors, printersetc.
4. Afterexecutionofthenewprogram,microprocessorreturns backtothepreviousprogram.

Interruptstructureof8085

Figure:Interruptstructureof8085

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TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is enabled until
itgets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory. This
interrupttransfersthecontroltothelocation 0024H.

RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt
isexecuted,theprocessorsavesthecontentofthePCregisterintothestackandbranchesto 003CHaddress.

RST6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is
executed,theprocessorsavesthecontent of thePCregister into thestack andbranchesto 0034Haddress.
RST5.5
Itisamaskableinterrupt.Whenthisinterruptisexecuted,theprocessorsavesthecontentofthePCregisterintothestackand
branchesto002CHaddress.
INTR
Itisamaskableinterrupt,havingthelowestpriorityamongallinterrupts.Itcanbedisabledbyresettingthemicroprocessor.
WhenINTRsignalgoeshigh,thefollowingeventscanoccur −
 Themicroprocessor checks thestatusofINTRsignalduringtheexecutionof eachinstruction. 
 WhentheINTRsignalishigh,thenthemicroprocessorcompletesitscurrentinstructionandsendsactivelowinter
ruptacknowledgesignal.

 Wheninstructionsarereceived,thenthemicroprocessorsavestheaddressofthenextinstructiononstackandexec
utesthereceivedinstruction.
• TheInterruptEnableflipflopis manipulatedusingtheEI/DI instructions.

• TheindividualmasksforRST5.5,RST6.5andRST7.5are manipulated usingtheSIMinstruction.

ThisinstructiontakesthebitpatternintheAccumulator andappliesittotheinterruptmask
enablinganddisablingthespecificinterrupts

SIMInstruction:

The SIM instruction is used to mask or unmask RST hardware interrupts. When executed, the SIM
instructionreads the content of accumulator and accordingly mask or unmask the interrupts. The format of
control word tobestoredintheaccumulatorbeforeexecuting SIMinstructionis asshownin Fig.

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RIMInstruction:
RIM instruction is used to read the status of the interrupt mask bits. When RIM instruction is executed,
theaccumulator is loaded with the current status of the interrupt masks and the pending interrupts. The format
andthemeaningofthedatastoredin theaccumulatorafter execution ofRIMinstructionisshowninFig

 Ifthe maskbitis0,theinterruptisavailable.

 If the maskbitis1,theinterruptismasked

Ex:Write anassemblylanguageprogram to enablesalltheinterruptsin8085afterreset.

EI : Enable
interruptsMVIA, 08H
:Unmasktheinterrupts
SIM :SetthemaskandunmaskusingSIMinstruction
******************************************************************************************

Basicoperationsof Microprocessor

Themicroprocessorperformsprimarily fouroperations:
I. MemoryRead: Readsdata(orinstruction)from memory.
II. Memory Write:Writesdata(or instruction)intomemory.
III. I/ORead:Acceptsdatafrominputdevice.
IV. I/OWrite:Sendsdata tooutputdevice.
The8085processorperformsthesefunctionsusingaddressbus,data busandcontrolbusasshowninFig

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TimingDiagram

 TimingDiagramisagraphicalrepresentation.
 It representstheexecutiontimetakenbyeach instructioninagraphicalformat.
 Theexecutiontimeisrepresented inT-states.

1. Instruction cycle: this term is defined as the number of steps required by the CPU to complete the
entireprocess ie. Fetching and execution of one instruction. The fetch and execute cycles are carried out
insynchronizationwith theclock.

2. Machine cycle: It is the time required by the microprocessor to complete the operation of accessing
thememory devices or I/O devices. In machine cycle various operations like opcode fetch, memory
read,memorywrite, I/Oread,I/O writeareperformed.
3. T-state:Each clockcycleiscalled asT-states.

MACHINECYCLESOF8085
The8085microprocessor has5basicmachine cycles. Theyare
1. Opcodefetch cycle(4T)
2. Memoryreadcycle(3T)
3. Memorywritecycle(3T)
4. I/Oread cycle(3 T)
5. I/Owritecycle(3T)

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Opcodefetch
 Themicroprocessorrequires instructionstoperformany particularaction.
 In ordertoperform these actionsmicroprocessorutilizesOpcode
whichisapartofaninstructionwhichprovidesdetail (ie.whichoperation µpneeds toperform) to
microprocessor.

MemoryRead
 For exampleMVI A,32 (April2018)

 Thetotalcycle consistsof7Tstatesand2machinecycles.opcode fetchandmemoryread.

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 At the end of opcode fetch the PC is incremented thus the address is 2001Hand the
instructiondecoderhas3EH.Nowtheoperandisto beread fromthememoryto RegisterA.
 The2ndm/ccycle are similarto first3statesofopcode exeptthestatus signal(S0=0andS1=1)

Memory Write
 The memory write machine cycle is executed by the processor to write a data byte in a
memorylocation.
 Theprocessortakes,3Tstatestoexecutethismachinecycle

I/Oread

 The I/O Read cycle is executed by the processor to read a data byte from I/O port or from
theperipheral.
 Theprocessortakes3Tstatestoexecutethismachinecycle.
 TheINinstructionusesthismachine cycleduringtheexecution.

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I/Owrite

 ExampleOUT01H storedatmemorylocation2050.Theopcode ofthe instructionisD3

 Theprocessortakes, 10Tstatestocompletethecycle.Itrequires
3machinecycleopcodefetch,memoryreadand memorywrite.

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UNITIIPROGRAMMING
OF8085PROCESSOR

Instruction -format and addressing modes – Assembly language format –

Data transfer,datamanipulation&controlinstructions–
Programming:Loopstructurewithcounting&Indexing– Lookuptable-Subroutine
instructions–stack
***************************************************************************************
**

8085 InstructionFormat

1. Instruction:

 It is a command given to the microprocessor to perform given task on

specifieddata.Each instruction has two parts viz. task to be performed known as

operationcodeoropcode andsecondisthedatatobeoperateduponknownasoperand.

 The Operand can be used in many different ways e.g. 8 bit data or 16 bit data

orinternal register ormemorylocationor8bitor16bitaddress.

 8085 Instructions can be classified based on the size they occupy in memory or

bythefunctionstheyperform.Figureshowstheclassificationoftheinstructions.

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Fig:ClassificationofInstructionSetof8085

*************************************************************************************
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************************************************************************************
1.1.InstructionFormat
Based onthesize, theinstructionscanbeclassifiedareasfollows
OnebyteInstructions:
Theseinstructionsareofonebyteinsizeandhenceoccupyonememorylocationin RAM.
Examples are CMA, RLC, RRC, RAL, RAR, STC, CMC etc. These instructionsdo not
require any operand to be specified with the instructions; instead the operandis
impliedintheinstructions.

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TwoByteInstruction:

These instructions of two byte (16-bits) in size and hence will occupy
twomemorylocationsinRAM.Examplesofsuch instructionsareMVIC,0A;

ThreeByteInstructions:
Theseareofthreebyteinsizeandhenceoccupythreelocationsinmemory(RAM).
Examplesofsuch instructionsare CALL,JMPetc.

***************************************************************************************
**
ExplaintheclassificationofInstructionsetwithexample.
Explainlogicalinstructionwithexample. (December2015)
***************************************************************************************
**
2. InstructionSetClassification

An instruction is a binary pattern designed inside a microprocessor to perform

aspecific function. The entire group of instructions, called the instruction set,
determineswhatfunctionsthe microprocessor canperform.

Theseinstructionscanbeclassifiedintothefollowingfivefunctionalcategories:

 Datatransfer(copy)operations,
 Arithmeticoperations,
 Logicaloperations,
 Branchingoperations,and
 Machine-controloperations.

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1DataTransfer Croup

Thedatatransferinstructionsmovedatabetweenregistersorbetweenmemoryandregisters.

 MOV Move
 MVI MoveImmediate
 LDA LoadAccumulatorDirectlyfromMemory
 STA StoreAccumulatorDirectlyinMemory
 LHLD LoadH& LRegisters DirectlyfromMemory
 SHLD StoreH& LRegisters DirectlyinMemory

An'X'inthenameofadatatransferinstructionimpliesthatitdealswitharegisterpair(16-bits);

 LXI LoadRegisterPairwithImmediatedata
 LDAX LoadAccumulatorfromAddressinRegisterPair
 STAX StoreAccumulatorinAddressinRegisterPair
 XCHG ExchangeH &LwithD&E
 XTHL ExchangeTopofStackwithH& L

2ArithmeticGroup
Thearithmeticinstructionsadd,subtract,increment,ordecrementdatainregisters
ormemory.
 ADD AddtoAccumulator

 ADI AddImmediateDatatoAccumulator

 ADC Addto AccumulatorUsing CarryFlag

 ACI AddimmediatedatatoAccumulatorUsing Carry

 SUB SubtractfromAccumulator

 SUI SubtractImmediateDatafromAccumulator

 SBBSubtractfromAccumulatorUsingBorrow(Carry)Flag

 SBI SubtractImmediatefromAccumulatorUsingBorrow(Carry)Flag

 INR IncrementSpecifiedByte byOne

 DCR DecrementSpecifiedBytebyOne registerPairbyOne

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 DCX DecrementRegisterPairby One

 DAD DoubleRegisterAdd;AddContentofRegisterPairtoH &LRegisterPair

3 LogicalGroup
This group performs logical (Boolean) operations on data in registers and memory
andon condition flags. The logical AND, OR, and Exclusive OR instructions enable you to
setspecificbitsintheaccumulator ON orOFF.

 ANA LogicalANDwith Accumulator

 ANI LogicalANDwithAccumulatorUsingImmediateData
 ORA LogicalORwithAccumulator
 OR LogicalORwithAccumulatorUsingImmediate Data
 XRA ExclusiveLogicalORwithAccumulator
 XRI ExclusiveORUsingImmediateData

The Compare instructions compare the content of an 8-bit value with the contents
oftheaccumulator;
 CMP Compare
 CPI CompareUsingImmediateData

The rotate instructions shift the contents of the accumulator one bit position to the
leftorright:

 RLC RotateAccumulatorLeft

 RRC RotateAccumulatorRight

 RAL RotateLeftThroughCarry
 RAR RotateRightThroughCarry

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Complementandcarryflaginstructions:
 CMA ComplementAccumulator
 CMC ComplementCarryFlag
 STC SetCarryFlag
4 BranchGroup
The branching instructions alter normal sequential program flow,
eitherunconditionallyorconditionally.Theunconditionalbranchinginstructionsareas
follows:
 JMP Jump
 CALL Call
 RET Return

Conditional branching instructions examine the status of one of four condition flags
todetermine whether the specified branch is to be executed. The conditions that may
bespecifiedareasfollows:

 NZ NotZero(Z= 0)
 Z Zero(Z= 1)
 NC NoCarry(C=0)
 C Carry(C=1)
 PO ParityOdd(P=0)
 PE ParityEven(P= 1)
 P Plus(S= 0)
 M Minus(S=1)

Thus,theconditionalbranchinginstructionsarespecifiedasfollows:

Jumps Calls Returns

INC CNC RNC(No Carry)
JNZ CNZ RNZ(Not Zero)
JM CM RM (Minus)
JP0 CPO RPO(ParityOdd)
JM CM RM(Minus)
JPE CPE RPE(ParityEven)
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JP0 CPO RPO(ParityOdd)

Twootherinstructionscanaffectabranchbyreplacingthecontentsortheprogramcounter:

 PCHL MoveH &L to ProgramCounter

 RST SpecialRestartInstructionUsed withInterrupts

5 .StackInstructions
ThefollowinginstructionsaffecttheStackand/orStackPointer

 PUSH PushTwo bytesofDataontotheStack

 POP PopTwoBytesofDataofftheStack
 XTHL ExchangeTopofStackwithH &L
 SPHL Movecontent ofH& L toStackPointer

6 .I/0instructions
 IN InitiateInputOperation
 OUT InitiateOutputOperation
7 MachineControlinstructions

 EI EnableInterruptSystem
 DI DisableInterruptSystem
 HLT Halt
 NOP NoOperation

***********************************************************************************************
**
Defineaddressingmode.Writethetypesofaddressingmodeswithexample.(December2014)(Decemb

er2015)(April2015)(April2018)(Dec2018)

***************************************************************************************

**

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AddressingModes
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Various ways of specifying the operands or various formats for specifying

theoperandsiscalledaddressingmode

 Implicitaddressing

Thismodedoesn’trequireanyoperand;thedataisspecifiedbytheopcodeitself.

 CMA–Complementthecontents ofaccumulator

 Immediateaddressing

Inthismode,the 8/16-bitdataisspecifiedintheinstructionitself asoneofitsoperand.

 MVIB,05H means05iscopiedintoregisterB.

 ADI06H

 Directaddressing–

Inthismode,thedataisdirectlycopiedfromthegivenaddressto theregister.

 STA2400H,IN02H

 STA2400Hmeansthedataataddress2400iscopiedtoregisterA.

 Registeraddressing

Inthismode,thedataiscopiedfromoneregister to another.

 MOVA,B

 ADDB

 Registerindirectaddressing

In this mode, the data is transferred from one register to another by using

theaddresspointedbythe register.

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 LDAXB,

 STAXD

LDAXB meansdataistransferred

fromthememoryaddresspointedbytheregisterpair BC to theregisterA.

***************************************************************************************

**

WriteshortnotesonSTACKandSubroutine

**************************************************************************************

4. STACK:

Stackisanareaofmemoryidentifiedbytheprogrammerfortemporarystorageofinformat

ion.

 Stackisa LIFOstructure.

 Stack normally grows backwards into memory-the programmer defines

thebottomofthestackandthestackgrows upinto reducingaddress range.

 Stackisdefined bysettingtheSP(stackpointer)register.LXISP,FFFFH

 Thesizeofthestackis limitedonlybytheavailablememory.

 Informationis savedonthestackbyPUSHingiton.

 Informationis retrievedfromthestackbyPOPing itoff.

 The 8085 provides two instructions:PUSH and POP for storing information

onthestackandretrievingit back.

 BothPUSH andPOPworkwith registerpairsonly.

PUSH

instructionEX:

PUSHB
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Stepstobefollowed forPUSHBonebyteinstruction

 DecrementSP

 Copythecontents ofregisterBtothememorylocationpointedbySP.

 DecrementSP

 Copythecontents ofregisterCtothememorylocationpointedto bySP.

POPinstruction:

EX: POP D

Stepstobefollowed forPOPDonebyteinstruction

 Copythecontents ofthememorylocationpointedto bytheSP toregisterE.

 IncrementSP

 Copythecontents ofthememorylocationpointedto bytheSPtoregisterD.

 IncrementSP

Operationofthestack:

 Duringpushing,thestackoperatesina'decrementthenstore'style-

Thestackpointerisdecrementedfirst,thentheinformationisplacedonthestack

 Duringpopping,thestackoperatesina"usethenincrement'style.-

Theinformationisretrievedfrom thetopofthe stackandthenthepointerisincremented.

 TheSPpointeralwayspointstothe"top ofthestack"

LIFO:

TheorderofPUSHsandPOPs must be opposite of each other in order to

retrieveinformationbackintoitsoriginal location.

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PUSH

BPUSH

.....POP

DPOP

Reversing the order of the POP instructions will result in the exchange of the

contentsofBC andDE

PSWregisterpair:

The 8085 recognizes one additional register pair called the

PSW(PROGRAMSTATUSWORD).Thisregisterpairismadeupoftheaccumulatorandtheflagregis

ters.

***************************************************************************Expl
ainthe use oflookuptable in8085.
***************************************************************************

5. Lookuptable

 Alookuptableisanarraythatreplacesruntimecomputationwithasimplerarrayindexingo

peration.

 The savings in terms of processing time can be significant, since retrieving a

valuefrom memory is often faster than undergoing an 'expensive' computation

orinput/outputoperation.

 The tables may be pre-calculated and stored in static program storage,

calculated(or "pre-fetched") as part of a program's initialization phase

(memorization), orevenstoredinhardware inapplication-specificplatforms.

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 L kuptablesarealsousedextensivelytovalidateinputvaluesbymatching
o Valid (orinvalid)itemsinanarrayand,insomeprogramming
o

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languages,mayincludepointerfunctions(oroffsetstolabels)toprocessthematchinginput.

ExampleoflookuptableAlgorithm

1. InitializeHLpair topointLookup table

2. Getthedata

3. Checkwhetherthegiveninputislessthan9

4. Ifyesgoto nextstepelsehalttheprogram

5. Addthedesiredaddresswiththeaccumulatorcontent

6. Storethe result

Program:

LXIH,5000

;InitialsieLookuptableaddressLD

A5050;Getthe data

CPI0A ;Check input >

9JCAFTER;ifyeserror

MVIA,FF ;Error

IndicationSTA5051

HLT

AFTER:MOVC,A

;AddthedesiredAddressM

VIB,00

DAD

BMOVA,M

STA5051;Storetheresult

HLT ;Terminatetheprogram
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LOOKUP TABLE:

5000 01
5001 04
500209
5003 16
5004 25
5005 36
5006 49
5007 64
5008 81

RESULT:

Input:Data

:05Hinmemorylocation5050Output:Data :

25H (Square of 5) in memory location 5051Input:Data

:11Hinmemorylocation 5050

Output:Data :FFH(ErrorIndication)inmemorylocation5051

**************************************************************************************************************

6.Sample8085AssemblyPrograms
Example-1:Writeassemblyprogramtoaddtwonumbers. (December2014)

MVI D,
8CHMVI C,
6EHMOV A,
CADDDOU
T
PORT1HLT
Example-
2:Writeassemblyprogramtomultiplyanumberby8Multiplyby2 is
equivalentto shifting.

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MVIA,40H
RLC
RLC
RLC
OUT
PORT1HLT
Example-2:Writeassemblyprogramtomultiplytwo8bitnumber

MVIB,07H

MVI C,

06HXRAA
GO ADD
BDCR
CJNZGO
STA
4A00HLT

Example-3:Writeassemblyprogramtofindgreatest betweenthetwonumbers.
MVI B,
30HMVI C,
40HMOV
A, BCMPC
JZ
EQUJC
GRT
OUT
PORT1HLT
EQU:MVIA,01HO
UT PORT1
HLT
GRT:MOVA,CO
UT PORT1HLT

WriteanassemblylanguageprogramfortogenerateFibannociseries usingsubroutines(Dec2014)
MVI
A,00STA
8000MVI
A,01STA
8001MVI
B,08LXIH,
8000
BACK:MOVA,MI
NXH
ADD
MINX
HMOV
M,ADCRB
DCXHJNZ
BACK
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HLT

Write anassemblylanguageprogram fortomultiplytwo16bitnumbers. (June2016)

LXIH,
0000LXIB,
1CD2LXISP,
01AD

LXID, 0000
MUL DAD
SPJNC
DOWNINX
D
DOWN DCXB
MOV
A,BORA
CJNZMU
L
SHLD
4A00
XCHGSHLD
4A02HLT

Programming using subroutine

InstructionsGenerationofSquarewaveformu
singDAC

ProgrammingusingLoopstructurewithCountingandIndexing
(i) 16bitMultiplication

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(ii) Findingthemaximumnumberinthegivenarray

Developanalgorithmand8085assemblylanguageprogramtosort100bytetypedata.Explaintheinstruction usedin
theprogram.(Dec2018)

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L3 MVIB,00
LXI

H,4200MOV

C,MINXH

DCR C

L2

MOVA,MI

NX

HCMPM

JC L1

MOV

D,MMOV

M,ADCX

HMOVM,D

MVIB,01

L1 DCR C

JNZ

L2

DCRB

JZ

L3

HLT

INPUT42

0099

4201 data1

…………….
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4300 data100

&&&&&&&&&&&&&&&&&&&&&&&&&&

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UNIT
IIIMICROCONTROLL
ER
Hardware Architecture, pinouts – Functional Building Blocks of Processor – Memory organization – I/O ports and
datatransfer concepts– Timing Diagram – Interrupts- Data Transfer, Manipulation, Control Algorithms& I/O
instructions,ComparisontoProgramming conceptswith 8085.

INTRODUCTION:
General-purposemicroprocessorcontains
 NoRAM
 NoROM
 NoI/Oports
ItmustaddRAM,ROM,I/Oports,andtimersexternallytomakethemfunctional.Itmakesthesystembulkierandmuchmoreexpensive
.Ithasthe advantageofversatilityontheamount ofRAM,ROM, andI/Oports

Microcontrollerhas
 CPU(microprocessor)
 RAM
 ROM
 I/Oports
 Timer
 ADCandotherperipherals

The fixed amount of on-chip ROM, RAM, and number of I/O ports makes them ideal for many applications
inwhichcostandspacearecritical.Inmanyapplications,thespaceittakes,thepoweritconsumes,andthepriceperunitaremuch
morecriticalconsiderationsthan thecomputingpower.

Whatisamicrocontroller?

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Adevicewhichcontainsthemicroprocessorwithintegratedperipheralslikememory,serialports,parallelports,timer/counter,int
erruptcontroller,dataacquisitioninterfaceslikeADC,DACiscalledmicrocontroller

ComparisonbetweenMicroprocessorandMicrocontroller

Microprocessor Microcontroller
1 Microprocessor contains ALU, general 1. Microcontroller contains thecircuitry
purposeregisters, stack pointer, program counter, ofmicroprocessor and in addition ithas built- in
clock timingcircuitandinterruptcircuit ROM,RAM,I/Odevices, timersandcounters.

2 It has many instructions to move data 2. It has one or two instructions to

betweenmemoryandCPU. movedatabetweenmemory andCPU.

3 Ithasoneortwobithandlinginstructions. 3. Ithasmanybithandlinginstructions.

4 Access times for memory and 4. Lessaccesstimesforbuilt-

I/Odevicesaremore inmemoryandI/Odevices

5 Microprocessor based 5. Microcontroller based system

systemrequiresmorehardware requireslesshardware reducing PCB size
andincreasing thereliability.

************************************************************************************************D
raw and Explain of architecture of 8051 microcontroller.(Nov 2010/May 2010,May 2015)
(MAY/JUNE2016),(NOV/DEC 2014),(APRIL/MAY2017)(April 2015)(April2018)
************************************************************************************************
ARCHITECTURE& BLOCKDIAGRAM OF8051MICROCONTROLLER
In 1981 ,intel corporation introduced an 8 bit microcontroller called the 8051.The 8051 is an 8-bit processor.
TheCPUcanworkon only8 bitsofdata ata time. The featuresof8051are

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1. Registersof8051

Themostwidelyusedregistersare
 A(Accumulator)forallarithmeticandlogicinstructions
 B,R0,R1,R2,R3,R4,R5,R6,R7
 DPTR(datapointer),
 PC(programcounter)
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 The R registers: The "R" registers are a set of eight registers that are named R0, R1, etc. up to R7.
Theseregisters are used as auxiliary registers in many operations. The "R" registers are also used to temporarily
storevalues.
 A and B Registers : The A and B registers are special function registers which hold the results of
manyarithmeticand logicaloperationsof8051.
 The A register is also called the Accumulator andasit‟s name suggests, is used as a general register
toaccumulatetheresultsofalarge number ofinstructions.
 By default, it is used for all mathematical operations and also data transfer operations between CPU and
anyexternalmemory

A
B
R0
DPTR DPH DPL
R1
R2 PC PC
R3
R4 Some805116-bitRegister
R5
R6
R7

Some8-
bitRegistersofth
e8051

Alltheaboveregistersare8bitsexceptDPTRandPC.

ProgramCounter(PC):
 8051hasa16-bitprogramcounter.
 Theprogramcounteralwayspointstotheaddressofthenextinstructiontobeexecuted.Afterexecutionofoneinstructionthe
programcounterisincrementedtopoint totheaddressof thenextinstructiontobeexecuted.

DataPointerRegister(DPTR):

 It isa16-bitregisterwhichistheonlyuser-accessible.
 DPTR,asthename suggests, isusedtopointto data.
 Whenthe8051accessesexternalmemoryitwillaccessexternalmemoryat theaddressindicatedbyDPTR.
 ThisDPTRcanalso beusedastwo8-registersDPHandDPL.

2. ROMmemory mapin8051 family

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 Themicrocontrollerwakesupatmemoryaddress0000whenitispoweredup.
 When8051ispoweredup,thePChasthevalueof0000init.ThismeansthatitexpectsthefirstopcodetobestoredatROMaddre
ss0000H.
 Forthisreason,in8051system,thefirstopcodemustbeburnedintomemorylocation0000HofprogramROM.Sincethisisw
here itlooks forthefirstinstructionwhen itis booted.
 ThefirstlocationofonchipROMofthis8051hasanaddressof0000andthelastlocationhastheaddressof0FFFH.

3. STACKPOINTER(SP)
 Theregisterusedtoaccessthestackiscalled SP(stackpointer)register.
 Thestackpointerinthe8051isonly8bitswide,whichmeansthatitcantakevalue00toFFH.When8051poweredup,
theSPregistercontains value07.

4. FlagbitsandPSWRegister:
 The8051hasan8-
bitProgramStatusWordregisterwhichisalsoknownasFlagregisterisusedtoindicatearithmeticconditionsand
logicalconditions suchas the carrybits.
 Inthe8-bitregister,only6-bitsareusedby8051.Thetwounusedbitsareuserdefinablebits.Inthe6-
bitsfourofthemareconditionalflags.
 TheyareCarry–CY,AuxiliaryCarry-AC,Parity-P,andOverflow-
OV.Theseflagbitsindicatesomeconditionsthatresultedafteraninstructionwas executed.

 ThebitsPSW3andPSW4aredenotedasRS0andRS1andthesebitsareusedtoselectthebankregistersoftheRAMlocation.T
he meaningofvariousbitsofPSW registeris shownbelow.
CY PSW.7 CarryFlag
AC PSW.6 AuxiliaryCarryFlag
FO PSW.5 Flag0availableforgeneralpurpose
RS1 PSW.4 RegisterBankselectbit1
RS0 PSW.3 Registerbankselectbit0
OV PSW.2 Overflowflag
--- PSW.1 Userdefinableflag
P PSW.0 Parityflagset/clearedbyhardware.

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TheselectionoftheregisterBanksandtheiraddressesaregivenbelow.

----------------------------------------------------------------------------------------------------------------------------------------------
ExplainRAMstructureof8051. [December2016]
Drawthememorystructureof 8051microcontroller. [December2017]
--------------------------------------------------------------------------------------------------------------------------------------------
5. 8051RegisterBanksandstackpointer

There are 128 bytes of RAM in the 8051 are assigned addresses 00 to 7FH. The 128 bytes are divided into three
differentgroupsas follows:
 1)Atotalof32bytesfromlocations00to1Fhexaresetaside forregisterbanksandthestack.
 2)Atotalof16bytesfromlocations20Hto2FHaresetasideforbit-addressableread/writememory.
 3)Atotalof80 bytesfromlocations30Hto7FHareusedforreadand writestorage,called scratchpad




















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Fig:RAMmemoryspaceallocationinthe8051

Register bankin8051
 These32bytes are dividedinto4banksof registersinwhicheach bankhas8registers,R0-R7.

 RAMlocationfrom0to7aresetasideforbank0ofR0-R7whereR0isRAMlocation0,R1isRAMlocation1,R2
isRAMlocation 2,andso on,untilmemorylocation7 whichbelongstoR7ofbank0.

 ItismucheasiertorefertotheseRAMlocationswithnamessuchasR0,R1,andsoon,thanbytheirmemorylocations
Registerbank0isthedefault when8051 is poweredup.

BitaddressableRAM

 Thebit-addressableRAMlocationsare20Hto2FH.
 These16bytesprovide128bitsofRAMbit-addressability,since16×8=128.0to127(indecimal)or00to7FH.
 Thefirstbyte of internalRAMlocation20H hasbitaddress0to7H
 Thelastbyteof2FHhasbitaddress78Hto7FH.Internal
RAM locations 20-2FH are both byte-addressable
and bit addressable.
 Bit address 00-7FH belong to RAM byte
addresses20-2FH.
 Bitaddress80-FFHbelongtoSFRP0,P1,…
 Only registersA,B,PSW,IP,IE,ACC,
SCON,andTCONarebit-addressable.








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While all I/O ports are bit-addressable, In PSW register, two bits are set aside for the selection of
theregisterbanksUponRESET,bank0isselected.Wecanselectanyotherbanksusingthebit-
addressabilityofthePSW.

StructureofInternalROM(On–chipROM):

 The8051microcontroller has4kBofonchipROMbutit canbe extendedupto 64kB.

 ThisROMisalsocalled programmemoryorcode memory.
 TheCODEsegmentisaccessedusingtheprogramcounter(PC)foropcodefetchesandbyDPTRfordata.
 TheexternalROMisaccessedwhentheEA(activelow)pinisconnectedtogroundorthecontentsofprogramcount
erexceeds0FFFH.
 WhentheInternalROMaddressisexceededthe8051automaticallyfetchesthecodebytesfromtheexternalprogra
m memory.

6. STACKin8051

 Thestackisasectionof RAMusedbytheCPU tostoreinformationtemporarily.This

informationcouldbedataoranaddress.
 TheregisterusedtoaccessthestackiscalledtheSP(stackpointer)register.Thestackpointerinthe8051is only8
bitwide, whichmeans that itcan takevalueof00toFFH.
 Whenthe8051ispoweredup,theSPregistercontainsvalue07.RAMlocation08isthefirstlocationbeginused
forthestackby the8051.
 ThestoringofaCPUregisterinthestackiscalledaPUSHandloadingthecontentsofthestackbackintoaCPUregist
eris calledaPOP.

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PushingontotheStack

SPispointingtothelast usedlocationofthestack¾As we pushdataontothe stack, theSPis incrementedbyone.

Poppingfromthestack

With every pop, the top byte of the stack is copied to the register specified by the instruction and the
stackpointerisdecrementedonce.

************************************************************************************************

Explainthepindescription of8051microcontroller.(Dec 2010,June2013) (Dec2018)

******************************************************************************************
8051PINDIAGRAM

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Figure:8051pindescription

The8051familymembers(e.g,8751,89C51,89C52,DS89C4x0)have40pinsdedicatedforvariousfunctionssuchasI/O,-RD,-
WR,address,data,andinterrupts.Theycomeindifferentpackages,suchasDIP(dualin-linepackage),QFP(quadflatpackage),
andLLC(leadlesschipcarrier).

 Vccpin40providessupplyvoltagetothechip.Thevoltagesourceis
 GNDPin 20istheground.
 XTAL1ANDXTAL2(PIN19,18)
The 8051 has an on-chip oscillator but requires an external clock to run it .A quartz crystal oscillator is
connectedto inputs XTAL1 (pin19) and XTAL2 (pin18) .The quartz crystal oscillator also needs twocapacitors of
30pFvalue.

 If you use a frequency source other than a crystal oscillator, such as a TTL oscillator ¾It will be connected
toXTAL1.
 XTAL2isleftunconnected

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Thespeedof8051referstothemaximumoscillatorfrequencyconnectedtoXTAL.Ex.A12-MHzchipmustbeconnected to a
crystal with 12 MHz frequency or less. We can observe the frequency on the XTAL2 pin using theoscilloscope

 EA（pin31）：externalaccess
– There is no on-chip ROM in 8031 and 8032 .so the EA pin is connected to GND to indicate the code
isstoredexternally.
– EA pin is connected to Vcc because the 8051 family members all come with on-chip ROM to
storeprograms.

 PSEN（pin29）：Programstoreenable
– Thisisanoutputpinand isconnectedto theOEpin oftheROM.

 ALE（pin30）：Addresslatchenable
– The ALE pin is used for de-multiplexing the address and data bus ofPort 0which provides both
addressanddata

 RST（pin9）：Reset
– It isapower-onreset.
 Upon applying a high pulse to RST, the microcontroller will reset and all values in registers
willbelost.
– .
Resetvaluesofsome8051registers

PARELLELI/OPORTS
I/Oportpins
ThefourportsP0,P1,P2,andP3.Eachportuses8pins.AllI/Opinsarebi-directional.AlltheportsuponRESETare
configuredasoutput,readytobeusedasoutputports.Tomaketheportsasaninputport,itmustprogrammedassuchbywriting1 toallits
bits.

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The8051hasfourI/Oports

 Port0P0（P0.0～P0.7）

 Port1P1（P1.0～P1.7）

 Port2P2（P2.0～P2.7）

 Port3P3（P3.0～P3.7)

Port0
 Itisalso designatedas AD0-AD7,allowing ittobeused forbothaddressand data.
 Whenconnectingan8051/31toanexternalmemory,port0 providesbothaddressanddata.
 The8051multiplexesaddressanddatathroughport0tosavepins.
 ALEindicatesifP0hasaddressordata
 WhenALE=0,itprovidesdataD0-D7
 WhenALE=1,ithasaddressA0-A7
 It canbeusedforinputor output,eachpinmust beconnectedexternallytoa10Kohmpull-upresistor.
 ThisisduetothefactthatP0 isanopendrain,unlike P1, P2,and P3.

PORT1
Port 1occupies total of 8 pins 1 to 8 In contrast toPort 0,this port does not need any pull up resistor, since it has
alreadypullup resistorsinternally.

PORT2
 In8051-basedsystemswithnoexternalmemoryconnectionBothP1andP2areusedassimpleI/O.
 In8031/51-basedsystemswithexternalmemoryconnections,Port2mustbeusedalongwithP0toprovidethe16-bitaddress
fortheexternalmemory
 P0providesthelower8bits via A0–A7
 P2isused fortheupper8bitsofthe16-bitaddress,designated asA8–A15,anditcannotbeusedforI/O.
Port3
 It canbeusedasinputoroutput.
 Port3doesnotneedanypull-up resistors
 Port3hastheadditionalfunctionofprovidingsomeextremelyimportantsignals.

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Explain Parallel ports of 8051 with its circuit description in detail. [NOV/DEC 2016, APRIL
2015,April2018]
************************************************************************************************

PORT0
Port-0 can be used as a normal bidirectional I/O port or it can be used for address/data interfacing for
accessingexternal memory. When control is '1', the port is used for address/data interfacing. When the control
is '0', theportcanbeused asabidirectional I/Oport

.PORT0asanInputPort

Let us assume that control is '0'. When the port is used as an input port, '1' is written to the latch. In this
situationboth the output MOSFETs are 'off'. Hence the output pin have floats hence whatever data written on pin
isdirectlyread by read pin.

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PORT0asanOutputPort

Suppose we want to write 1 on pin of Port 0, a '1' written to the latch whichturns 'off'the lower FETwhile
due to '0' control signal upper FET also turns off as shown in fig. above. Here we want logic '1' on pin butwe
getting floating value so to convert that floating value into logic '1' we need to connect the pull up
resistorparallel to upper FET. This is the reason why we needed to connect pull up resistor to port 0 when we
wanttoinitializeport0 as anoutputport.

If we want to write '0' on pin of port 0, when '0' is written to the latch, the pin is pulled down by
thelowerFET.Hencetheoutputbecomeszero

Whenthecontrolis'1',address/data buscontrolstheoutputdriverFETs.Iftheaddress/data
bus(internal)is'0',theupperFETis'off'andthelowerFETis'on'.Theoutputbecomes'0'.Iftheaddress/databusis'1',theupper
FETis'on'andthelowerFETis'off'.Hencetheoutputis'1'.Hencefornormaladdress/datainterfacing(forexternalmemorya
ccess)nopull-upresistorsarerequired.Port-0latchiswrittentowith1'swhenusedforexternalmemory access.
PORT1:

Thestructure ofa port-1pinisshowninfigbelow.Ithas8pins (P1.1-P1.7).

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 Port-1 dedicated only for I/O interfacing. When used as output port, not needed to connect
additionalpull-upresistorlikeport 0.
 It has provided internally pull-up resistor as shown in fig. below. The pin is pulled up or down
throughinternalpull-up whenwewanttoinitializeas anoutputport.
 To use port-1 as input port, '1' has to be written to the latch. In this input mode when '1' is written to
thepin by the external device then it read fine. But when '0' is written to the pin by the external device
thentheexternal sourcemust sinkcurrent dueto internalpull-up.
 If the external device is not able to sink the current the pin voltage may rise, leading to a possible
wrongreading.
PORT2:

Thestructure ofa port-2pinisshowninfig.below.It has8-pins(P2.0-P2.7) .

Port-2 we use for higher external address byte or a normal input/output port. The I/O operation is
similarto Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again
due tointernalpull-up thereis limited currentdriving capability.

PORT3:
Port-3(P3.0-P3.7)havingalternatefunctionstoeachpin,Theinternalstructureofaport-3pinisshowninfigbelow.

Followingare thealternate functionsofport3

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*************************************************************************************************

Explainspecialfunctionregisterof8051. (Dec2010)

SPECIALFUNCTIONREGISTER
In 8051 microcontroller there arecertain registers which uses the RAM addresses from 80h to FFH and they
aremeant for certain specific operations. These registers are called Special functionregisters (SFRs).Some of these
registersarebitaddressable also.

The SFR (Special Function Register ) can be accessed by their names or by their addresses. Not all the
addressspace of 80 to FF is used by SFR.The unused locations 80H to FFH are reserved and must not be used by the
8051programmer
The list of SFRs and their functional names are given below. In these SFRs some of them are related to I/O
ports(P0,P1,P2 and P3) and some of them are meant for control operations (TCON, SCON, PCON) and remaining are
theauxillarySFRs, inthesense thatthey don'tdirectlyconfigurethe8051

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S.No Symbol NameofSFR Address(Hex)

1 ACC* Accumulator 0E0

2 B* B-Register 0F0
3 PSW* ProgramStatuswordregister 0DO
4 SP StackPointerRegister 81
5 DPL Datapointerlowbyte 82
DPTR DPH Datapointerhighbyte 83
6 P0* Port0 80
P1* Port1 90
8 P2* Port2 0A
9 P3* Port3 0B
10 IP* InterruptPrioritycontrol 0B8
11 IE* InterruptEnablecontrol 0A8
12 TMOD Tmiermoderegister 89
13 TCON* Timercontrolregister 88
14 TH0 Timer0Higherbyte 8C
15 TL0 Timer0Lowerbyte 8A
16 TH1 Timer1Higherbyte 8D
17 TL1 Timer1lowerbyte 8B
18 SCON* Serialcontrolregister 98
19 SBUF Serialbufferregister 99
20 PCON Powercontrolregister 87

*************************************************************************************************
Explainthevariousaddressingmodes of8051microcontroller.
*****************************************************************************************
ADDRESSINGMODES OF8051:

The way in which the data operands are accessed by different instructions is known asthe addressing
modes.There are various methods of denoting the data operands in the instruction. The 8051
microcontrollersupportsmainly5 addressing modes. Theyare
1. Immediateaddressingmode
2. DirectAddressingmode
3. Registeraddressingmode
4. RegisterIndirectaddressingmode
5. Indexedaddressing mode

1. Immediateaddressingmode:
The addressing mode in which the data operand is a constant and it is a part of the instruction itself
isknown as immediate addressing mode. Normally the data must be preceded by a # sign. This addressing
modecanbeused to transferthedatainto anyoftheregistersincluding DPTR.

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Example:
MOVA, # 27H :Thedata (constant) 27ismovedtotheaccumulator register
ADD R1,#45 H : Add the constant 45 to the contents of the
accumulatorMOVDPTR,#8245H :Movethedata8245
intothedatapointerregister.MOVP1,#21 H

2. Directaddressingmode:
The addressing mode in which the data operand is in the RAM location (00 -7FH) and the address of the
dataoperand is given in the instruction is known as Direct addressing mode. The direct addressing mode uses
thelower128 bytesofInternalRAM and theSFRs.
Example:
MOVR1,42H:MovethecontentsofRAMlocation 42intoR1register
MOV49H,A:MovethecontentsoftheaccumulatorintotheRAMlocation49.
ADDA,56H:Addthe contentsoftheRAMlocation56 totheaccumulator

3. Registeraddressingmode:
Theaddressingmodeinwhichthedataoperandtobemanipulatedliesinoneoftheregistersisknownasregister addressing
mode.
Example:
MOV A, R0: Move the contents of the register R0 to the
accumulatorADD A, R6 :Add the contents of R6 register to the
accumulatorMOVP1, R2:Movethecontentsofthe R2registerintoport1
MOVR5,R2:Thisisinvalid.Thedata transfer between theregistersisnotallowed.

4. RegisterIndirectaddressingmode:
TheaddressingmodeinwhicharegisterisusedasapointertothedatamemoryblockisknownasRegisterindirectaddressing
mode.
Example:
MOVA,@R0:MovethecontentsofRAM locationwhose addressisinR0intoA(accumulator)
MOV@R1,B: Movethecontentsof BintoRAMlocation whose addressisheldby
R1WhenR0andR1areusedaspointers, they mustbeprecededby@sign
Oneoftheadvantagesofregisterindirectaddressingmodeisthatitmakesaccessingthedatamoredynamic
thanstaticasin thecaseofdirectaddressingmode.

5.Indexedaddressingmode :
ThisaddressingmodeisusedinaccessingthedataelementsoflookuptableentrieslocatedinprogramROMspace of8051.
Example:MOVCA,@ A+DPTR
The 16-bit register DPTR and register A are used to form the address of the data element stored inon-chipROM.
Here Cdenotes code .In this instruction the contents of A are added to the 16-bit DPTR register to formthe16-bit
addressofthedataoperand.

ExplaintheDataTransferSchemesanditstypesindetail .
************************************************************************************************************************

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DATATRANSFERSCHEMES
 Inamicroprocessor-
basedsystem,thedatatransfertakesplacebetweentwodevicessuchasmicroprocessorandmemory,microproc
essorandI/OdevicesandmemoryandI/Odevices.
 AmicroprocessorbasedsystemoracomputermayhaveseveralI/Odevicesofdifferentspeed.
 AslowI/Odevicecannottransferdatabecauseittakessometimetogetready.
 TosolvethisproblemofspeedmismatchbetweenamicroprocessorandI/Odevicesanumberofdatatransfertec
hniques havebeendeveloped.

Theyareclassifiedintotwocategories.
1. Programmeddatatransferscheme
2. DMA(DirectMemoryAccess)datatransferscheme

ProgrammedDataTransferScheme
 ProgrammeddatatransferschemearecontrolledbytheCPU.
 Dataaretransferred anI/OdevicetotheCPUorviceversaunderthecontrolofprograms.
 Theseprogramsareexecuted bytheCPUwhenanI/Odeviceisreadytotransferdata.
 Itisusedwhensmallamountofdataaretobetransferred.Itisclassifiedinto followingthreecategories.

SynchronousDataTransferScheme
 Synchronousmeans“atthesametime”.
 Thedevicewhich sends dataandthedevicewhich receivesdataaresynchronizedwith thesameclock.
 ThedatatransferwithI/OdevicesisperformedbyexecutingINorOUTinstructionsforI/OmappedI/Ode
vices.

[OR]
 ThedatatransferwithI/Odevicesisperformedbyexecutingmemoryread/writeinstructionformemorymappe
dI/Odevices.
 Inthistypeofdatatransfer,thestatusoftheI/Odevicei.e.,whether
itisreadyornot,isnotexaminedbeforedataaretransferred.Hence,thistechniqueisrarelyusedforI/Odevices.

AsynchronousDataTransferScheme
 Asynchronousmeans“atirregularintervals”.
 Thedevicewhichsendsdataandthedevicewhichreceivesdataarenotsynchronizedwiththesameclock.
 Thistechniqueofdatatransferisused
whenthespeedofanI/Odevicedoesnotmatchthespeedofthemicroprocessorandalsothetimingcharac
teristicofI/Odeviceisnotpredictable.
 ThestatusoftheI/Odevicei.e.,whetherthedeviceisreadyornotischeckedbythemicroprocessor
beforethedata aretransferred.
 Ifitisnotready,themicroprocessorinitiatestheI/Odevicetogetreadyandthencontinuouslychecksthestatusof
theI/Odevicetillthe I/Odevicebecomes readytotransferdata.

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 WhenI/Odevice becomesready,the microprocessorsendsinstructiontotransferdata.
 Thismethodofdatatransfer isalsocalledhandshakingmode.
 The microprocessorsendsaninitiatingsignaltotheI/Odevicetogetready.
 WhenI/Odevicebecomesreadyitsendssignalstotheprocessortoindicatethatitisready.Suchsignals
arecalledhandshakesignals.

InterruptDrivenDataTransferScheme

 Inthisscheme,themicroprocessorinitiatesanI/Odevicetogetreadyandthenitexecutesitsmainprogram
insteadofremaininginaprogramlooptocheck the statusoftheI/O device.
 WhentheI/Odevicebecomesreadytotransferdata,itsendsahighsignaltothemicroprocessorthrougha
specialinputlinecalledaninterruptline.
 Inotherword,itinterruptsthenormalprocessingsequenceofthemicroprocessor.
 OnreceivingthemicroprocessorcompletesthecurrentinstructionathandandthenattendstheI/Odevice.
 Itsavesthecontents oftheprogramcounteronthestackfirstandthentakes
upasubroutinecalledInterruptService Subroutine(ISS).

DMATransferScheme
 DMAtransferschemeisnotcontrolledbytheCPU.DataaredirectlytransferredfromanI/Odevice
tothememoryorviceversa.
 ThedatatransferiscontrolledbytheI/OdeviceoraDMAcontroller.Itisusedwhenlargeamountofdataar
etobetransferred.
 DMAdatatransferschemeis fasterthanprogrammeddatatransferscheme.
 Itisusedtotransferdatafrommassstoragedevicessuchasharddisks,floppydisksetc.,
 Itisalso used forhigh-speedprinters.

DMAdatatransferschemeareofthefollowingtwotypes.BurstMode
 InwhichtheI/OdevicewithdrawstheDMArequestonlyafteronthedatabyteshavebeentransferrediscall
edburstmodeofdatatransfer.
 Itisemployedbymagneticdiskdrives.

CycleStealingTechnique
 Inthistechnique,along blockofdataistransferredbyasequenceofDMAcycles.
 In thismethodaftertransferringonebyteorseveralbytes theI/Odevicewithdraws DMArequest.
 ThismethodreducesinterferenceinCPU‟sactivities.
 Theinterferencecanbeeliminatedcompletelybydesigninganinterfacingcircuitrywhichcanstealbuscyclefo
rDMAdatatransfer onlywhenthe CPUisnotusing the systembus.

**********************************************************************************

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******************************************************************************************
Explainthe varioustypesof instructionset of8051microcontroller.(June2016)(Dec2015)(Dec2017)
******************************************************************************************

INSTRUCTIONSET IN8051 MICROCONTROLLER:

1. ArithmeticInstructions:

ADD
– 8-bitadditionbetweentheaccumulator(A)andasecondoperand.
• Theresultisalways intheaccumulator.
• TheCYflagisset/resetappropriately.
• ADDC
– 8-bitadditionbetweentheaccumulator,asecondoperandandthepreviousvalueoftheCYflag.
• Usefulfor16-bitadditionintwosteps.
• TheCYflagisset/resetappropriately.
• DA
– Decimaladjusttheaccumulator.
• Formattheaccumulatorintoaproper 2digitpackedBCDnumber.
• Operatesonlyontheaccumulator.
• WorksonlyaftertheADDinstruction.
• SUBB
– SubtractwithBorrow.
• Subtractanoperandandthepreviousvalueoftheborrow(carry) flagfromtheaccumulator.
• AA-<operand>- CY.
• Theresultisalways saved intheaccumulator.
• TheCYflagisset/resetappropriately.
• INC
– Incrementtheoperandbyone.
• Theoperandcanbearegister,adirectaddress,anindirectaddress,thedatapointer.
• DEC
– Decrementtheoperandbyone.
• Theoperandcanbearegister,adirectaddress,anindirectaddress.
• MULAB /DIV AB
– MultiplyAby Band placeresultinA:B.
– DivideAbyBandplaceresultinA:B.

2. logicalinstructionsin8051

• ANL/ ORL
– WorkonbytesizedoperandsortheCYflag.
• ANLA,Rn
• ANLA,direct
• ANLA,@Ri
• ANLA,#data
• ANLdirect,A
• ANLdirect,#data
• ANLC,bit
• ANLC,/bit

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• XRL
– Worksonbytesonly.
– CPL/CLR
– Complement/Clear.
– Workontheaccumulatororabit.
• CLR P1.2
• RL/RLC /RR/RRC
– Rotatetheaccumulator.
• RLandRRwithoutthecarry
• RLCandRRCrotatethroughthecarry.
• SWAPA
– Swaptheupperandlowernibblesof theaccumulator.
– Nocompareinstruction.
– Builtintoconditionalbranchinginstructions.

3. DataTransferInstructions

• MOV
– 8-bitdatatransferforinternalRAMandtheSFR.
• MOVA, Rn
• MOVA,direct
• MOVA,@Ri
• MOVA,#data
• MOVRn, A
• MOVRn,direct
• MOVRn,#data
• MOVdirect,A
• MOVdirect,Rn
• MOVdirect,direct
• MOVdirect,@Ri
• MOVdirect,#data
• MOV@Ri,A
• MOV@Ri,direct
• MOV@Ri,#data
• MOV
– 1-bitdatatransferinvolvingtheCY flag
• MOVC, bit
• MOVbit,C
• MOV
– 16-bitdatatransferinvolvingtheDPTR
• MOVDPTR,#data
• MOVC
– MoveCodeByte
• Loadtheaccumulatorwithabytefromprogrammemory.
• Mustuseindexedaddressing
• MOVCA,@A+DPTR
• MOVCA,@A+PC
• MOVX
– Datatransferbetweentheaccumulatorandabytefromexternaldatamemory.
• MOVXA,@Ri

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• MOVX A,@DPTR
• MOVX @Ri,A
• MOVX @DPTR,A
• PUSH/POP
– PushandPop adatabyte ontothestack.
– ThedatabyteisidentifiedbyadirectaddressfromtheinternalRAMlocations.
• PUSH DPL
• POP 40H
• XCH
– Exchangeaccumulatorandabytevariable
• XCH A,Rn
• XCH A,direct
• XCH A,@Ri
• XCHD
– Exchangelowerdigitofaccumulatorwiththelowerdigitof thememorylocationspecified.
• XCHDA,@Ri
• Thelower4-bitsoftheaccumulatorareexchangedwiththelower4-
bitsoftheinternalmemorylocationidentifiedindirectlyby theindexregister.
• Theupper4-bitsofeacharenotmodified.
Explainthevariousbitmanipulationinstructionin8051withexample.(Dec2018)
4. Boolean(or)Bitmanipulationinstructionsin8051.

• Thisgroupof instructionsisassociatedwiththesingle-bitoperationsofthe8051.
• ThisgroupallowsmanipulatingtheindividualbitsofbitaddressableregistersandmemorylocationsaswellastheCYflag.
– TheP,OV,andAC flagscannotbedirectlyaltered.
• Thisgroupincludes:
– Set,clear,and,orcomplement,move.
– Conditionaljumps.
• CLR
– ClearabitortheCYflag.
• CLRP1.1
• CLRC
• SETB
– SetabitortheCYflag.
• SETBA.2
• SETBC
• CPL
– ComplementabitortheCYflag.
• CPL40H ;Complement bit40ofthebitaddressablememory
• ORL/ ANL
– OR/AND a bitwiththeCYflag.
• ORL C,20H ; OR bit 20 of bit
addressablememorywiththeCYflag
• ANL C,/34H ; AND complement of bit 34 of
bitaddressablememorywiththeCY flag.
• MOV
– DatatransferbetweenabitandtheCYflag.
• MOV C,3FH ;CopytheCYflagtobit3Fofthebitaddressablememory.
• MOV P1.2,C ;CopytheCYflagto bit2 ofP1.

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• JC/JNC
– Jumptoarelative addressifCYisset/cleared.
• JB/JNB
– Jumptoa relativeaddressifabitisset/cleared.
• JB ACC.2,<label>
• JBC
– Jumptoa relative addressifabitissetandclearthebit.
– Instructionsthatareusedforsignal-bitoperationsareasfollowing

5. Branchinginstructionsin8051.

• The8051providesfourdifferenttypesofunconditionaljumpinstructions:
– ShortJump–SJMP
• Usesan8-bitsignedoffsetrelativetothe1stbyteofthenextinstruction.
– LongJump–LJMP
• Usesa16-bitaddress.
• 3byteinstructioncapableofreferencinganylocationintheentire64Kofprogrammemory.
– AbsoluteJump–AJMP
• Usesan11-bitaddress.
• 2byteinstruction
• Theupper3-bitsof theaddresscombinewiththe5-bit opcodetoform the1stbyteandthelower8-
bitsoftheaddressformthe2ndbyte.
• The11-bitaddressissubstitutedforthelower11-bitsofthePCtocalculatethe16-bitaddressofthetarget.
• Thelocationreferencedmustbewithinthe2KBytememorypagecontainingtheAJMPinstructio
n.
– IndirectJump–JMP
• JMP @A+ DPTR
• The8051provides2formsfortheCALLinstruction:
– AbsoluteCall–ACALL
• Usesan11-bitaddresssimilarto AJMP
• Thesubroutinemustbewithinthesame2Kpage.
– LongCall– LCALL
• Usesa 16-bitaddresssimilartoLJMP
• Thesubroutinecanbeanywhere.
– Bothformspushthe16-bit addressof thenextinstructiononthestackandupdatethestackpointer.
• The8051provides2formsforthereturninstruction:
– Returnfromsubroutine–RET
• Popthereturnaddressfromthestackandcontinueexecutionthere.

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– ReturnfromISV–RETI
• Popthereturnaddressfromthestack.
• Restoretheinterruptlogictoacceptadditionalinterruptsatthesameprioritylevelastheonejustprocessed.
• Continueexecutionattheaddressretrievedfrom thestack.
• ThePSWisnotautomaticallyrestored.

• The8051supports5differentconditionaljumpinstructions.
– ALLconditionaljumpinstructionsusean8-bitsignedoffset.
– Jumpon Zero –JZ/JNZ
• Jump iftheA==0/A!= 0
• Thecheckisdoneatthetimeoftheinstructionexecution.
– Jumpon Carry– JC/ JNC
• Jump iftheCflag isset/cleared.
– Jumpon Bit– JB/JNB
• Jump ifthespecifiedbitisset/cleared.
• Anyaddressablebitcanbespecified.
– Jump iftheBitissetthen Clearthebit– JBC
• Jump ifthespecifiedbitisset.
• Thenclearthebit.
• CompareandJumpif NotEqual–CJNE
– Comparethemagnitudeof thetwo operandsandjumpifthey arenotequal.
• Thevaluesareconsideredtobeunsigned.
• TheCarryflagisset/clearedappropriately.
• CJNE A,direct,rel
• CJNE A,#data,rel
• CJNE Rn,#data,rel
• CJNE @Ri,#data,rel
• DecrementandJumpifNot Zero–DJNZ
– Decrement the first operand by 1 and jump to the location identified by the second operand if the
resultingvalueisnotzero.
• DJNZ Rn,rel
• DJNZ direct,rel
• NoOperation
– NOP
BasicI/OInstructions

 IN,OUT,INSandOUTSare theinstructionsforthetransfer of datatoandfroman I/Odevice.

 INand OUTtransferdatabetweenan I/Odeviceandthemicroprocessor'saccumulator(AL,AXorEAX).
TheI/O addressisstoredin:
 RegisterDXasa16-bitI/Oaddress(variableaddressing).
 Thebyte,D8,immediately followingtheopcode(fixedaddress).

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 Only16-bits(A0toA15)are decoded.
 AddressconnectionsaboveA15areundefined forI/Oinstructions.
 0000H-03XXHareusedfortheISA bus.
 INSandOUTStransfertoI/OdevicesusingES:DIandDS:SI, respectively.

***********************************************************************************************Wi
th a neat Diagram explain what is interrupts and types of interrupts in 8051. [NOV/DEC 2016
,MAY/JUNE2016,APRIL/MAY2015]
************************************************************************************************
InterruptProgramming
An interruptis anexternalorinternaleventthatinterruptsthemicrocontrollertoinform itthata
deviceneedsitsservice.Asinglemicrocontrollercanserveseveral devicesby two ways
 Polling
 Themicrocontroller continuouslymonitorsthestatusofagivendevice
 Whentheconditionsmet, itperformstheservice.
 After that,itmoves ontomonitorthenextdevice untileveryone isserviced

Polling can monitor the status of several devices and serve each of them as certain conditions are met
Thepolling method is not efficient, since it wastes much of the microcontroller‟s time by polling devices that do
notneedservice
ex.JNBTF,target

 Interrupts
 Wheneveranydeviceneedsitsservice,thedevicenotifiesthemicrocontrollerbysendingitaninterruptsignal
 Uponreceivinganinterruptsignal,themicrocontrollerinterruptswhateveritisdoingandservesthedevice
 Theprogramwhichisassociatedwiththeinterruptiscalledtheinterruptserviceroutine(ISR)orinterrupthandler.

Foreveryinterrupt, theremustbeaninterruptserviceroutine(ISR),orinterrupthandler
 Whenaninterruptisinvoked,themicrocontroller runsthe interruptservice routine.
 Foreveryinterrupt,there isafixedlocationinmemorythatholdstheaddressof itsISR.
 ThegroupofmemorylocationssetasidetoholdtheaddressesofISRs iscalledinterruptvectortable

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 Stepsinexecutinganinterrupt

Figure:Interruptserviceroutine
1. Finishcurrentinstructionandsavestheaddressofthenextinstruction(PC)onthestack
2. It jumpstoafixedlocationinmemorycalledtheinterruptvector tablethatholdsthe addressoftheISR.

4. Itstartstoexecutetheinterruptservicesubroutineuntilitreachesthelastinstructionofthesubroutinewhichis
RETI(returnfrominterrupt)

5. UponexecutingtheRETIinstruction,themicrocontrollerreturnstotheplacewhereitwasinterrupted.GetPOP
PC from Stack.
6. Thenitstartstoexecute fromthataddress

 InterruptSources
Sixinterruptsareallocatedasfollows

Figure:8051Interruptsources

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 InterruptVectors

Uponreset,allinterruptsaredisabled(masked),meaningthatnonewillberespondedtobythemicrocon
trollerifthey areactivated
 Theinterruptsmustbeenabledbysoftware inorderfor themicrocontrollertorespondtothem.
 ThereisaregistercalledIE(interruptenable)thatisresponsibleforenabling(unmasking)anddisabling(masking)
theinterrupts.

Fig:Interruptstructureof8051
 InterruptRelatedRegister
Thevariousregistersassociatedwithinterruptsare
 InterruptEnable(IE)

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 InterruptPriority(IP)
 TimercontrolTCON)
 Serialcontrol(SCON)
1. InterruptEnable(IE)Register(EnablingandDisabling)
EA ----- ET2 ES ET1 EX1 ET0 EX0

D7 D6 D5 D4 D3 D2 D1 D0

 EX0/EX1:Enables(1)/disables(0)theexternalinterrupt0andtheexternalinterrupt1onportP3.2/P3.3
 ET0/ET1:Enables(1)/disables(0)theTimer0andTimer1interruptviaTF0/1
 ES:Enables(1)/disables(0)theserialportinterruptforsendingandreceivingdata
 EA:Enables(1)/disables(0)allinterrupts
Toenableaninterrupt,wetakethefollowing steps:
1. BitD7of theIEregister(EA)mustbesettohigh toallowtherestof registerto takeeffect
2. ThevalueofEA

 IfEA =1,interruptsare enabled andwillbe respondedtoiftheircorrespondingbitsinIEarehigh

 IfEA =0,nointerruptwillberespondedto,eveniftheassociatedbitintheIEregister ishigh.

2. InterruptPriority(IP)Register

 PS-IP.4-SerialPortInterruptPrioritybit
• PT1-IP.3-Timer1InterruptPrioritybit
• PX1-IP.2 External Interrupt1Prioritybit
• PT0-IP.1 Timer0Interrupt Prioritybit
• PX0-IP.0 External Interrupt0Prioritybit

Whenthe8051ispoweredup,the prioritiesare assignedaccordingtothe following

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Wecanalterthesequenceofinterruptprioritybyassigningahigherprioritytoanyoneoftheinterruptsby
programming aregistercalledIP(interruptpriority)
 Togiveahigherprioritytoanyoftheinterrupts,wemakethecorrespondingbitintheIPregisterhighWhentwo
ormoreinterruptbitsin theIPregisterareset to high
 Whiletheseinterruptshaveahigherprioritythanothers,theyareservicedaccordingtothesequenceofTable.
3. TCON(Timercontrol register)
Itisusedtoselect edge andtypeofexternalinterruptsEX0andEX1.
TCON(timercontrol)registerisan8-bitregister. TCONregisterisabit-addressableregister

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

D7 D6 D5 D4 D3 D2 D1 D0

 TF1:Timer1overflowflag.
 TR1:Timer 1runcontrolbit.
 TF0:Timer0overflag.
 TR0:Timer 0runcontrolbit.
 IE1:External interrupt1edgeflag.
 IT1:External interrupt1typeflag.
 IE0:External interrupt0edgeflag.
 IT0:External interrupt0typeflag
4. SCONRegister(Serialcontrolregister)
UsedtosetRIand TIinterruptflags ofserial communication

*************************************************************************************************

TimerInterruptProgramming

Thetimerflag(TF)israisedwhenthetimerrollsover
In pollingTF,we havetowaituntiltheTFisraised

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 The problem with this method is that the microcontroller is tied down while waiting for TF to be
raised,andcannotdo anything else
Usinginterruptssolvesthisproblem and,avoidstying downthecontroller
 If the timer interrupt in the IE register is enabled, whenever the timer rolls over, TF is raised, and
themicrocontrollerisinterruptedinwhateveritisdoing,andjumpstotheinterruptvectortabletoservicetheISR.
 In thisway,themicrocontrollercandootheruntilitisnotifiedthatthetimerhasrolledover.

The8051hastwoexternalhardwareinterrupts
 Pin12(P3.2)andpin13(P3.3)ofthe8051,designatedasINT0andINT1,areusedasexternalhardware interrupts
 Theinterrupt vector tablelocations0003Hand0013Haresetasidefor INT0andINT1
 Therearetwoactivationlevelsfortheexternalhardwareinterrupts
 Leveltriggered
 Edgetriggered

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Inthelevel-triggeredmode, INT0andINT1pinsarenormallyhigh
 Ifalow-levelsignalisappliedtothem,ittriggerstheinterrupt
 Thenthemicrocontrollerstopswhateveritisdoingandjumpstotheinterruptvectortabletoservicethatinterrupt
 Thelow-
levelsignalattheINTpinmustberemovedbeforetheexecutionofthelastinstructionoftheISR,RETI;otherwise,a
nother interrupt will begenerated
 Thisiscalledalevel-triggeredorlevelactivatedinterruptandisthedefaultmodeuponreset ofthe8051

PinsP3.2andP3.3areusedfornormalI/OunlesstheINT0andINT1bitsintheIEregisterareenabled

 AfterthehardwareinterruptsintheIEregisterareenabled,thecontrollerkeepssamplingtheINTnpinforalow-
level signal onceeach machinecycle
 Accordingtoonemanufacturer‟sdatasheet,
 Thepinmustbe held inalowstate untilthestart oftheexecution of ISR
 IftheINTnpinisbroughtbacktoalogichighbeforethestartoftheexecutionofISRtherewillbenointerrupt
 IfINTnpinisleftatalogiclowaftertheRETIinstructionoftheISR,anotherinterruptwillbeactivatedafteronei
nstruction isexecuted
 ToensuretheactivationofthehardwareinterruptattheINTnpin,makesurethatthedurationofthelow-levelsignal
is around4 machine cycles, but no more.

 Thisisdue tothe factthatthelevel-triggeredinterruptisnotlatched

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 Thusthepin mustbeheldinalowstateuntilthestartoftheISRexecution

Tomake INT0andINT1edgetriggeredinterrupts,wemustprogram thebitsofthe TCONregister

 TheTCONregisterholds,amongother bits,theIT0andIT1 flagbitsthatdetermine level-oredge-
triggeredmodeofthehardwareinterrupt
 IT0andIT1are bitsD0andD2of theTCONregister
 Theyarealsoreferred toasTCON.0andTCON.2sincetheTCONregisterisbitaddressable.

Inedge-triggeredinterrupts
 Theexternalsourcemustbeheldhighforatleastonemachinecycle,andthenheldlowforatleastonemachinecycle
 ThefallingedgeofpinsINT0andINT1arelatchedbythe8051andareheldbytheTCON.1andTCON.3bits
ofTCONregister
 Functionasinterrupt-in-serviceflags
 ItindicatesthattheinterruptisbeingservicednowandonthisINTnpin,andnonewinterruptwillberespondedt
o untilthis serviceis finished

Inthe8051thereisonlyoneinterruptset asideforserialcommunication
 Thisinterruptisusedtobothsendandreceive data
 Iftheinterruptbit intheIEregister(IE.4)is
enabled,whenRIorTIisraisedthe8051getsinterruptedandjumpsto memorylocation
0023HtoexecutetheISR
 InthatISRwemustexaminetheTIandRIflagstoseewhichonecausedtheinterruptandrespondaccordingly.

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ExplainTimermodesof8051microcontroller.(April2017)
****************************************************************************************
PROGRAMMINGTIMERSOF8051
1. TimerRegisters.
The8051hastwotimers/counters,theycan beusedeitheras
 Timers are used to generate a time delay or as Event counters to count events happening outside
themicrocontroller.
BothTimer0andTimer1registersare16bitswide.
 Since 8051 has an 8-bit architecture, each 16-bits timer is accessed as two separate registers of low
byteand high byte.The low byte register is called TL0/TL1 and the high byte register is called TH 0/TH1.It can
beaccessedlikeany otherregister
For example MOV TL0,#4FH
MOVR5, TH0

Figure:TimerRegisters

2. TMOD(TimermodeRegister)

Bothtimers0and1usethesameregister,calledTMOD(timermode),tosetthevarioustimeroperationmodes
 TMODisan8-bitregister
 Thelower 4bitsareforTimer0
 Theupper 4bitsareforTimer1

Ineach case,
 Thelower 2bitsareusedtosetthetimermode
 Theupper 2bitstospecifytheoperation

Figure:TMODRegister

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 Gate:Whenset,timeronlyrunswhileINT(0,1) ishigh.
 C/T:Counter/Timerselectbit.
 M1:Modebit1.
 M0: Modebit 0.

Timersof8051dostartingandstoppingbyeithersoftwareorhardwarecontrol
Forusingsoftwaretostartandstopthetimerwhere GATE =0
 Thestartandstopof thetimerare controlledbywayofsoftwarebytheTR(timerstart)bitsTR0andTR1

 TheSETBinstructionstartsit,anditisstoppedbytheCLRinstruction.
 TheseinstructionsstartandstopthetimersaslongasGATE=0 intheTMODregister
 The hardware way of starting and stopping the timer by an external source is achieved
bymakingGATE=1intheTMODregister.
 Theanotherregister usedintimerprogrammingisTCONregister.

3. TCON(Timercontrolregister)
TCON(timercontrol)registerisan8-bitregister. TCONregisterisabit-addressableregister

 TF1:Timer1overflowflag.
 TR1:Timer 1runcontrolbit.
 TF0:Timer0overflag.
 TR0:Timer 0runcontrolbit.
 IE1:External interrupt1edgeflag.
 IT1:External interrupt1typeflag.
 IE0:External interrupt0edgeflag.
 IT0:External interrupt0typeflag.
Modesofoperationof8051timers

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MODE1:16bitTimer
Thefollowingarethecharacteristics andoperationsofmode1:
1. Itisa16-bittimer;therefore,itallowsvalueof0000toFFFFHtobeloadedintothetimer‟sregisterTLandTH
2. AfterTHandTLareloaded witha16-bitinitialvalue,thetimermustbestarted.
 Thisisdone bySETBTR0fortimer 0andSETBTR1for timer1
3. After thetimerisstarted,itstartstocountup
 It countsupuntilitreaches itslimitofFFFFH

 Whenitrollsover fromFFFFHto0000,itsetshigh aflagbitcalled TF(timerflag)

 Eachtimerhasitsowntimerflag:TF0fortimer0,andTF1fortimer1.Thistimerflagcanbemonitored

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 Whenthistimerflagisraised,oneoptionwouldbetostopthetimerwiththeinstructionsCLRTR0orCLRTR1,
fortimer0 and timer1,respectively.
 .Afterthetimerreachesitslimitandrollsover,inordertorepeattheprocessTHandTLmustbereloadedwith
theoriginal value,and TFmust bereloadedto 0.
Togenerate atimedelay

1. LoadtheTMODvalueregisterindicatingwhichtimer(timer0ortimer1)istobeusedandwhichtimermode (0 or1)is
selected
2. Loadregisters TLandTHwithinitialcountvalue
3. Startthetimer
4. Keep monitoringthetimerflag(TF)withtheJNBTFx,targetinstructiontoseeif itisraised
 Getoutoftheloopwhen TFbecomeshigh
5. Stopthetimer
6. CleartheTFflagforthe nextround
7. GobacktoStep2toloadTH and TLagain.
MODE2:8bitTimerAutoreload

Thefollowingare thecharacteristics andoperationsofmode 2:

1. It isan8-bittimer;therefore,itallowsonlyvaluesof 00toFFH tobe loadedintothetimer‟sregister TH
2. After THisloadedwiththe8-bit value,the 8051givesacopyofittoTL
 Thenthetimermustbe started
 Thisisdonebytheinstruction SETBTR0for timer0 andSETBTR1for timer1
3. Afterthetimerisstarted,itstartstocountupbyincrementingthe TLregister
 ItcountsupuntilitreachesitslimitofFFH
 WhenitrollsoverfromFFH to00,itsetshightheTF(timerflag)
 When the TL register rolls from FFH to 0 and TF is set to 1, TL is reloaded automatically with
theoriginalvaluekept by theTHregister.

 To repeat the process, we must simply clear TF and let it go without any need by the programmer
toreloadtheoriginalvalue.

 This makes mode 2 an auto-reload, in contrast with mode 1 in which the programmer has to reload
THandTL.

Togenerate atimedelay
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1. LoadtheTMODvalueregisterindicatingwhichtimer(timer0ortimer1)istobeused,andthetimermode(mod
e2)isselected
2. LoadtheTHregisterswiththeinitialcountvalue
3. Starttimer
4. Keep monitoringthetimerflag (TF) withtheJNBTFx,targetinstructiontoseewhetheritisraised
 GetoutoftheloopwhenTFgoeshigh
5. CleartheTFflag
6. GobacktoStep4,since mode2isautoreload.
Timersascounters

 Timerscanalsobeusedascounterswhich are usedforcountingeventshappeningoutsidethe8051.

 Whenitisusedas a counter,itisapulse outsideof the8051 thatincrementsthe TH,TLregister.

 TMODandTH,TLregisters are thesameasforthe timerdiscussedpreviouslyexceptthesource ofthe
frequencyThe C/Tbit intheTMODregistersdecidesthesource oftheclockforthe timer.
 WhenC/T=1,thetimer isusedasacounter andgetsitspulsesfromoutsidethe8051.
 The counter counts up as pulses are fed from pins 14 and 15, these pins are called T0 (timer0
input)andT1(timer1 input).

 IfGATE=1,thestartandstopofthetimeraredoneexternallythroughpinsP3.2andP3.3fortimers0and1,
respectively
 Thishardwarewayallowstostartorstopthetimerexternallyatanytimeviaasimpleswitch

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 Thefrequencyforthe timerisalways1/12ththefrequencyofthe crystalattachedto the 8051,

regardlessofthe8051 version.

.Explaintheserialprogrammingof8051withitsassociatedregisters.[December2017]Explai
nhowtoprogramforsending andreceivingdataseriallyusing8051.
SERIALCOMMUNICATIONPROGRAMMING

Computerstransferdataintwoways:
 Parallel
Often8or morelines(wire conductors)are usedtotransfer datatoadevice thatisonlyafew feetaway
 Serial
Totransfer toadevice located manymetersaway,theserialmethodisused.The dataissentonebitatatime.

At the transmitting end, the byte of data must be converted to serial bits using parallel-in-serial-out
shiftregister
 Atthereceivingend,there isaserialin-parallel-outshiftregistertoreceive theserialdataandpacktheminto
byte.
 When the distance is short, the digital signal can be transferred as it is on a simple wire and requires
nomodulation.
 If data istobe transferredonthetelephone
line,itmustbeconvertedfrom0sand1stoaudiotones.Thisconversionisperformedby
adevicecalledamodem,“Modulator/demodulator.

Serialdatacommunicationusestwomethods
o Synchronousmethodtransfersablockofdataatatime.
o Asynchronousmethodtransfersasinglebyteatatime.
It ispossibletowrite software touseeither ofthesemethods,buttheprogramscanbetediousandlongThere are
special ICchipsmadebymany manufacturersforserialcommunications
 UART(universalasynchronousReceiver/transmitter)
 USART(universalsynchronous-asynchronousReceiver-transmitter)
mitte dandreceived,itisa duplex transmission
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39

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 Ifdata transmittedonewayatime,itisreferredtoashalfduplex.
 Ifdata cango bothwaysata time,itisfullduplex.
 Thisiscontrasttosimplextransmission.

Asynchronousserial datacommunicationis widelyusedforcharacter-oriented transmissions.

Each characterisplacedinbetween startandstopbits,thisiscalledframing.
Block-oriented datatransfersusethesynchronousmethod
The start bit is always one bit, but the stop bit can be one or two bits .The start bit is always a 0 (low) and
thestopbit(s)is 1 (high)

Therate ofdatatransferinserial datacommunicationisstatedinbps(bitspersecond).Anotherwidelyusedterminologyforbps

is baud rate

RS232
ItisaninterfacingstandardRS232wassetbytheElectronicsIndustriesAssociation(EIA)in1960.The
standardwassetlongbeforetheadventoftheTTLlogicfamily,itsinputandoutputvoltagelevelsarenotTTLcompatible
InRS232,a 1isrepresentedby-3~-25V,whilea 0bitis+3~+25V,making-3to+3undefinedSincenotallpins are
usedinPC cables,IBMintroducedtheDB-9 versionoftheserialI/Ostandard

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Handshakesignalsof MODEM

DTR(dataterminalready)
Whenterminalisturnedon,itsendsoutsignalDTRtoindicatethatitisreadyfor communication

DSR(datasetready)
When DCE is turned on and has gone through the self-test, it assert DSR to indicate that it is ready
tocommunicate
RTS(requesttosend)
WhentheDTEdevice hasbytetotransmit,itassertRTStosignalthemodemthatithasa byteofdatatotransmit
CTS(cleartosend)
Whenthemodemhasroomforstoringthedataitistoreceive,itsendsoutsignalCTStoDTEto
indicatethatitcanreceivethedatanow.
DCD(datacarrierdetect)
Themodemassertssignal DCDtoinformtheDTEthatavalidcarrierhas beendetected
andthatcontactbetweenitandtheothermodem is established
RI(ringindicator)
AnoutputfromthemodemandaninputtoaPCindicatesthatthetelephone isringingItgoes on
andoffin synchronous with theringing sound.

MAX232

MAX232 chip is called as a line driver which is required to convert RS232 voltage levels to TTL
levels,andviceversa.
 8051hastwopinsthatareusedspecificallyfortransferringandreceivingdata serially.
 These twopinsare calledTxDandRxDandare partoftheport3group(P3.0andP3.1).
 These pins are TTL compatible; therefore, they require a line driver to make them RS232 compatible.
Weneeda line driver(voltage converter) to convert the R232‟s signals to TTL voltage levels that will
beacceptable to 8051‟s TxDandRxDpins.

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Alinedriver suchasthe MAX232chipisrequiredtoconvertRS232voltage levelstoTTLlevels,andviceversa.

 8051hastwopinsthatareusedspecificallyfortransferringandreceivingdata serially.
 These twopinsare calledTxDandRxDandare partoftheport3group(P3.0andP3.1).
 ThesepinsareTTLcompatible;therefore,theyrequirealinedrivertomakethemRS232.compatible.

SBUFisan 8-bitregisterusedsolelyfor serialcommunication.

 For abyte data tobetransferredviatheTxDline,itmustbeplacedintheSBUFregister.
 The moment a byte is written into SBUF, it is framed with the start and stop bits and transferred serially
viatheTxDline.
 SBUFholdsthebyte ofdata whenitisreceivedby 8051RxDline.
 Whenthebitsare receivedseriallyviaRxD, the8051deframesitbyeliminatingthestopand
 startbits,makinga byte outofthedata received.

SCONisan8-bitregister usedtoprogramthe startbit,stopbit,anddatabitsofdata framing,amongother things

SM0,SM1
They determine the framing of data by specifying the number of bits per character, and the start and stop
bitsThisenablesthemultiprocessing capabilityofthe8051

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When8051receivesdataseriallyviaRxD,itgetsridofthestartandstopbitsandplaces thebyte inSBUFregister

It raisestheRIflagbittoindicatethatabyte hasbeen receivedandshouldbepickedupbefore it
islost
RIisraisedhalfway throughthestopbit

Inprogramming the8051totransfer characterbytesserially

1. TMODregister isloadedwiththevalue 20H,indicatingtheuseof timer 1inmode2(8-bitauto-reload) tosetbaudrate.

2. TheTH1isloadedwithoneofthe valuestosetbaudrate for serialdata transfer
3. TheSCONregister isloadedwiththevalue 50H,indicatingserialmode1,wherean8-bitdataisframedwithstartand
stop bits
4. TR1isset to1 tostart timer1
5. TIiscleared byCLRTIinstruction
6. Thecharacterbytetobetransferred seriallyiswrittenintoSBUFregister
7. TheTI flagbitismonitoredwiththeuse ofinstructionJNBTI,xxtoseeif thecharacter
hasbeentransferredcompletely.
8. Totransfer thenextbyte,gotostep5.

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Thestepsthat 8051goesthroughintransmittingacharacter viaTxD

1. Thebyte charactertobetransmittediswrittenintotheSBUFregister
2. Thestartbitistransferred
3. The8-bitcharacteristransferred onbitatatime
4. Thestopbitis transferred

 It isduringthetransfer of thestopbitthat8051raises
theTIflag,indicatingthatthelastcharacterwastransmitted
5. By monitoringtheTIflag, we makesurethatwe are notoverloading theSBUF
 If we write another byte into the SBUF before TI is raised, the un transmitted portion of
thepreviousbytewill belost
6. AfterSBUFisloadedwithanewbyte,theTIflagbitmustbeforcedto0byCLRTIinorderforthisnewbytetobetra
nsferred
 By checkingthe TIflag bit,we knowwhetherornotthe8051isreadytotransferanother byte
 It mustbe notedthatTIflagbitisraisedby8051itselfwhenitfinishesdatatransfer
 It mustbe clearedbytheprogrammerwithinstructionCLRTI
 IfwewriteabyteintoSBUFbeforetheTIflagbitisraised,weriskthelossofaportionofthebyte being
transferred
 TheTI bitcanbecheckedby
 TheinstructionJNBTI,xxUsinganinterrupt

Inprogramming the8051toreceivecharacterbytesserially
1. TMOD register is loaded with the value 20H, indicating the use of timer 1 in
modesetbaud rate
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2. TH1isloadedtosetbaudrate
3. TheSCONregister isloadedwiththevalue 50H,indicatingserialmode1,wherean8-bitdata
isframedwithstartand stop bits
4. TR1isset to1 tostart timer1
5. RIisclearedbyCLRRIinstruction
6. TheRIflagbitismonitoredwiththeuseofinstructionJNBRI,xxtosee ifanentire character
hasbeenreceived yet
7. WhenRIisraised, SBUFhasthe byte, itscontentsaremovedintoa safeplace.
8. Toreceive thenextcharacter,gotostep5.

InreceivingbitviaitsRxD pin,8051goesthrough thefollowingsteps.

1. It receivesthestartbit
 Indicatingthatthenextbitisthefirstbitof thecharacterbyteitisaboutto receive
2. The8-bitcharacterisreceivedonebit attime
3. Thestopbitis received
 Whenreceivingthe stopbit8051makesRI= 1,indicatingthatanentire character byte
hasbeenreceivedandmustbepickedupbefore itgetsoverwrittenbyanincoming character
raised, weknowthata characterhasbeenreceived andissittinginthe SBUFregister
 WecopytheSBUFcontentstoa safe placeinsome otherregister ormemory beforeitislost
5. AftertheSBUFcontentsare copiedintoa
safeplace,theRIflagbitmustbeforcedto0byCLRRIinordertoallowthenextreceived characterbyte to beplacedin
SBUF.
 Failuretodothiscauseslossofthereceivedcharacter.

Thereare twowaystoincrease thebaudrate ofdatatransfer

 Touseahigherfrequency crystal
 Tochange abitinthePCONregister
PCON
 PCONregisterisan8-bitregister
 When 8051 is powered up, SMOD is zero. We can set it to high by software and thereby double
thebaudrate.

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***********************************************************************************************
**

Explainthe interfacingofexternalRAM andROMwith8051.

Writeshortnotesonmemory
addressing(November2007,December2017)Explainhowtoaccessexternalme
morydevicesinan8051basedsystem.
Interfacingto externalmemory

For8751/89C51/DS5000-basedsystem,
EA(Externalaccess)
 weconnectedtheEApintoVcc toindicatethattheprogramcodeisstoredinthemicrocontroller‟s
on-chipROM
 Toindicatethatthe programcode isstoredinexternalROM,thispinmustbeconnectedtoGND.

SincethePC(programcounter)ofthe8031/51is16-bit,itiscapableofaccessingupto64Kbytesofprogramcode.
 In the8031/51,port0andport2providethe16-bitaddresstoaccessexternalmemory.
 P0providesthelower 8bitaddressA0– A7,andP2 providestheupper8bitaddress A8–A15
 P0isalso usedtoprovide the8-bitdatabusD0–D7.
 P0.0–P0.7areusedfor boththeaddressanddata pathsusingaddress/datamultiplexing.
ALE(addresslatchenable) pinisanoutputpin for8031/51
 ALE=0,P0isusedfor datapath.
 ALE =1,P0isusedforaddresspath74LS373 DLatch.
 To extract the address from the P0 pins we connect P0 to a 74LS373 and use the ALE pin
tolatchtheaddress

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PSEN(programstoreenable)signalisanoutputsignalforthe8031/51microcontrollerandmustbeconnectedto
theOEpin ofaROM containing theprogramcode
It is important to emphasize the role of EA and PSEN when connecting the 8031/51 to external
ROMWhentheEApinisconnectedtoGND,the8031/51fetchesopcode fromexternalROMbyusingPSEN
Theconnectionof thePSENpintotheOEpinofROM
Insystemsbasedonthe8751/89C51DS5000whereEAisconnectedtoVcc,thesechipsdonotactivatethePSENpin
Thisindicates thattheon-chipROMcontainsprogramcode.

ConnectiontoExternalProgramROM

WeuseRDtoconnectthe8031/51toexternalROMcontainingdata.FortheROMcontainingtheprogramcode, PSENis
used to fetchthecode.

The 8051 has 128K bytes of address

space64Kbytesaresetasideforprogramco
de
Programspaceisaccessedusing theprogramcounter(PC)tolocateand fetchinstructions
In some example we placed data in the code space and used the instruction MOVC
A,@A+DPTRtogetdata, whereC stands forcode
The other 64K bytes are set aside for data. The data memory space is accessed using the DPTR register and
aninstructioncalledMOVX,whereXstandsforexternal–Thedatamemoryspacemustbeimplementedexternally.

WeuseRDtoconnectthe8031/51toexternalROMcontainingdata.FortheROMcontainingtheprogramcode,PSENis
used to fetchthecode.

ConnectiontoExternalprogramROM

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ConnectiontoExternalData ROM

InterfacingexternalRAMwith8051

MOVXisawidely usedinstructionallowingaccesstoexternaldatamemory space

TobringexternallystoreddataintotheCPU,we usetheinstructionMOVXA,@DPTR

Toconnectthe8051toan externalSRAM,wemustusebothRD(P3.7)andWR(P3.6)

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In writingdatatoexternaldata RAM,weusetheinstructionMOVX@DPTR,A

***********************************************************************************************
****

TimingDiagram

InstructionTimings
 One“machinecycle”=6states(S1- S6)

 Onestate=2 clockcycles

 One“machinecycle” =12clockcycles

 Instructionstake1-4cycles
 e.g.1cycleinstructions:ADD,MOV,SETB,NOPinstr
ycle uctions:JMP,JZ
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 4cycleinstructions:MUL,DIV

Describe the timing diagram of external data memory read cycle of 8051.(Dec

2018)MOVX

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P0=Port0P2

=Port2

PCL=LowbyteofPC

PCH=HigherbyteofPC

 TimingdiagramoftheMOVXinstructionisshownabove.

 Eachmachinecycleconsistsof6statesnamelyS1,S2

…S6.Generallyarithmeticandlogicoperationstakeplaceduringphase1andinternalregi

ster-to-register transfer takes place during phase 2.ALE signal is

activatedduringS1P2andS2P1anditisactivatedonceagainduringS4P2andS5P1.

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************************************************************************************

SAMPLEPROGRAMS:
1. Addtwo8-bitnumbers

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MOVA,#30H ;(A) 30
ADD A, #50H ;(A)(A)+50H

2. Addtwo16-bitnumbers

MOVDPRT,#2040H ; (DPTR) 2040H(16bitnumber)

MOV A, #2BH ; (A) 2BH (lower byte of second 16 bit number)MOV
A, #20H ; (B) 20H (Higher byte of second 16 bit number)ADD A,
DPL ;Addlowerbytes

MOVDPL,A ;Saveresultoflowerbyteaddition
MOVA,B ;GethigherbyteofsecondnumberinA
ADD A, DPH
;Addhigherbyteswithanycarryfromlowerbyteaddition
MOVDPH,A ; Saveresultofhigherbyteaddition
3. Divisiontwo8-bitnumbers

MOVA,#90 ;GetthefirstnumberinA
MOVB,#20 ;GetthesecondnumberinB
DIVA, B ;A+B,Remainder inBandQuotientinA

4. Multiplytwo8-bitnumbers

MOVA,#8F ;GetthefirstnumberinA
MOVB,#79 ;Getthesecondnumber inB
MULA,B ;AxB,HigherbyteofresultinBandlowerbyteofresultinA

5. Toaddtwo16bitBCDnumbers

MOVDPTR,#1234H ;Loadfirst number

MOVR0,#20H
;LoadlowerbyteofsecondnumberMOV
R1,#30H
;LoadhigherbyteofsecondnumberMOV
A,R0
;GetthelowerbyteofsecondnumberAD
DA,DPL; addtwolowerbytes
DAA ;AdjustresulttovalidBCD
MOVDPL,A ;Storethesumoflower bytes
MOVA,R1 ;Getthehigherbyteofsecondnumber
ADDCA,DPH
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;Addtwohigherbytesconsideringcarryoflowerbyteaddition
DAA ;AdjustresulttovalidBCD

MOVDPH,A ;Storethesumofhigherbytes

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6. Tofindthesumof10numbersstoredinthearray

MOVDPTR,#2200H ; Initialize
memorypointerMOVX
A,@DPTR ;Getthecount

MOVR0,A ;Initializetheiterationcounter
INC DPTR ;Initializepointertoarrayofnumbers
MOVR1,#00 ;Result=0
BACK:MOVXA,@DPTR
;getthenumberAD
DA, R1 ;A Result +A
MOVR1,A ;Result A
INC DPTR ;Incrementthearraypointer
DJNZR0, BACK
;Decrementiterationcountifnotzerorepeat
MOVDPRT,#2300H ; Initializememorypointer

MOVA,R1 ;Gettheresult
MOVX@DPTR,A ;Storetheresult

*************************

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UNIT
IVPERIPHERALINTERFACI
NG

*******************************************************************************************
Studyonneed, Architecture,configurationandinterfacing, withICs:8255,8259, 8254,8237, 8251,8279, -

A/DandD/Aconverters&Interfacingwith8085&8051.

**************************************************************************************************
1. Introduction:

DataTransferTechniques

Datatransfermay
takeplacebetweentwodevices.Fore.g.
 Microprocessorandmemory
 MicroprocessorandI/Odevice
 Memory andI/Odevice

Classificationofdatatransfertechniques
1. Programmeddatatransfer
2. DirectMemory Access(DMA)
Programmeddatatransfer

 Dataistransferred fromtheI/Odevicetothemicroprocessorormemory.
 Dataistransferredunderthecontroloftheprogramstoredintheprogrammemoryofthemicroproc
essorbasedsystem.
 Thistechniqueofdatatransferisnormallyusedifthesizeofdatatobetransferredissmall.
Programmeddatatransfertechniquesisclassifiedas
 Paralleldatatransfer
 Serialdatatransfer
 Synchronous datatransfer
 Asynchronousdatatransfer
 InterruptInitiateddatatransfer
ComparisonofParallel/Serial

Parallel Serial

8 bitsofdata tranferredatatime Only 1 bit of data is transferred at a

9 linesrequiredtoconnecttwodevicesAd time2 lines required to connect two
vantageousover smalldistances devicesAdvantageousoverlongdistances

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ComparisonofAsynchronous/SynchronousDataTransfertechniques

Asynchronous Synchronous

Used to transfer one character at a Used to transfer a block

timeStartandstopbitsareusedwitheach ofcharactersat atime
character No start/ stop bits are
Speedisless usedSpeedishigh
Transmitterandreceivercanusetwoseparate Transmitter and receiver share
clockinputs acommonclock

 InterruptInitiatedDataTransfer
 Microprocessorinitiatestheinterruptmechanism andstartsexecutingthemainprogram.
 I/Odeviceinformsthemicroprocessorthatitisready bygeneratingan interruptsignal.
 Microprocessorservices theinterruptbycompletingthedatatransfer.

 DMAControlledData Transfer
 DMAstandsforDirectMemoryAccess
 usedwhenlarge amountofdataistobetransferred
 Microprocessordoes notparticipateinthistypeofdata transfer
 Dataistransferreddirectly between anI/Odeviceand memoryorvice-versa
 Datatransfer iscontrolledbyanI/Odevice oraDMAcontroller
 DMAdatatransferisfastas compared toprogrammeddatatransfer

************************************************************************************************************
Describe the internal block diagram of 8255 / PPI.(December 2010) (April 2018)(December
2017)Explainthefunctioningof8255programmableperipheralinterfaceanditsmodes.[April/May2017,
May/June 2016, April/May 2015, Nov/Dec2015,April/May 2011,May/June
2014,May/June2013,Nov/Dec2013,May/June 2009]
*********************************************************************************
. 2.Parallel communication interface (8255)(Programmable peripheral
interface)Definition:
The 8255 is a general purpose programmable I/Odevice used for parallel data transfer. It can
beprogrammed to transfer data under various conditions, from simple I/O to Interrupt I/O. It is
flexible,versatileandeconomical whenmultipleI/Oports are required.
FunctionalBlockDiagram
The8255consistsoffour sectionsnamely,
 Databusbuffer
 Read/writecontrollogic
 GroupAcontrol
 GroupBcontrol

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Figure.Blockdiagram of8255ProgrammablePeripheralinterface.

DATABUSBUFFER:
 Thisisatri-state,bi-
directionaldatabususedtointerfacetheinternaldatabusof8255Atothesystemdatabus of8085.
 UsingIN orOUTinstructions,CPUcanread orwrite thedatafrom/tothe databusbuffer.
 It can alsobeusedtotransfercontrolwordsand statusinformationbetween CPUand8255A.

READ/WRITECONTROLLOGIC:
 Thisblockcontrolsthechipdetection(CS),read(RD) andwrite(WR)operations.
 It consists of A0and A1 signals which are generally connected to the CPU address lines
A0andA1respectively.
 When CS (Chip select) signal goes low, different values of A0 and A1select one of
I/Oportsorcontrol register.

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GroupAandGroupBcontrol:
• GroupAandBgettheControlSignalfromCPUandsendthecommandtotheindividualcontrolblocks.
• GroupAsendthecontrolsignaltoportAandPortC(Upper)PC7-PC4.
• GroupBsendthecontrolsignal toportBandPortC(Lower)PC3-PC0.

PORTA:
• Thisisa 8-bitbuffered I/O latch.
• Itcanbeprogrammedby mode0,mode1,mode 2 .

PORTB:
• Thisisa8-bitbufferI/O latch.
• Itcanbeprogrammedbymode0and mode1.

PORTC:
• The eight bit ports of PORT C can be used as individual bits or be grouped into two 4 bit
ports.Cupper (Cu) and C Lower(CL).The functions of these ports are defined by writing a control
wordinthecontrol register.

FunctionsofPin:

Thesignaldescriptionof8255isbrieflypresentedasfollows

 It has24I/Oprogrammable pinswhich canbe groupedintothree

8bitparallelportsofPortA,PortBand Port C.
 ItisTTL compatible.
PA7-
PA0:TheseareeightportAlinesthatactsaseitherlatchedoutputorbufferedinputlinesdependinguponthecontrol
word loadedintothecontrolword register.
PC7-PC4:UppernibbleofportClines.Theymayactaseitheroutputlatchesorinputbufferslines.Thisportalsocan
beusedforgenerationofhandshakelines inmode1 ormode2.

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PC3-PC0:These are thelower portClines,otherdetailsarethesame asPC7-PC4lines.
PB0-PB7:ThesearetheeightportBlineswhichareusedaslatchedoutputlinesorbufferedinputlinesinthe samewayas
port A.
A1-A0:Thesearetheaddressinputlinesandaredrivenbythemicroprocessor.TheseaddresslinesA1-A0areusedfor
addressinganyone ofthefour registers,i.e.three portsandacontrolwordregister asgiven
intable below.

RD:Thisistheinputlinedrivenbythemicroprocessorandshouldbelowtoindicatereadoperationto8255.

WR:Thisisaninputline drivenby themicroprocessor. Alowon this line indicates writeoperation.

CS:Thisisachipselectline.Ifthislinegoeslow,itenablesthe8255torespondtoRDandWRsignals,
otherwiseRDandWRsignalareneglected•Incaseof8086systems,ifthe8255istobeinterfacedwithlower
orderdatabus,theA0and A1pins of8255 areconnectedwithA1and A2respectively.

D0-D7:These are thedata buslinesthose carry data orcontrolwordto/fromthemicroprocessor.

RESET:Alogichighonthislineclearsthecontrolwordregisterof8255.Allportsaresetasinputportsbydefault
afterreset.
OPERATING MODESOF8255
 BSRmode
 I/Omode

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CONTROLWORDFORMATS:

D7bitof controlworddecidesthetype ofmode.

 Ifitis„1‟.I/Omodeisselected.
 Ifitis„0‟.BSRmodeisselected

a) BSR(BITSET/RESET)mode:

 ThePORTCcanbeSetorResetbysendingOUTinstructiontotheCONTROLregisters.
 In BSRmodeindividualbitsofPortCcanbe usedfor applicationssuchason/off switch.
 The controlwordsetsorresetonebitatatime.

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b) FORI/OMODE

ThemodeformatforI/O asshowninfigure

TheI/O modeisdividedintothree modes mode0,mode1, andmode 2givenbelow

 Mode0– BasicI/O mode
 Mode1–strobbedI/O mode
 Mode2–Bidirectionaldatatransfer mode
Stepsto communicatewithperipheralsthroughthe8255.Theyare
1. Determine the addresses of Port A,B and C and of the control register according to the chip
selectlogic and address lineA0 and A1.
2. Writea controlwordinthecontrolregister
3. Write I/Oinstructions to communicatewith peripherals throughports A, B andC.control
worddoesnotalteranypreviouslytransmittedcontrolwordwithbitD7=1.ThustheI/OoperationsofPortAand
Port B arenot affectedby aBSR control word.

I/OMODES:

1) MODE0(Simpleinput/Output):
Inthismode,portA,portBareusedastwosimple 8bitI/OportsandportCastwo4bitportsused as
individually (Simply).

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 Featuresofmode0are:
 Anyportcanbe inputoroutput
 Outputsarelatched
 Inputsarenotlatched
2) MODE1:(Input/outputwithHandshake)

Inthismode,inputoroutputistransferredbyhandshakingSignals.Thehandshakingsignalsareexchangedbetween
themicroprocessor andperipheralpriorto datatransfer.

 Featuresofmode1

1. Twoports(AandB)functionas8bitI/Oports.Theycanbeconfiguredeitherasinputoroutputports.
2. Eachportuses3linesfromportCashandshakesignals.Theremaining2linesofPORTCcanbeusedforsimpl
eI/Ooperations.

Inputcontrolsignal(Mode1 ):
 STB(Strobeinput)–Ifthislinesfallstologiclowlevel,thedataavailableat8-bitinputportisloaded into
inputlatches.

 IBF (Input buffer full) If this signal rises to logic 1, it indicates that data has been loaded
intolatches, i.e. it works as an acknowledgement. IBF is set by a low on STB and is reset by the
risingedgeofRDinput.

 INTR (Interrupt request) This active high output signal can be used to interrupt the
CPU.wheneveraninputdevicerequeststheservice.INTRissetbyahighSTBpinandahigh atIBFpin.
 INTEisaninternalflagthatcanbecontrolledbythebitset/resetmodeofeitherPC 4(INTEA)orPC2(INT
EB)as shownin fig
 INTRisresetbyafallingedgeofRDinput.Thusanexternalinputdevicecanberequesttheservice
oftheprocessorby puttingthedataonthebusand sending thestrobesignal.

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Outputcontrol signal(Mode1) :

 OBF (Output buffer full) – This status signal, whenever falls to low, indicates that CPU
haswritten data to the specified output port. The OBF flip-flop will be set by a rising edge of
WRsignaland resetby alowgoingedgeat theACKinput.
 ACK (Acknowledge input) – ACK signal acts as an acknowledgement to be given by an
outputdevice. ACK signal, whenever low, informs the CPU that the data transferred by the CPU
to theoutputdevicethroughtheport isreceived by theoutput device.
 INTR (Interrupt request ) – Thus an output signal that can be used to interrupt the CPU
whenan output deviceacknowledgesthe data receivedfromthe CPU.INTRis setwhen ACK,
OBFand INTE are 1. It is reset by a falling edge on WR input. The INTEA and INTEB flags
arecontrolledby thebitset-resetmodeofPC6andPC2respectively.

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3) MODE2:bi-directionalI/Odatatransfer:

 FeaturesofMode2

 Inthismode,PortAcanbeconfiguredasthebidirectionalportandPortBiseitherinMode0 orMode1.
 PortAuses5signalsfromPortCashandshakesignalsfordatatransfer.Theremaining3signalsfromPor
t Ccanbeusedeither as simpleI/Oor ashandshakefor Port B.
.

*******************************************************************************

3. Serial Communication Interface

(8251)(ProgrammableCommunicationInte

rface)

Introduction:
Thebasicconceptsconcerning theserialI/Omodecanbeclassified intothefollowingcategories
1. InterfacingRequirements
2. Alphanumericcodes
3. Transmissionformat
4. Errorchecks indatacommunication
5. Datacommunicationovertelephone lines
 InterfacingRequirements

SerialI/OInterfacing
 The MPU selects the peripheral through chip select and uses the control signals .Read to receive
dataandwritetotransmit data.
 To communicate with alphabetic letters and decimal numbers of the computer into binary, we
useASCII code of 7 bit 00H to 7FH is assigned to a letter, a decimal number, a symbol or a
machinecommand.

[30– 39H 0to 9 ]

[41H–5AH AtoZ]
[21H– 2FH forvarioussymbols]
[00-1FH formachine commands]
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 Transmissionformat

 In synchronous format, receiver and a transmitter are synchronized with the same clock and
ablockofcharacteristransmittedalongwiththesynchronizationinformation.Thisformatisgenerallyused
forhighspeed transmission(morethan 20Kbits/second)

 The asynchronous format is character oriented. Each character carries the information of the
startand stop bits. Transmission starts with one start bit(low) followed by a character , and one or
twostop bits (high) .This is also known as framing.It is used in low speed transmission less
than20Kbits/second.

 CommunicationModes
Accordingtothedirectionandsimultaneityofdata flow,itisclassified as
Simplex-Data are transmittedinonlyonedirection.
Example:Transmissionfromamicrocomputer toa printer.
Duplex-Dataflow inbothdirection
 HalfDuplex-Ifthetransmissiongoesonewayatatimeitiscalledhalf duplex.
 FullDuplex–
Ifbothtransmittingandreceivingsignalsgoessimultaneously,itiscalledfullduplex.Example:Transmis
sion between computers.

 Rateoftransmission
The rate at which the bits are transmitted is called bits/second or Baud rate. For
example1200 baud= 1200 bits/second. Itindicates1200 bits are transmitted in a second.For1 bit
ittakes1/1200 =0.83ms.

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***************************************************************************************E
xplainUSART(8251)serialcommunicationinterfacewithitsfunctionalblockdiagram.(April2018)(June2016)
*************************************************************************************

ProgrammableCommunicationInterface8251(USART)/(Programmableserialinterface)

Definition:
The 8251 is a programmable USART (Universal Synchronous Asynchronous Receiver
Transmitter)is designed for Synchronous and Asynchronous serial communication; The 8251
receives paralleldata from the CPU and transmits serial data after conversion. This device also
receives serial datafromtheoutsideandtransmits paralleldatatotheCPUafter conversion.

Theblockdiagramof8251includesfivesections:
 Read/Writecontrollogic
 Transmittersection
 ReceiverSection
 Databusbuffer
 Modemcontrol

Figure:8251USARTSerialcommunicationInterface

 The control logic interfaces the chip with the MPU determines the functions of the
chipaccordingto thecontrol wordinits registerandmonitors thedataflow.

 Thetransmittersection convertsa parallelwordreceivedfromtheMPUintoa serialbitsand

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transmitsthemover TxDlinetoa peripheral.

 Thereceiversectionreceivesserialbitsfromaperipheralconvertsthemintoparallelwordandtransfersthe
wordto theMPU.

 TheMODEMcontrolisusedtoestablishdatacommunicationthroughmodemsovertelephonelines.

1. Transmittersection
 ThetransmitteracceptsparalleldatafromtheMPUand convertsthemintoserialdata.
 It hastworegisters, Abufferregistertoholdeightbitsand anoutputregistertoconverteightbitsinto
astreamofserialbits.
 TheMPUwritesabyteinthebufferregisterwhenevertheoutputregisterisempty,the
contents
ofthebufferregisterare transferredtotheoutputregister.
 ThissectiontransmitsdataontheTxDpinwiththeappropriateframingbits(start&stop).3outputand1 input
signalare associatedwith transmittersection.

TXD(TransmitData)
Thisisanoutputterminalfortransmittingdatafrom whichserial-converteddata issent out.

TXRDY(TransmitterReady)
Thisisanoutputterminal
duringhighindicatesthatthe8251isreadytoacceptatransmitteddatacha
racter. Itcan beusedeithertointerrupttheMPUorto indicatethestatus.

TXEMPTY(TransmitterEmpty)
Thissignalatlogic1indicatesthatthe8251hastransmittedallthecharactersandtheoutputregisterisempty.Itisre
set whenabyte istransferredfromthebuffer to theoutput register.

TXC(Transmitter clock)
Thisisaclockinputsignalwhichdeterminesthetransferspeedoftransmitteddata.In"synchronous
mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode",
itispossibletoselect thebaudratefactor by modeinstruction.Itcanbe1,16 or64 thebaud.

2. ReceiverSection

 The receiver accepts serial data on the RxD line from a peripheral and converts them into
paralleldata.
 Thesectionhastworegisters, thereceiverinputregisterand thebufferregister.
 When RxD line goes low, the control logic assumes it is a start bit, waits for half a bit time
andsamples the line again.If the line is still low, the i/p register accepts the following bits, forms
acharacter and loads it into the buffer registersubsequently. The parallel byte is transferred to
theMicroprocessor whenrequested.
RXD(ReceiveData)
Thebitsarereceivedseriallyonthislineandconvertedintoaparallelbyteinthereceiverinputregister.
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RXC(Receiverclock)
ThisclocksignalcontrolstherateatwhichbitsarereceivedbytheUSART.Inasynchronousmode,thecloc
k canbeset to 1,16 and64 times thebaud.

RXRDY(ReceiverReady)
ThisoutputsignalgoeshighwhenUSARThasacharacterinthebufferregisterandisreadytotransferit
totheMPU.This linecanbeusedeitherto indicatethestatusorto interrupttheMPU.

SYNDET/BD(Inputoroutputterminal)
This is a terminal whose function changes according to mode. In "internal synchronous mode."
thisterminalis athighlevel,ifsynccharacters are receivedandsynchronized.

In "asynchronous mode," this is an output terminal which generates "high level" output upon the
detectionof a "break" character if receiver data contains a "low-level" space between the stop bits of two
continuouscharacters.

3. MODEMControl

.
1. DSR(Datasetready)
Thisisaninputportfor
MODEMinterface.ThisisnormallyusedtocheckiftheDatasetisreadywhencommunicating with
amodem.
2. DTR(Data terminalready)
Thisisanoutputportfor MODEMinterface.It isusedtoindicatethatthedevice
isreadytoacceptdatawhenthe8251 is communicating with amodem.
3. CTS(Cleartosend)
This is an input terminal for MODEM interface which is used for controlling a transmit circuit.
Theterminal controls data transmission if the device is set in "Tx Enable" status by a command.
Data istransmittableiftheterminal is at lowlevel.
4. RTS(Request tosenddata)
This is an output port for MODEM interface. Itis used to indicate the MODEM that
thereceiverisreadyto receiveadatabytefromtheMODEM.

4. Read/WritecontrollogicandRegisters
Thissection includesR/Wcontrollogic,
 sixinputsignals,
 controllogicand
 3bufferregisters:Dataregister, controlregisterandstatusregister.
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ControlRegister
The 16 bit register for a control word consists of two independent bytes. The first byte is called the
modeinstructionand the second byte is called the command instruction. This register can be accessed as
anoutputport when theC/Dpinis high.

StatusRegister
Thisinputregister checksthereadystatusofaperipheral.Thisregister isaddressedasaninputportwhentheC
/Dishigh.Ithas thesameport address asthecontrol register.

DataBuffer
Thisbidirectionalregister canbeaddressedasaninputportandanoutputportwhenC/Dpinislow.

Theinputsignalstothecontrollogicare asfollows.
Therearetwotypes ofcontrolword.
1. Modeinstruction(settingof function)
2. Command(settingofoperation)
1)Mode Instruction
Modeinstructionisusedforsettingthefunctionofthe8251.Thewritingofacontrolwordafterresettingwillberecogniz
ed as a"modeinstruction."
8251Mode word
Items setbymodeinstruction areasfollows:
• Synchronous/asynchronousmode
• Stopbitlength(asynchronousmode)
• Characterlength
• Paritybit
• Baudrate factor(asynchronousmode)
• Internal/externalsynchronization(synchronousmode)
• Numberofsynchronous characters(Synchronous mode)

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8251commandword

8251statusword

PinDescription
 Initializingthe8251
• Toimplementserialcommunication,theMPUmustinform8251ofalldetailssuchasmode,baud,stopbits,par
ityetc.,
• Thereforepriortodatatransfer,asetofcontrolwordsmustbeloadedintothe16bitcontrolregister
ofthe 8251.TheMPmustcheckthereadinessofaperipheral byreadingthe statusregister.

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• Thecontrolwordsare dividedintotwoformats:Mode wordandcommandword.
• Themodewordspecifiesthegeneralcharacteristicsofoperation(suchasbaud,parity,numberofstop bits)
.Thecommand word enablesdata transmission and/orreception andthe status wordprovide
theinformation concerningregisterstatus andtransmission errors.

*******************************************************************************
Drawtheblockdiagramof8279Keyboard/DisplaycontrollerandexplainhowtointerfacetheHexKeyPad and7-
segmentLEDs using8279. (December2017)
******************************************************************************

4. ProgrammableKeyboard/Displaycontroller–8279

Definition:

A8279isageneralpurposekeyboarddisplaycontrollerthatsimultaneouslydrivesthedisplay of
asystemandinterferesakeyboardwith theCPU,leavingitfreeforroutinetask.

 Thekeyboardisinterfacedeitherininterruptmodeor polledmode.
 In theInterruptmode,the processorisrequestedserviceonlyifanykeyispressed,
otherwisetheCPUcan proceedwith itsmain task.
 In the Polledmode,theCPUperiodicallyreadsaninternalflag of8279tocheckforakeypressed.

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BasicDescriptionofthe8279

DATABUS(D7-D0)
Alldata andcommandsbetween themicroprocessor and8279are transmittedontheselines.
RD(read):
Microprocessorreadsthedata/statusfrom8279.
WR(write):
Microprocessorwritesthedatato8279
A0:
Ahighsignalonthislineindicatesthatthewordisacommandorstatus.Alowsignalindicatesthedata.
RESET:
Highsignalinthispinresetsthe8279.Afterbeingreset,the8279isplacedinthefollowingmodes
 16x8–bitcharacter display– leftentry
 Twokeylockout
CS(ChipSelect):
Alowsignalonthisinputpinenablesthecommunicationbetween8279andthemicroprocessor.
IRQ(InterruptRequest):
 TheinterruptlinegoeslowwitheachFIFO/sensorRAMreadsandreturnshighiftherestillinformat
ion in theRAM
SL0-SL3:
 Thescanlineswhichareusedtoscanthekeyswitchorsensormatrixandthedisplaysdigits.Theselin
es canbeeitherencoded(1 of16) ordecoded(1 of 4)

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RL0-RL7:
 Inputreturnlineswhichareconnectedtothescanlinesthroughthekeysorsensorswitches. They
have active internal pull-ups to keep them high serve as an 8- bit input in thestrobedinput
mode.
SHIFT:
 It hasanactiveinternalpull-uptokeepithighuntila switchclosure pullsitlow.
CNTL/STB:
 Forkeyboardmode,thislineisusedasacontrolinputandstoredlikestatusonakeyclosure.
 The lineisalsothestrobedlinetoenter thedataintotheFIFOinthe strobed input.
OUT A0– OUTA3, OUTB0– OUT B3:
 Thesetwoportsarethe outputsforthe 16x4displayrefreshregisters.Thesetwo
portsmayalsobeconsidered asone8 – bit port.
 Thetwo4–bitportsmaybe blankedindependently.
BD:
Thisoutputisusedto blankthedisplaydigitswitching or byadisplaybanking command.

************************************************************************************
ExplaintheworkingPrincipleof8279Keyboard/DisplayController.(April2010)(June2016)
(December2016)(May2015)(December2015)
*************************************************************************************

Keyboard/DisplayController(8279)
A8279isageneralpurposekeyboarddisplaycontrollerthatsimultaneouslydrivesthedisplayofasysteman
dinterferes a keyboardwiththeCPU,leavingit free forroutinetask.

Functionalblockdiagramof 8279
It consistsoffoursections
 Keyboardsection
 Scansection
 Displaysection
 CPUInterfacesection

CPUINTERFACESECTION:
 Thissectionhasbi-directionaldatabuffer(DB0–
DB7),I/Ocontrollines(RD,WR,CS,A0)andInterruptRequest lines (IRQ).
 TheA0signaldetermineswhethertransmit/receivecontrolwordordataisused.
 AnactivehighinlineIRQisgenerated tointerruptthemicroprocessorwhenever thedataisavailable.

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Figure:8279keyboard/DisplayInterface

 It consistsof
a) Asetof fourscanlinesandeightreturnlinesforinterfacingkeyboards
b) Asetofeightoutputlinesforinterfacingdisplay.

A0 RD WR Operation
0 0 0 MPUwritesthedatais8279
0 0 1 MPUreadsthedata from8279
1 1 0 MPUwritescontrolwordto8279
1 0 1 MPUreadstatuswordfrom8279

KEYBOARDSECTION:
 This section has keyboard debounce and control, 8X8 FIFO/sensor RAM, 8 return
lines(RL0– RL7)and CNTL/STBandshift lines.
 Inthekeyboarddebounceandcontrolunit,keysareautomaticallydebouncedandthekeyboardcan
beoperated in two modes.
 Twokeyslockout
 N–key rollover
 The8X8FIFO/sensorRAMconsistsof8registersthatareusedtostoreeightkeyboardentries.

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 Thereturn lines(RL0-RL7)are connectedtoeightcolumnsofkeyboard.
 ThestatusofshiftandCNTL/STBlinesare stored alongwiththekeyclosure.
SCANSECTION:
 Thissectionhas scancounterand fourscan lines(SL0 –SL3).
 These linesare decodedby4to16decoder togenerate16scanlines.
 Generally SL0–SL3 are connectedwiththerowsofa matrixkeyboard.

DISPLAYSECTION:
 ThissectionhastwogroupsofoutputslinesA0–A3andB0–
B3.Theselinesareusedtosenddatatodisplay drivers.
 BDlineisusedblankthedisplay.It also has16X8displaysRAM.
 ThedisplayaddressregisterholdstheaddressofthewordcurrentlybeingwrittenorreadbytheCPUtoorf
romthedisplay RAM.
 Thecontentsof theregistersareautomaticallyupdatedby8279toacceptthenextdataentrybyCPU.
Modesofoperationsof 8279

1. Input(Keyboard)modes
2. Output(Display)modes

1. Keyboardmodes
 ScannedkeyboardmodewithNkeyrollover
In this mode, each key depression is treated independently. When a key is pressed, the
debouncecircuit waits for 2 keyboards scans and then checks whether the key is still depressed. If it
is stilldepressed,thecodeis enteredin FIFO RAM
 Scannedkeyboardmode with2keylockout.
It prevents 2 keys from being recognized if pressed simultaneously. If two keys are pressed
withina debouncecycle (simultaneously),nokeyis recognizedtill oneofthem remains
closed, and the other is released. The last key that remains depressed is considered as single
validkeydepression.

2. Displaymodes

 Leftentrymode
The dataisentered fromtheleftsideof thedisplayunit.

 Rightentrymode
Thefirstentrytobe displayed isentered ontherightmostdisplay.

ProgrammingtheKeyboardInterface :
• Beforeanykeystrokeisdetected, the8279mustbeprogrammed
• Thefirst3bitsofthenumbersenttothecontrolport(11H)selectoneofthe8differentcontrolwords.

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Command Wordsof8279

KeyboardDisplaymodeset
Theformatofthecommandwordistoselectdifferentmodesofoperationof 8279

ControlWordDescription
a) 000DDMMM

Modeset:Opcode000.DDs
etsdisplaysmode.MMMset
skeyboardmode

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DDfieldselectseither:8-or16-digitdisplayWhethernewdataareenteredtotherightmostorleftmostdisplay
position.

b) Programmableclock(001PPPPP)
The clock for operation of 8279 is obtained by dividing the external clock input signal by
aprogrammable constant called prescaler.The clock command word programs the internal clock
driver.The code PPPPP, is a prescalar that divides the clock input pin (CLK) to achieve the
desiredoperatingfrequency,e.g.100 KHzrequires 010102

(c)ReadFIFO/SensorRAM(010AIXAAA )
The read FIFO control word selects the address (AAA) of a keystroke from the FIFO
buffer(000to 111).X-don‟t careandAIselectsauto-increm(entfortheaddress

d) ReadDisplayRAM(011AIAAAA)
Thiscommand enablesaprogrammer toreadthedisplayRAMdata.
Thedisplayreadcontrolwordselectsthe4bitaddressAAAApointstothe16bytedisplayRAMpositionsthat isto
beread.

e) WriteDisplayRAM(100AIAAAA)
The display write control word selects the 4 bit address AAAA points to the 16 byte
displayRAM positions that is to be written.. Display. Z selects auto-increment so subsequent writes go
tosubsequentdisplay positions.

f) Displaywithinhibitblanking(1010WWBB)
The display write inhibit control word inhibits writing to either the leftmost 4 bits of
thedisplay (left W) or rightmost 4 bits (right W).BB works similarly except that they blank (turn off)
halfoftheoutput pins.

g) ClearDisplayRAM(1100CCFA)
The clear control word clears the display, FIFO or both Bit F clears FIFO and the
displayRAMstatus, andsets address pointerto 000.
If CC are 00 or 01, all display RAM locations become
00000000.If CC is 10,-->00100000, ifCCis 11, -->11111111.

h) EndInterrupt/Errormodeset(1110E000)
EndofInterruptcontrolwordisissuedtoclear IRQ pintozeroinsensor matrixmode

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 Clockmustbeprogrammedfirst.If3.0MHzdrivesCLKinput,PPPPPisprogrammedto 30
or111102.
 Keyboardtypeisprogrammednext.Thepreviousexampleillustratesanencodedkeyboard,extern
aldecoderusedtodrivematrix.
 ProgramtheoperationoftheFIFO.Onceprogrammedneverreprogrammeddone,untilaprocedur
e isneededtoread priorkeyboardcodes.

**************************************************************************************
Drawandexplainthefunctionalblockdiagramof8254Timerandits command wordformat.[ May/June
2016,Nov/Dec2016,May/June 2013,May/June2009][Dec 2017]
Explaintheblocksdiagramandmodesofthe 8254timer.{Nov/Dec 2015.Dec2012,June2014]

*************************************************************************************

5. Programmable Interval Timer

(8254/8253)Definition:

The 8254 is a programmable interval timer/counter is used for the generation of accurate time delays
,controlling real-time events such as real-time clock, events counter, and motor speed and direction
controlunder softwarecontrol.
After the desired delay, the 8254 will interrupt the CPU. This makes microprocessor to be free
thetasks related to the counting process and can execute the programs in memory, while the timer device
mayperformthecountingtasks. Thisminimizes theSoftwareoverhead onthemicroprocessor.

Applicationof8254:
• Realtimeclock
• Event-counter
• Digitalone-shot
• Programmablerategenerator
• Squarewavegenerator
• Binaryratemultiplier
• Complexwaveformgenerator
• Complexmotorcontroller

It consistsof
 Threeindependent16-bitprogrammablecounters(timers)
 adata busbuffer
 Read/WritecontrolLogic
 Controlregister

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8254FunctionalBlock diagramof8253

DATABUSBUFFER:

This3-state,bi-directional,8-bitbuffer isusedtointerface the8254tothesystembus.

READ/WRITELOGIC:

 TheRead/Writelogicacceptsinputsfromthesystembusandgeneratescontrolsignalsforthe
otherfunctional blocks ofthe8254.
 A1andA0selectoneofthethreecontentscountersorthecontrolwordregistertobereadfrom/writte
ninto.
 A “low”ontheRDinput tellsthe8254 thattheCPUis readingoneofthecounters.
 A“low”onthe WRinputtellsthe8254thattheCPU
iswritingeitheracontrolwordoraninitialcount.
 BothRDandWRarequalifiedbyCS;RDandWRareignoredunlessthan8254hasbeenselectedby
holding CSlow.

CONTROLWORDREGISTER:

 Thecontrolword registerisselected bytheread/writelogicwhenA1,A0=11.

 IftheCPUthendoesawriteoperationtothe8254,thedataisstoredinthecontrolwordregisterandisi
nterpretedasa controlwordusedtodefinetheoperationofthe counters.

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 Thecontrolwordregistercanonlybewrittento;statusinformationisavailablewiththeRead-
Backcommand.

COUNTER0,COUNTER1,COUNTER2:

 Eachisa16bitdown counter
 Thecounters arefullyindependent. Each countermayoperateinadifferentmode.
 Each counter hasaseparateclockinput,countenable(gate) inputlinesand outputlines.
 Thecontrolwordregisterisnotapartof thecounter
itself,butitscontentsdeterminehowthecounteroperates.

8254PinDescription

D0to D7:read,write, Chipselect& AddresspinsA1andA0are connectedto Microprocessor

A1,A0 Theaddressinputsselectoneofthefourinternalregisters
forprogramming,reading,orwritingtoacounter.

CLK:Theclockinputisthetimingsourceforeachoftheinternalcounters.ItisoftenconnectedtothePCLKsignal
fromthebus controller
CS:ChipSelect enablesthe8254forprogramming,and readingandwriting

Gate: Thegateinputcontrols theoperationofthe counterinsomemodes

OUT:Acounter outputiswherethewave-form generatedbythetimerisavailable

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Read/Writecausesdata tobe read/writtenfromthe 8254andoften connectstothe

Each counter is individually programmed by writing a control word, followed by

theinitial count.Thecontrol word allows theprogrammerto select thecounter, model of
operation,binaryorBCDcount andtype ofoperation (read/write).

Commandwordof8254

Eachcountermaybeprogrammedwithacountof1toFFFFH.Minimumcountis1allmodesexcept2 and 3
with minimumcount of2.
Each counterhasaprogram controlwordusedtoselecttheway the counteroperates.

Iftwobytesareprogrammed,thenthefirstbyte(LSB)stopsthecount,andthe
secondbyte(MSB)startsthecounterwith thenewcount.

****************************************************************************************
Explainthevariousmodesofoperationof timerinterface 8253/8254.[Dec 2013,Dec 2015,Dec 2016]
**************************************************************************************
Thereare 6modesof operationforeachcounter
1. MODE0:INTERRUPTONTERMINALCOUNT:
2. MODE1:ProgrammableOne-Shot:
3. MODE2:RATEGENERATOR:
4. MODE3:SQUAREWAVEGENERATOR
5. MODE4:SOFTWARETRIGGEREDSTROBE:
6. MODE5:HARDWARETRIGGEREDSTROBE(RETRIGGERABLE):

Modesofoperation
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MODE0:INTERRUPTONTERMINALCOUNT:
 Mode0istypicallyusedforeventcounting.AftertheControlWordiswritten,OUTisinitiallylow,and will
remain lowuntil theCounterreacheszero.
 OUT thengoeshigh andremainshighuntilanew countor anewMode
0ControlWordiswrittenintotheCounter.
 GATE=1enablescounting;GATE =0disablescounting. GATE hasnoeffectonOUT.
 Theoutputbecomesalogic0whenthecontrolwordiswrittenandremainsthereuntilNplusthenumberofpr
ogrammedcounts.

MODE1:PROGRAMMABLEONE-SHOT:
 OUTwillbeinitiallyhigh.
 OUTwillgolowontheCLKpulsefollowingatriggertobegintheone-
shotpulse,andwillremainlowuntil theCounterreacheszero.
 OUTwillthengo highandremain highuntiltheCLKpulseafter thenexttrigger.
 TheGateinputtriggersthecountertooutputa0pulseforcountclocks.CounterreloadedifGate
ispulsed again.

MODE2:RATEGENERATOR:
 This Mode functions like a divide-by-N counter. It is typically used to generate a Real
TimeClockinterrupt.
 OUTwillinitiallybehigh.Whentheinitialcounthasdecrementedto1,OUTgoeslowforone CLK
pulse. OUT then goes high again, the Counter reloads the initial count and
theprocessisrepeated.
 Mode 2 is periodic, the same sequence is repeated indefinitely. For an initial count of N,
thesequencerepeatseveryNCLKcycles.
 GATE = 1 enables counting;GATE= 0 disables counting.IfGATE goes low during
anoutputpulse, OUTis set highimmediately.
 Counter generates a series of pulses 1 clock pulse wide. The separation between pulses
isdeterminedbythecount.Thecycleis repeateduntilreprogrammedorGpin setto 0.

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MODE3:SQUAREWAVEGENERATOR
 Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for
thedutycycleofOUT. OUTwillinitiallybehigh.
 When half the initial count has expired, OUT goes low for the remainder of the count. Mode
3isperiodic; thesequenceabove is repeatedindefinitely.
 An initial count of N results in a square wave with a period of N CLK cycles.GATE =
1enables counting; GATE = 0 disables counting. If GATE goes low.while OUT is low, OUT
issethighimmediately;no CLK pulseis required.
 Even counts: OUT is initially high. The initial count is loaded on one CLK pulse and then
isdecrementedby two on succeedingCLKpulses.
 When the count expires OUT changes value and the Counter is reloaded with the initial
count.The above process is repeated indefinitely.so for odd counts, OUT will be high for (N +
1)/2countsand lowfor(N-1)/2 counts

MODE4:SOFTWARETRIGGEREDSTROBE:
• OUTwillbeinitiallyhigh.Whentheinitialcountexpires,OUTwillgolowforoneCLKpulseandthengohigh
again.Thecountingsequenceis``triggered'„bywritingthe initialcount.(Gmustbe1).

MODE5:HARDWARETRIGGEREDSTROBE(RETRIGGERABLE):

OUT will initially be high.Counting is triggeredby a rising edge of GATE.When the initial counthas
expired, OUTwill golow forone CLKpulse and then gohigh again. G controls similartoMode1.
Triggerwithcountof 5

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*******************************************************************************
Explaintheworkingprincipleof8257DMAcontrollerinterface.(June2016)
WhatisDMA? Explain the DMA based data transfer sing DMA controller (April 2015)
*******************************************************************************
6. DirectMemoryAccess
Direct memory access (DMA) or DMA mode of data transfer is the fastest amongst all the modes
ofdatatransfer.Inthismode,thedevicemaytransferdatadirectlyto/frommemorywithoutanyinterferencefro
mtheCPU.
DMAController
TheDMAcontroller(8257)allowscertainhardwaresubsystemstoread/writedatato/frommemorywithoutmi
croprocessorintervention, allowingtheprocessorto dootherwork.
.

1 2 3 4 5 6 7 8 9
CLK

HOLD

HLDA

It is used in disk controllers, video/sound cards etc, or between memory locations. Typically,
theCPU initiates DMA transfer, does other operations while the transfer is in progress, and receives
aninterruptfrom theDMAcontroller oncetheoperation is complete.

It containsoffivemainblocks.

1. Databusbuffer
2. Read/Controllogic
3. Controllogicblock
4. Priorityresolver
5. DMAchannels.

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Figure:8237DMAcontroller

 Programmingthe8237
Thereare4stepsrequiredtoprogram theaddressandcountregisters first:
1. CleartheF/Lflip-flopwithaclearF/Lcommand
2. Disablethechannel
3. ProgramtheLSBandthenMSBoftheaddress
4. ProgramtheLSBandthenMSBof thecount
Additional programming is required to select the mode of operation before the channel
isenabledand started.

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Internalregisters
• Thecurrentaddressregister(CAR)isusedtoholdthe16-bitmemoryaddressusedfortheDMA
transfer.
• Thecurrentwordcountregister(CWCR)programsachannelforthenumberofbytes(upto64K)tran
sferredduring aDMAaction.
• Thebaseaddress(BA)andbasewordcount(BWC)registersareusedwhenauto-initialization
 isselectedforachannel.Inthismode,theircontentswillbereloadedtotheCARandCWCRafter
theDMAaction is completed.
• Each channelhasitsownCAR,CWCR,BA andBWC.
• Thecommandregister(CR)programstheoperationofthe 8237DMAcontroller
• Themoderegister (MR)programsthemodeofoperationforachannel.
• Therequestregister(RR)isusedtorequestaDMAtransferviasoftware,whichisveryusefulin
memory-to-memory transfers.
• Themaskregisterset/reset(MRSR)setsorclearsthechannelmasktodisableorenableparticular
DMAchannels.
• ThestatusregistershowsthestatusofeachDMAchannel.

Data busbuffer:
 Itisatri-state,bidirectional,8bitbufferwhichinterfacesthe8257tothesystemdataintheslavemode;itisused
totransferdatabetweenmicroprocessorandinternalregisters.
 In master mode,itisusedtosendhigherbyte address(A8-A15) onthedata bus.
Read/writelogic:
 Whenthemicroprocessorisprogrammingorreadingoneoftheinternalregistersoftheread/writelogic
accepts theI/Oread(IOR)orlowsignal.
 Decodesleastsignificantfouraddressbits(A0-
A7)andeitherwritesthecontentsofthedatabusaddressedregisterorplacesthecontentsoftheaddressedregis
teronto databus.
 DuringDMAcyclestheRead/writelogicgeneratestheI/OreadandmemorywriteorI/Owriteandmemoryre
adsignalsIORcontrolthedata transferbetweenperipheralandmemorydevice.

DMAchannels:
The8257providesfouridenticalchannelslabeledCH0,CH1,CH2andCH3.Eachchannelhastwo-
16bitregisters.They are
1. DMAaddressregister
2. Terminalcountregister
1. DMAaddressregister:
 It specifies theaddress ofthefirstmemorylocation tobe accessed.

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 ItisnecessarytoloadvalidmemoryaddressintheDMAaddressregisterbeforechannelisenabled.
2. Terminalcountregister:
 Thevalueloadedintotheloworder14bitsofTCRspecifiesthenumberofDMAcyclesminusone(N-
1)beforeTC output isactivated.
 Therefore,forNnumberofdesiredDMAcyclesitisnecessarytoloadthevalueN-
1intotheloworder14 bitsofTCR.
 MSB2bitsspecifythetypeofoperationtobe performed.
ControlLogic:
 ItcontrolsthesequenceofoperationsduringallDMAcyclesbygeneratingtheappropriatecontrolsignalsand
the16 bit addressthat specifiedthememorylocationto beaccessed.
 It consistsof modesetregister andstatusregister.
 ModesetregisterisprogrammedbytheCPUtoconfigure8257whereasthestatusregisterisreadbyCPUtoche
ckwhichchannelshavereachedaterminalcountconditionandstatusofupdate flag.

 Modesetregister:
 LSB4bitsare the enable4DMA channels.
 MSB4bitsaretheenableautoload,TCstop,extendedwrite,rotatingprioritymodesandterminalco
unt registers.
 ItisclearedbyRESETinput,thisdisablingalloptions,inhibitingallchannelsandpreventingbus
conflictson power-up.
Mastermode,
 It controlsthesequenceofDMAoperationduring allDMAcycles.
 Itgeneratesaddress andcontrolsignals.
 It increments16bitaddressand decrement14bitcounter registers.
 Itactivates aHRQsignalonDMAchannel Request.
Slavemode itisdisabled.

 STATUSREGISTER:

 Itindicateswhichchannelshavereachedaterminalcountconditionandincludestheupdateflag.

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 TheTcstatusbit=1,terminalcounthasbeenreached for thatchannel.
 Tc bitremainssetuntilthe statusregister isreadorthe8257isreset.
 Updateflag=1,8257isexecutingupdatecycle
 In update cycle8257ladparameters inchannel3tochannel2.

PRIORITYRESOLVER:
Itresolvestheperipheralsrequest.Itcanbeprogrammedtoworkintotwomodes,eitherfixedmodeorrotati
ng priority mode.

InitializingofDMAcontroller

 A DMA controller is capable of becoming the bus master and supervising a transfer between
anI/O or mass storage interface and memory. While making a transfer, it must be able to
placememoryaddressonthebusandsendandreceivehandshakingsignalsinamannersimilartothatof the
bus control logic. The purpose of a DMA controller is to perform a sequence of transfers (ieablock
transfer)by stealing bus cycles.

 A DMA controller is designed to service one or more I/O mass storage interfaces, and
eachinterface is connected to the controller by a set of conductors. A portion of a DMA controller
forservicingasingleinterfaceis calledachannel..

 ThegeneralorganizationofaonechannelDMAcontrolleranditsprincipalconnectionisshowninfigure.In
additiontotheusualcontrolandstatusregisters,eachchannelmustcontainanaddressregisterand abyte(or
word)count register.

 Initializingthe controller consists of filling these registers with the beginning (or ending) addressof
the memory arraythat is to be used as a buffer and the number of bytes (words) to betransferred
.For an input to memory, each time the interface has data to transfer it makes a DMArequest

 Thecontrollerthenmakesabusrequestandwhenitreceivesabusgrant,itputsthecontentsofthe
addressregisteron theaddressbus, sendsan acknowledgementbackto the interface,andissues I/O
read and memory write signals. The interface then puts the data on the data bus anddropsits
request.

 Whenthememoryacceptsthedataitreturnsareadysignaltothecontroller,whichthenincrements (or
decrements) the address register, decrements the byte (word) count, and drops itsbusrequest.

 Upon the countreaching zero, the processstops anda signal issentto the processorasaninterrupt
request or to the interface to notify it that the transfers have terminated. An output issimilarly
executed except that the controller issues I/O write and memory read signals and
thedataaretransferredintheotherdirection.

DRQ0-DRQ3(DMA Request):
Thesearetheasynchronousperipheralrequestinputsignal.Therequestsignalsisgeneratedbyexternalperipher
al device.

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DACK0-DACK3:
These are the active low DMA acknowledge output lines. Low level indicate that, peripheral
isselectedforgivingtheinformation(DMA cycle).Inmastermodeitisusedforchipselect
HLDA becomes active to indicate the processor has placed its buses at high-impedance stateas canbe
seen in the timing diagram,there are a few clock cycles between the time that HOLD changes
anduntilHLDAchanges
HLDA output is a signal to the requesting device that the processor has relinquished control of
itsmemory and I/O space. one could call HOLD input a DMA request input and HLDA output a
DMAgrantsignal

StepsinaDMAoperation
 ProcessorinitiatestheDMAcontrollergivesdevicenumber,memorybufferpointer,called
channelinitialization.
 Onceinitialized,itisreadyfordatatransfer.
 Whenready,I/OdeviceinformstheDMAcontroller.DMAcontrollerstartsthedatatransferprocess
 Obtainsbusbygoingthroughbusarbitration
 Placesmemoryaddressandappropriatecontrol signals
 Completestransferandreleasesthebus
 Updates memoryaddressandcount value
 Ifmoretoread,loopsbacktorepeat
theprocessNotifytheprocessor
whendonetypicallyusesaninterrupt

ModesofDMA operation

Eachchannelmaybeputinoneoffourmodes,withitscurrentmodebeingdeterminedbybits7and6ofthechannel
‟s moderegister.Thefourpossiblemodes are

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a)Byte b)Burst c)Block

 Singletransfer mode(01)
After each transfer the controller will release the bus to the processor for at least one bs
cycle,but will immediately begin testing for DREQ inputs and proceed to steal another cycle
assoonas aDREQlinebecomes active.
 Blocktransfermode(10)
DREQ needonly be active until DACKbecomesactive,after which the bus is not
releaseduntiltheentireblock ofdatahas beentransferred.
 DemandTransfermode(00)
This is similar to the block mode except that DREQ is tested after each transfer. If DREQ
isinactive , transfers are suspended until DREQ once againbecomes active ,at which time
theblocktransfercontinuesfromthepointatwhichitwassuspended.Thisallowstheinterfacetostop
thetransferintheeventthat itsdevice cannotkeepup.
 CascadeMode(11)
In this mode 8237s may be cascaded so that more than four channels can be included in
theDMA subsystem. In cascading the controllers ,those in the second level are connected to
thosein the first levelby joining HRQ to DREQ andHLDA to DACK ,To conservespace,
thismodewillnot beconsideredfurther.
Inthismode
Single-cyclemode:DMAdatatransferisdoneone byte atatime

Burst-mode:DMAtransferisfinishedwhen alldatahasbeenmoved.

***************************************************************************************
Draw the block diagram of 8259A and explain how to program8259A(April 2010).(Dec
2018)Explaintheworkingof8259withaneatblockdiagram.(Nov/Dec 2016/April 2015)
**********************************************************************************

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7. ProgrammableInterruptcontroller(8259)D

efinition:

 The Intel 8259 Programmable Interrupt Controller handles up to eight vectored priority interrupts
orthe CPU.It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It
ispackagedina28-pinDIP, usesNMOStechnologyandrequires asinglea5Vsupply.

 It accepts requests from the peripheral equipment, determines which of the incoming requests is
ofthe highest importance (priority), ascertains whether the incoming request has a higher priority
valuethanthelevelcurrentlybeingserviced,andissuesaninterrupttotheCPUbasedonthisdetermination.

 Interrupt Request Register (RR): IRR stores all the interrupt request in it in order to serve
themoneby oneon thepriority basis.

 In-Service Register (ISR): This stores all the interrupt requests those are being served, i.e.
ISRkeepsatrackoftherequests being served.

 PriorityResolver:Thisunitdeterminestheprioritiesoftheinterruptrequestsappearingsimultaneously.
The highest priority is selected and stored into the corresponding bit of ISRduring INTA pulse.
The IR0 has the highest priority while the IR7 has the lowest one, normally infixed priority mode.
The priorities however may be altered by programming the 8259A in rotatingprioritymode.

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 Interrupt Mask Register (IMR) : This register stores the bits required to mask the
interruptinputs.IMR operates onIRRat thedirectionofthePriorityResolver.

InterruptControlLogic:Thisblockmanages theinterrupt andinterruptacknowledgesignalsto

be sent to the CPU for serving one of the eight interrupt requests. This also accepts the
interruptacknowledge (INTA) signal from CPU that causes the 8259A to release vector address on
to thedatabus.

 DataBusBuffer:Thistristatebidirectionalbufferinterfacesinternal8259Abustothemicroprocessor
system data bus. Control words, status and vector information pass through databuffer during read
orwriteoperations.

 Read/Write Control Logic: This circuit accepts and decodes commands from the CPU.
Thisblockalso allows thestatusofthe8259Ato betransferredon to thedatabus.

 Cascade Buffer/Comparator: This block stores and compares the ID‟s all the 8259A used
insystem. The three I/O pins CASO-2 are outputs when the 8259A is used as a master. The
samepins act as inputs whenthe 8259A is in slave mode. The 8259A in master mode sends the ID
ofthe interrupting slave device on these lines. The slave thus selected, will send its
preprogrammedvector addresson thedatabus duringthenextINTApulse.

 CS: This is an active-low chip select signal for enabling RD and WR operations of 8259A.
INTAfunctionis independent ofCS.

 WR: This pin is an active-low write enable input to 8259A. This enables it to accept
commandwordsfromCPU.

 RD: This is an active-lowreadenable input to 8259A. A low on this line enables8259A

toreleasestatus onto thedatabusofCPU.

 D0-D7 : These pins from a bidirectional data bus that carries 8-bit data either to control word
orfromstatus wordregisters.Thisalso carriesinterrupt vectorinformation.

 CAS0 – CAS2 Cascade Lines: A signal 8259A provides eight vectored interrupts.
Ifmoreinterrupts are required, the 8259A is used in cascade mode. In cascade mode, a master
8259Aalong with eight slaves 8259A can provide up to 64 vectored interrupt lines. These three
lines actasselectlines foraddressing theslave8259A.

 PS/EN: This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used
asbuffered enable to control buffer transreceivers. If this is not used in buffered mode then the pin
isusedasinput todesignatewhetherthechipisusedas a master(SP=1)orslave(SP=0).

 INT:Thispingoeshighwheneveravalidinterruptrequestisasserted.ThisisusedtointerrupttheCPUand
isconnectedto theinterrupt input ofCPU.

 IR0–
IR7(Interruptrequests):ThesepinsactasinputstoacceptinterruptrequesttotheCPU.Inedgetriggered
mode,aninterruptserviceisrequestedbyraisinganIRpinfromalowtoahigh

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stateandholdingithighuntilitisacknowledged,andjustbylatchingittohighlevel,ifusedinleveltriggeredm
ode.

 A0 : This input signal is used in conjunction with WR and RD signals to write commands into
thevariouscommandregisters,aswellasreadingthevariousstatusregistersofthechip.Thislinecanbetied
directly to oneoftheaddresslines.

CommandWordsof8259A

The8259Aaccepts twotypesofcommandwords generatedbytheCPU:

1. InitializationCommandWords(ICWs):
Beforenormal operation canbegin, each 8259A in the system must bebroughtto astarting
pointedbyasequenceof2 to 4 bytestimedby WR pulses.

2. OperationalCommandWords(OCWs):
Theseare thecommandwordswhichcommandthe8259A tooperate invariousinterruptmodes.These
modes are:
a. Fullynestedmode
b. Rotatingprioritymode
c. Specialmaskmode
d. Polledmode
TheOCWscan be writtenintothe8259Aanytime afterinitialization.

 InterruptSequenceof8259ProgrammableInterruptController

InterruptSequencewithan8085system

1. OneormoreIRlinesareraised highthatset correspondingIRRbits.

2. 8259Aresolvespriorityandsendsan INTsignaltoCPU.

3. TheCPUacknowledgewithINTApulse.

4. UponreceivinganINTAsignalfromtheCPU,thehighestpriorityISRbitissetandthecorresponding IRR bit

is reset.The 8259 will also release a CALL instruction code (11001101) on tothe8 bitdatathrough its D7
-D0 pins.

5. The CALL instruction will initiate a second INTA pulse. During this period 8259A releases an 8-
bitpointeron toadata bus fromtwo moreINTApulsesto be senttothe8259fromtheCPUgroup.

6. These two INTA pulses allow the 8259 to release its programmed subroutine address onto the data
bits.The lower 8 bit address is released at the first INTA pulse and the higher8 bit address is released at
thesecondINTApulse.

7. This completes the 3 byte CALLinstruction releasedby the 8259. Interrupt cycle.The ISR bit isreset
at the end of the second INTA pulse if automatic end of interrupt (AEOI) mode is
programmed.Otherwise ISR bit remains set until an appropriate EOI command is issued at the end of
interruptsubroutine.

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 PriorityModes

1. FullyNestedMode

 IR0isthehighestandIR7isthe lowestone
 InadditionanyIRcanbeassignedthehighestpriority;theprioritysequencewillbeginatthat IR.

Example:

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

4 5 6 7 0 1 2 3

2. AutomaticRotation(equalPriority):
Inthismode,adevicewhichoneisbeingservicedwillbeconsideredasalowestpriorityinthenexttime
First IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
Time
6 7 0 1 2 3 4 5

Second IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

Time
1 0 7 6 5 4 3 2

3. Specificrotationmode(SpecificPriority)
Theprogrammercanchangetheprioritiesby programmingthebottompriority andthsfixing
allotherpriorities.ieif IR4isprogrammedasthelowestpriority,thenIR% willhavethe highestone.

EndofInterrupt (EOI)
 Afterthecompletionofaninterruptservice,thecorrespondingISRbitneedstobereset.
 ThisiscalledtheEndofInterrupt(EOI).
 Itcanbeissuedin3formats.Theyare,

(i) Non-specificEOIcommandWhenthe8259receivesthiscommand,itresetsthe
highestpriorityISRbit.
(ii) SpecificEOIcommandIt specifieswhichISRbittobereset.
(iii) AutomaticEOIcommand Whenthe

8259receivesthethirdsignal,theISRbitisreset

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CommandandStatusWordsof8259

 CommandWordforOperationalCommandWords(OCWs)

****************************************************************************************
ExplainA/Dinterfacewith 8085 withneatsketch.(Dec2014)
ExplainhowD/AandA/Dinterfacingdonewith8085withanapplication(April2015)(Dec 2017)
***************************************************************************************
8.Analogtodigital conversion
 Theprocessofanalogtodigitalconversionisaslowprocess,andthemicroprocessorhastowaitfor
thedigitaldatatilltheconversion is over.

 Aftertheconversionisover,theADCsendsendofconversionEOCsignaltoinformthemicroprocessor that
the conversion is over and the result is ready at the output buffer of the ADC.These tasks of issuing
an SOC pulse to ADC, reading EOC signal from the ADC and reading thedigitaloutputoftheADC
arecarriedoutby the CPUusing 8255I/Oports.

 The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal
iscalledas theconversion delayoftheADC.

 It may range anywhere from a few microseconds in case of fast ADC to even a few
hundredmillisecondsincaseofslowADCs.

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 The available ADC in the market use different conversion techniques for conversion of
analogsignal to digitals. Successive approximation techniques and dual slope integration
techniques arethe mostpopulartechniques used intheintegratedADC chip.

GeneralalgorithmforADC interfacingcontainsthefollowingsteps:
1. Ensurethe stabilityofanaloginput,appliedtotheADC.
2. Issuestartof conversion(SOC)pulsetoADC
3. Readendofconversionsignaltomark theendof conversionprocesses.
4. Read digital data output of the ADC as equivalent digital output.

Figure:ADC0808interfacingwith8085using8255

 Analog input voltage must be constant at the input of the ADC right from the start of
conversiontilltheend oftheconversiontogetcorrect results.
 This may be ensured by a sample and hold circuit which samples the analog signaland holds
itconstantforaspecifictimeduration.
 The microprocessor may issue a hold signal to the sample and hold circuit. If the applied
inputchanges before the complete conversion process is over, the digital equivalent of the analog
inputcalculatedby theADC may not becorrect.

ADC0808/0809 :
• Theanalogtodigitalconverterchips0808and0809are8-
bitCMOS,successiveapproximationconverters.

• This technique is one of the fast techniques for analog to digital conversion. The
conversiondelay is 100μs at a clock frequency of 640 KHz, which is quite low as compared to
otherconverters.

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• These converters do not need any external zero or full scale adjustments as they are
alreadytaken care of by internal circuits. These converters internally have a 3:8 analog
multiplexer sothat at a time eight different analog conversion by using address lines ADD A,
ADD B, ADDC.

• Using these address inputs, multichannel data acquisition system can be designed using
asingle ADC.

• The CPU may drive these lines using output port lines in case of multichannel applications.
Incase ofsingleinputapplications, thesemay be hardwiredto selecttheproper input.

• There are unipolar analog to digital converters, i.e. they are able to convert only
positiveanaloginput voltageto theirdigitalequivalent.

• Thesechipsdonotcontainanyinternalsampleandholdcircuit.Ifoneneedsasampleandhold circuit
for the conversion of fast signal into equivalent digital quantities, it has to
beexternallyconnectedat each oftheanalog inputs.

• Vcc Supplypins+5V
• GND GND
• Vref + Referencevoltage positive+5 Voltsmaximum.
• Vref_ Reference voltage negative 0Volts
minimumI/P0–I/P7 Analoginputs
• ADDA,B,CAddresslinesforselecting analoginputs.
• O7– O0 Digital 8-bitoutputwithO7MSBandO0LSB
• SOC Startofconversionsignalpin
• EOC Endof conversionsignalpin
• OE Outputlatchenablepin,ifhighenables output
• CLK ClockinputforADC

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Example: Interfacing ADC 0808 with 8085using 8255 ports. Use port A of 8255 for
transferringdigital data output of ADC to the CPU and port C for control signals.Assume that an
analog input ispresentatI/P2 of theADCandaclockinput ofsuitablefrequencyisavailableforADC.

• Solution:TheanaloginputI/P2isusedandthereforeaddresspinsA,B,Cshouldbe0,1,0respectively to
select I/P2. The OE and ALE pins are already kept at +5V to select the ADC andenable the outputs.
Port C upper acts as the input port to receive the EOC signal while port C loweractsastheoutputport to
send SOC to theADC.
Port A acts as a 8-bit input data port to receive the digital data output from
theADC.The8255 controlword is written asfollows:
D7D6D5D4D3D2D1D01 0
0 1 1 0 00

TherequiredALPisasfollows:
MOV A, 98h; initialise 8255
asOUTCWR, ;discussed
above.MOVA,02h;SelectI/P2asanalo
gOUTPortB , input.
MOV AL,00h;
GivestartofconversionOUTPortC
;pulsetotheADC
MOVAL, 01h
OUT Port
CMOVAL,00h
OUTPortC
WAIT: INPortC ;Checkfor EOCby
RCR ; reading port C upper
andJNCWAIT ;rotating through carry.
INPortA ; If EOC, read digital equivalent ;in
ALHLT ;Stop

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Figure:InterfacingADCto8051
ThecircuitinitiatestheADCtoconvertagivenanalogueinput,thenacceptsthecorrespondingdigitaldataand
displaysit on theLEDarrayconnectedatP0
ORG00H
MOVP1,#11111111B//initiatesP1as theinputport
MAIN: CLR P3.7 // makes
CS=0SETBP3.6//makesRD
highCLRP3.5//makesWRlow
SETBP3.5//lowto highpulsetoWRforstartingconversion
WAIT:JBP3.4,WAIT//pollsuntilINTR=0
CLRP3.7 //ensuresCS=0
CLRP3.6//hightolowpulsetoRDforreadingthedatafromADC
MOVA,P1//movesthedigital datatoaccumulator
CPLA//complementsthedigitaldata
MOV P0,A // outputs the data to P0 for the
LEDsSJMPMAIN//jumpsbacktotheMAINprogra
mEND
***************************************************************************Explai
ntheinterfacingofD/Aconverter
with8085and8051.andWriteaprogramforgenera
tingany typical waveform.(June2016)(Dec2018)
***************************************************************************

9. InterfacingDigitalToAnalogConverters

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• The digital to analog converters convert binary number into their equivalent voltages.
TheDACfindapplicationsinareaslikedigitallycontrolledgains,motorsspeedcontrols,programmab
le gain amplifiers etc.

• AD 7523 8-bit Multiplying DAC :This is a16 pin DIP,multiplying digitalto analogconverter,
containing R-2R ladder for D-A conversion along with single pole double
thrownNMOSswitches to connectthedigitalinputsto theladder.

• The pin diagram of AD7523 is shown in fig the supply range is from +5V to +15V, while
Vrefmaybe anywherebetween-
10Vto+10V.Themaximumanalogoutputvoltagewillbeanywherebetween-
10Vto+10V,whenallthedigitalinputsareatlogichighstate.

• Usually a zener is connected between OUT1 and OUT2 to save the DAC from
negativetransients. An operational amplifier is used as a current to voltage converter at the
output ofADto convert thecurrentoutput ofADtoaproportionaloutputvoltage.

Figure:DACconnectedwith8085via8255

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Figure:DACconnectedwith8051

ItalsooffersadditionaldrivecapabilitytotheDACoutput.Anexternalfeedbackresistoracts to
control the gain. One may not connect any external feedback resistor, if no gain control isrequired.
EXAMPLE: Interfacing DAC AD7523 with an 8085 CPU running at 8MHZ and write an
assemblylanguage programtogenerateasawtooth waveformofperiod 1mswith V max5V.
Solution:FigshowstheinterfacingcircuitofAD74523with8086using8255programgivesanALPto
generateasawtoothwaveformusingcircuit.
MOV A, 80h ;make all ports
outputOUTC0, AL
AGAIN: MOV AL, 00H ;start voltage for
rampBACK:OUTPA
INR
ACPI
0FFhJBB
ACK
JMPAGAIN
In theabove program, portAisinitializedastheoutputportforsendingthe digitaldata asinputto
DAC.

• Therampstartsfromthe0V(analog),henceALstartswith00H.Toincrementtheramp,thecontentofA
Lisincreasedduringeach execution ofloop tillitreaches F2H.
• Afterthatthesawtoothwaveagainstartsfrom00H,i.e.0V(analog)andtheprocedureisrepeated.Thera
mpperiodgiven bythis program isprecisely 1.000625ms.
• HerethecountF2Hhasbeencalculatedbydividingtherequireddelayof1msbythetimerequiredforthe
executionoftheloop once.
• Therampslopecanbecontrolledbycallinga controllabledelayaftertheOUT instruction.
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INTERFACING8279WITH8085

Interfacing8254with8085

INTERFACING8255WITH8085
8085Microprocessorinterfacedtothe8255.

 PortAhasbeenusedastheinputportforthesecuritystatus,whereas,portBhasbeenus
edasthe outputportforthe command.
 Theportnumbersassignedare04(portA),05(portB),06(portC)and07(Control
Word)asevidentfromthecircuit.

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ExplaintheLEDinterfacingwith8086microprocessor(April2018)
******************************************************************************
InterfacingLEDwith 8086
LED(LIGHT EMITTINGDIODES)

Light Emitting Diodes (LED) is the most commonly used components, usually for displaying
pinsdigital states. Typical uses of LEDs include alarm devices, timers and confirmation of user input
suchasamouseclick orkeystroke.

INTERFACINGLED

Fig. 1 shows how to interface the LED to microprocessor. As you can see the Anode is
connectedthrougharesistortoGND&theCathodeisconnectedtotheMicroprocessorpin.SowhenthePortPin
is HIGH theLEDis OFF&whenthePort PinisLOWthe LEDis turnedON.

INTERFACINGLEDWITH8086WenowwanttoflashaLEDin8086TrainerBoard.Itworksby turning
ON a LED & then turning it OFF & then looping back to START. However the
operatingspeedofmicroprocessoris veryhigh

PINASSIGNMENTWITH8086

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CIRCUITDIAGRAMTOINTERFACELEDWITH8255

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ASSEMBLYPROGRAMTOONANDOFFLEDUSING8086

Title:Program to BlinkLEDs

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UNIT–V
MICROCONTROLLERPROGRAMMING&APPLICATIONS

*********************************************************************************************** S
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**********************************************************************************

****************************************************************************************
ExplaintheinterfacingofKeyboardwith 8051.[June2016.December2016.April2018]
************************************************************************************************

2
. K
E
YBO
AR
DAN
DDS
IP
L
AYIN
T
ER
F
AC
E

Keyboardsare organizedinamatrixofrows andcolumns

 TheCPUaccessesbothrowsandcolumnsthroughports.Therefore,withtwo8-
bitports,an8x8matrixofkeyscanbeconnected toamicroprocessor.
 Whenakeyispressed,arowandacolumnmakeacontact,Otherwise,thereisnoconnectionbetweenrowsand
columns
 InIBMPCkeyboards,asinglemicrocontrollertakescareofhardwareandsoftwareinterfacing.

A4x4matrixconnectedtotwoports.Therowsareconnectedtoanoutputportandthecolumnsareconnectedto an input
port.

 It is the function of the microcontroller to scan the keyboard continuously to detect and identify
thekeypressed

 Todetectapressedkey,themicrocontrollergroundsallrowsbyproviding0totheoutputlatch,thenit reads the

columns. If the data read from columns is D3 – D0 = 1111, no key has been pressed andtheprocess
continues tillkeypress is detected.

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 If one of the column bits has a zero, this means that a key press has occurred, For example, if D3 – D0
=1101,thismeansthatakeyintheD1columnhasbeenpressed.Afterdetectingakeypress,microcontroller
willgothroughtheprocess of identifying thekey.
 Startingwiththetoprow,themicrocontrollergroundsitbyprovidinga lowtorow D0only.
 Itreadsthecolumns,ifthedatareadisall1s,nokeyinthatrowisactivatedandtheprocessismovedtothenextrow.
 It groundsthenextrow,reads thecolumns,andchecksforanyzero
 Thisprocesscontinuesuntiltherow isidentified
 Afteridentificationofthe rowinwhichthekey hasbeen pressed
 Findoutwhichcolumnthepressed keybelongs to.

Programfordetectionandidentificationofkeyactivationgoesthroughthe followingstages:

1. To make sure that the preceding key has been released, 0s are output to all rows at once, and
thecolumnsarereadandcheckedrepeatedly untilall thecolumnsarehigh.
 When all columns are found to be high, the program waits for a short amount of time before
itgoes to the next stage of waiting for a key to be pressed. To see if any key is pressed,
thecolumnsarescannedoverandoverin aninfiniteloopuntil oneofthemhas a0on it.
 Remember that the output latches connected to rows still have their initial zerosmaking
themgrounded.

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2. Afterthekeypressdetection,itwaits20msfor the bounceandthenscansthecolumnsagain.
 It ensuresthatthefirstkeypressdetectionwasnotanerroneousone duetoaspike noise.
 If after the 20-ms delay the key is still pressed, it goes back into the loop to detect a real
keypress
3. Todetectwhichrow keypressbelongsto,itgroundsonerow atatime,readingthecolumnseachtime
 Ifitfindsthatallcolumnsarehigh,this meansthatthekeypresscannotbelongtothatrow.Therefore, it
grounds the next row and continues until it finds the row the key press belongsto.
 Upon finding the row that the key press belongs to, it sets up the starting address for the look-
uptableholding thescancodes(orASCII)forthatrow.

4. Toidentifythekeypress,itrotatesthecolumnbits,onebitatatime,intothecarryflagandcheckstoseeif itis low

 Uponfindingthezero,itpullsouttheASCII code for thatkeyfromthelook-uptable
 otherwise,itincrementsthepointertopointtothenextelementof thelook-up table

KEYBOARDINTERFACINGWITH8051:

Thestepsinalgorithmare asfollows:
1. InitializeP1.0,P1.1,P1.2andP1.3asinputs.
2. Checkifallthekeysarereleasedbywriting„0‟toP1.4-P1.7andcheckifallreturnlinesareinstate“1”.Ifnotthenwait.
3. Calldebounce.

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4. Waitforkeyclosure.Groundallscanlinesbywriting„0‟andthencheckifatleastoneofreturnlinesshows
„0‟level.

5. Calldebounce.

6. Iskeyreallypressed?(Checkatleastoneofthe returnlinesshows„0‟level).NoStep4,Yesstep7.
7. Findkeycodeanddisplaythekeypressedon7-segmentdisplay.

8. Gotostep1.

PROGRAM:
Fromtheabovefigureidentifytherowandcolumnofthepressedkeyforeachofthefollowing.
(a) D3– D0 =1110fortherow, D3–D0 =1011forthecolumn
(b) D3– D0 =1101fortherow, D3– D0 =0111forthecolumnSolution:

Fromtheabovefigure,therowandcolumncanbeusedtoidentifythekey.

(a) TherowbelongstoD0andthecolumnbelongstoD2;therefore, keynumber2waspressed.

(b) TherowbelongstoD1andthecolumnbelongstoD3;therefore,keynumber 7waspressed.
;Keyboardsubroutine.
;ThisprogramsendstheASCII codeforpressedkeytoP0.1.
;P1.0–P1.3connectedtorowsP2.0–P2.3connectedtocolumns.

LOOK-
UPTABLEFOREACHASCIIROWOR
G 300H
KCODE0:DE‘0’,‘1’,‘2’,‘3’ ;Row 0
KCODE1:DE‘4’,‘5’,‘6’,‘7’ ;Row 1
KCODE2:DE‘8’,‘9’,‘A’, ‘B’ ;Row 2
KCODE3:DE‘C’,‘D’,‘E’,‘F’ ; Row3

MOVP2,#0FFH ;makeP2aninputport
K1: MOVP1,#0MCV ;groundallrowsatonce
A,P2 ;readallcolumnensureallkeysopen.
ANLA,#00001111BCJNE ;maskedunusedbits
A,#00001111B,K1 ;checktillallkeysreleased
K2: ACALLDELAY ;call20msdelay
MCVA,P2 ;seeifanykeyispressed
ANLA,#00001111B ;maskunusedbits
CJNEA,#00001111B,OVER
;keypressed,awaitclosureSJ
MPK2 ;checkifkeypressed
OVER: ACALLDELAY ;wait20msdebouncetime
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MCVA,P2 ;checkkeyclosure
ANLA,#00001111B ;
CJNEA,#00001111B, OVER1 ;
SJMPK2 ;
OVER1:MOV P1,#11111110B ;
MOV A,P2 ;
ANLA,#00001111B ;

CJNEA,#00001111B,ROW_0
MOVP1,#11111101B
MOVA,P2
ANLA, #00001111B
CJNEA,#00001111B,ROW_1
MOVP1,#11111011B
MOVA,P2
ANLA, #00001111B
CJNEA,#00001111B,ROW_2
MOVP1,#11110111B
MOVA,P2
ANLA, #00001111B
CJNEA,#00001111B,ROW_3
LJMPF2
MOVDPTR, #KCODE0
SJMPFIND
MOV
DPTR,SJMP
FINDMOV
DPTR,SJMP
FINDMOV
DPTR,RRC
A
JNC
MATCHINC
DPTR
MATCH:SJMPFIND
CLRA
MOVCA,@A+
MOV
P0,ALJMPK1

Thestepsinalgorithmareasfollows:
1. InitializeP1.0,P1.1,P1.2andP1.3asinputs.

2. Checkifallthe keysarereleasedbywriting„0‟toP1.4-
P1.7andcheckifallreturnlinesareinstate„1‟.Ifnotthenwait.
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3. Calldebounce.

4. Waitfor
keyclosure.Groundallscanlinesbywriting„0‟andthencheckifatleastoneofreturnlinesshows„0‟level
.
5. Calldebounce.

***************************************************************************************
Explaintheinterfacingofsteppermotorwith8051. [June2016/April2018][DEC2018]

***************************************************************************************

3. Interfacingsteppermotorwith8051

STEPPERMOTOR

A stepper motor is a brushless, synchronous electric motor that converts digital pulses into
mechanicalshaft rotation. Every revolution of the stepper motor is divided into a discrete number of steps, and the
motormustbesent aseparatepulseforeach step.

Stepper motors can be used in various areas of your microcontroller projects such as making
robots,roboticarm, andautomaticdoorlock system.

Fig. shows how to interface the Stepper Motor to microcontroller. As you can see the stepper motor
isconnected with Microcontroller output port pins through a ULN2803A array. So when the microcontroller
isgivingpulseswithparticularfrequencytols293A,the motorisrotatedinclockwise oranticlockwise.

StepAngle

 Stepangle ofthesteppermotoris definedastheangletraversedbythemotorinonestep.

 Tocalculate stepangle,simplydivide360by number ofstepsamotortakestocompleteonerevolution.

 Motorrotatinginfullmodetakes4stepstocompletearevolution,sostepanglecanbecalculatedasstepangleθ
=360° / 4 =90.

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 By knowing thesteppermotorstepangle helpstomovethemotorincorrectangular position.
 As you can see the stepper motor is connected with Microcontroller output port pins through
aULN2803Aarray.
 So when the microcontroller is giving pulses with particular frequency to ls293A, the motor is rotated
inclockwise oranticlockwise
ProgramtointerfaceSteppermotorwith8051
 Tocontrolasteppermotorin8051trainerbyturningON&OFFafourI/Oportlinesgeneratingataparticular
frequency.
 The 8051trainer kit hasthree numbers of I/O portconnectors,connectedwithI/OPortlines(P1.0–P1.7),(P3.0–
P3.7)to rotatethesteppermotor.
 LS293DisusedasadriverforportI/Olines,driversoutputconnectedtosteppermotor,connectorprovidedforexter
nalpowersupplyifneeded.

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By givingtheexcitationasindicatedabovethroughport1we canrotatestepper motorinclockwise
oranticlockwise direction.

NOTE:Toturnthemotorinthereversedirectionenter as(RLA
insteadofRRA).Theschematicsectionsgivenis,steppermotorconnectedtoport 1 andthesampleprogramisgivenbased
on 8255.

STUCOR
APP
Example4:Describethe8051connectiontothesteppermotoroffigureshowsandcodeaprogramtorotate
itcontinuously.

Figure:InterfacingStepperMotorwith8051
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Solution:

MOV A, #66H Loadstepsequence

BACK: MOV P1,A Issue sequence to
motor
RR A Rotate right
clockwise
ACALL DELAY Wait
SJMP BACK Keepgoing
…………….
DELAY
MOV R2,#100H
H1: MOV R3,#255H H1:
H2: DJNZ R3,H2 H2:
DJNZ R2,H1
RET

********************************************************************************************

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**********************************************************************************************

4. WASHINGMACHINECONTROLI
NTRODUCTION:
 Washingmachineconsistsofawashingbasketthatcanrotate.
 InthecentreofthebasketisacylindricalverticalcolumncalledAgitator.
 TheAgitatorcanalsomoveindependently.
 Thewater,detergentandclothsareputinthewashingbasket.
 Duringwashing,theagitatorandthewashingbasketrotateinoppositedirectionsinsmallsteps.
 Duetothisaction, theclothesgetwashed.

1. InputSettings
Therearefourknobsforprogrammingthewashingmachine.
1) Loadselect
 Loadmeansthenumberofclothesintendedtobewashedtogether.
 Therearethreesettings(high,mediumandlow).

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 Basedontheloadselected,themachinedecidestheamountofwaterrequired.
2) WaterInletSelect
 Machinecantakeeitherhot,tapormixwater.
 Therearetwoinletpipesonthe machine forhotandtapwater.
 Theknobsetting “mix”allows50%tapand50% hotwaterasinput.
3) Modes
Throughthisknob,the machinecanbeoperatednormalorsave mode.
(i) Normalmode
1. Theclothesarewashed.
2. Thedetergentisdrained.

3. Thefreshwaterisput.
4. Theclothesarerinsed.
5. Thewaterisdrained.
6. Usingspin, themoisturefromclothesistakenout.
(ii) Savemode
Thesavemodehasbeendesignedtosavedetergent,andisusedwhenclothesneedtobewashedinanu
mberoflots.
4) ProgramSelect
 Usingthisknob,themachine isprogrammedtowashtheclothesofdifferent kinds.
 ThevarioussettingsareExtraHeavy,Heavy,Normal,Light
andDelicate.2.Indications
1. MachineON:ThereisanLEDindicationwhichglowswhenthemachine isON.
2. WashingComplete:Asoundisgeneratedtoannouncethatthewashingiscomplete.

3. WashingCycle
Differentoperationsperformedbythe machineinatypicalwashcyclesare
 Fill
 Agitate
 Soak
 Drain
 Spin
 Fill:
 Wateris filledthroughtheinlet.
 Thequantityofwaterdependsontheloadsetting(high,mediumor low).
 Inthefirstfill,watertemperatureisdecidedbythe settingtap,hotormix.
 Inthesecondfill,afterdrainandspin,onlytapwaterisfilledforrisingtheclothes.
 Agitate:

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 Inthisoperation, thewashbasket rotatesinsmallsteps.
 Aftereverystep,it waitsforsomesecond.
 Simultaneously,theagitatorrotates intheoppositedirectioninsmallstepsandaftereverystep,there is
waitstate.
 Soak:
 Theoperationisusedtoallowtheclothestosoakthedetergent.
 Themachineoperationbasicallystopsforaspecifiedtimeperiod.
 Drain:
 Allthewaterand detergentaretakenoutthroughthedrainpipe.
 Spin:
 Inthisoperation,theagitatordoesnotmove.
 Thewashbasketisrotatedathighspeedandmostofthemoisturefromclothesistakenoutthroughholesi
ntheinnermetallicbasket.

4. ControlSystemDesign
 Withtheaboveknowledgeabouttheoperationofthewashingmachine,consider8051microcontroller
basedwashingmachine.
Thevariouscontrolsare:
 Inletcontrolofwater
 Waterquantitycontrol
 Agitatorcontrol
 Spincontrol
 Draincontrol
 Programcontrol
 Waterinletselect
 Loadselect

Inputs&Outputportassignments:

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FLOWCHARTFORWASHINGMACHINE:

WASHINGMACHINEINTERFACINGUSING8051
Thevariousindicationsare:
 Machineonindication(LED)
 Washingcomplete(LED+BUZZER)
 Alltheportsof8051canbeusedforinput–outputoperations.
 Agitatorcontrolrequirescontrollingofbothsteppermotors1and2.
 Henceeightlineswillberequiredforthispurpose.

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Figure:WashingMachinecontrolCircuit using8051

Figure:Hardwareinterfacingusing8051

PROGRAM:
SMRT: JNB P0.0,START ;checkforstar
JNBP0.1,SKIPW ;checkifprewashisactivated
SETBP1.0 ;ifyesdoprewashCALLD_PREWASH
;waitforprewash

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CLRBP1.0 ;stopprewash
SKIPW: SETBP1.1 ; Do Main wash
1CALLD_MAINWASH1
;Waitformainwash1CL
RBP1.1 ;stopmainwash1
JNBP0.2,SKIPMW2 ;checkifclothtype iscotton
SETBP1.2 ; if yes do main
washCALLD_MAINWASH2 ; Wait for main
wash2CLRBP1.2 ;stopmainwash2
SKIPMW2:SETBP1.3 ;Dorinse1
CALLD_RINSE1 ;waitforrinse1
CLRBP1.3 ;stoprinse1
JNBP0.2,SKIPRINSE2 ;
CheckforclothtypeiscottonSETBP1.4 ;Ifyesdorinse 2
CALLD_RINSE2 ;Waitforrinse2
CLRBP1.4 ;stoprinse2
JNBP0.2,SKIPGS ;checkforclothtypeiscotton
SETBP1.5 ;Ifyesdogradualspin
CALLD_GS ;waitforgradualspin
CLRBP1.5 ;stopgradualspin
SKIPGS: SETBP1.6 ;Dospin
CALLD_SPIN ;waitforspin
CLRBP1.6 ; StopSpin
LJMPSTART ;Gotostart

*
*
Explaintheclosedloopcontrolofaservomotorusing8051withaneatdiagram.[April/May2017,May/June2016,N
ov/Dec 2014,May/June2013,Nov/Dec 2015][December2017]
Explaintheservomotorusing8051microcontroller.[April/May2011]
***************************************************************************************
5. CLOSEDLOOPCONTROLOFSERVOMOTOR

INTRODUCTION:
 Servomotorisbasedonservomechanismanditismainlyusedforpositioncontrol.
 Aservosystemmainlyconsistsofthreebasiccomponents–

 Acontrolleddevice

 Outputsensor

 Feedbacksystem.

 Thisisanautomaticclosedloopcontrolsystem.
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 Hereinsteadofcontrollingadevice byapplyingthevariable inputsignal,thedevice

iscontrolledbyafeedbacksignalgeneratedbycomparing outputsignalandreferenceinputsignal
 Theservomotorismostcommonlyusedintheindustrialapplicationlikeautomationtechnology.

 Itisaselfcontainedelectricaldevicethatrotatespartsofamachinewithhighefficiencyandgreatprecision.
 Theoutputshaft ofthismotorcan bemovedtoaparticularangle.

 Servomotorsaremainlyusedinhomeelectronics,toys,cars,airplanes,etc

TYPESOFSERVOMOTOR:

 Servomotorsareclassifiedintodifferenttypesbasedontheirapplication,suchas

 ACservomotor
 DCservomotor
 BrushlessDCservomotor
 Positionalrotation
 Continuousrotation
 Linearservomotoretc.

 Typicalservo motorscompriseofthreewiresnamely,powercontrolandground.
 Theshapeand sizeofthesemotorsdependontheirapplications.DCSERVOMOTOR.
 Themotorwhichisused asaDCservomotorgenerallyhaveaseparate
DCsourceinthefieldofwinding&armaturewinding.

 DCservomotorprovidesveryaccurateandalsofastrespondtostartorstopcommandsignalsduetothe
lowarmatureinductive reactance.
 DCservomotorsareusedinsimilarequipmentsandcomputerizednumericallycontrolledmachines.

ACSERVOMOTOR:

 ACservomotorisanACmotorthatincludesencoderisusedwithcontrollersforgivingclosedloopcontrolandf
eedback.
 Thismotorcanbeplacedtohighaccuracyandalsocontrolledpreciselyascompulsoryfortheapplications.
 ApplicationsofanACmotormainlyinvolveinautomation,robotics,CNCmachinery,andother

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applicationsahighlevelofprecisionandneedfulversatility.

Figure:Feedbacksignaltothemicrocontroller

Figure:Controllingaservomotorwithanglerotations.

POSITIONALROTATIONSERVOMOTOR

 Positionalrotationservomotorisa mostcommontypeofservomotor.

 Thesecommonservosinvolveinradiocontrolledwater,radiocontrolledcars,aircraft,robots,toysandmanyot
herapplications.
CONTINUOUSROTATIONSERVOMOTOR
 Continuousrotationservomotorisquiterelatedtothecommonpositional
rotationservomotor,butitcangoinanydirectionindefinitely.
 This type of motor is used in a radar dish if you are riding one on a robot or you can use one as a
drivemotoronamobilerobot.
ADVANTAGESOFSERVOMOTOR

 Theservomotorissmallandefficient.

 High-speedoperationispossiblebytheservomotors.

APPLICATIONSOFSERVOMOTOR

 Theapplicationsofservomotorsmainlyinvolveincomputers,robotics,toys,CD/DVDplayers,etc.

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DCSERVOMOTORINTERFACINGWITHTHEMICROCONTROLLER

 Theactualpositionofthemotorissensedwiththesensorandit iscomparedwiththedesiredposition.

 Thedifferencebetweentheactualanddesiredposition,themotorrotateseitherinclockwisedirectionoranticlo
ckwisedirection.
 Thusthepositionoftherotoriscontrolledbythecontroller output.

FLOWCHART:

Figure:Flowchartforclosed loopcontrolofDCservomotor

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DCSERVOMOTORINTERFACINGWITH8051.

Figure:DCServoMotorInterfacingWith8051

PROGRAM:

Label Mnemonics Operand Comments

MOV A, P0 Gettheactualpositionvaluefromthe
inputportP0.
MOV R0 GetthedesiredpositionvalueinR0of
,#data selectedregisterbank.
SUBB A,R0 Findthedifferencebetweenactualand
desiredposition.
MOV R1,A StoretheresultinR1ofselected
registerbank.
JZ L1 Iftheresultiszero,makethemotorto
stop.
JC RIGHT Ifthemagnitudeofdesiredpositionis
high,gotoRIGHT.
LEFT: RLC A
DNZ R1,LEFT Orelsemakethemotortorotateleft
untilthedesiredpositionisreached.
L1: MOV P1,00H Maketherotortostoprotating.
RIGHT: RRC Amakethemotortorotaterightuntil
thedesiredpositionisreached.
DNZ R1,RIGHT
SJMP L1 Maketherotortostoprotating

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RET

SAMPLEPROGRAMS:(8051Microcontroller)
1. Addtwo8-bitnumbers

MOVA,#30H ;(A)30
ADDA, #50H ;(A)→ (A)+50H

2. Addtwo16-bitnumbers

MOVDPTR,#2040H;(DPTR)←2040H(16bitnumber)
MOVA,#2BH ;(A) 2BH (lower byte of second 16 bit
number)MOVB,#20H ;(B)
20H(Higherbyteofsecond16bitnumber)ADDA, DPL
;Addlowerbytes
MOVDPL, A ;Saveresultoflowerbyteaddition
MOVA,B ;Gethigher byteofsecondnumberinA
ADDA, DPH ;Addhigher byteswithanycarryfromlower
byteadditionMOVDPH,A ;Save resultofhigher byte addition

3. Divisiontwo8-bitnumbers

MOVA,#90 ;GetthefirstnumberinAMOVB,#20
;GetthesecondnumberinBDIV A,B
;A+B,RemainderinBandQuotientinA

4. Tofindthesumof10numbersstoredin thearray. (June2016)

Statement:Calculatethesumofseriesofnumbers.Thelengthoftheseriesisinmemorylocation2200H
andtheseriesitselfbeginsfrommemorylocation2201H.

a. Assumesthesumtobe8-
bitnumbersoyoucanignorecarries.Storethesumatmemorylocation2300H.
b. Assumethesumtobe16-bitnumber.Storethesumatmemorylocations2300Hand2301H.

Sampleprogram

2200H=04H
2201H=20H
2202H=15H
2203H=13H
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Result=20+15+13+22=6AH2300H=6AH

Program

MOVDPTR, #2200H
;Initializememory
pointerMOVXA, @DPTR ;Getthecount
MOVR0,A ;Initializetheiterationcounter
INCDPTR ;Initializepointerto arrayofnumbers
MOVR1,#00 ;Result=0
BACK: MOVX A, @DPTR; get the
umberADDA,R1 ;AResult+A
MOVR1,A ;ResultA
INCDPTR ;Incrementthearraypointer
DJNZR0, BACK ;Decrement iterationcountifnotzerorepeat
MOVDPRT,#2300H ;Initialize
memorypointerMOVA,R1 ;Gettheresult
MOVX@DPTR,A ;Storetheresult

ampleprogram

2200H=04H
2201H=9AH
2202H=52H
2203H=89H
2204H=3EH
Result=9AH+52H+89H+3EH=6AH
2300H=B3H Lower
byte2301H=01HHigherb
yte

Program

MOVDPTR,#2200H ;Initialize
memorypointerMOVXA,@DPTR ;Getthecount
MOVR0,A ;Initializetheiterationcounter
INCDPTR ;Initializepointerto arrayofnumbers
MOVR2,#00 ;[Make resultR2= 00H]
MOVR1,#00 ;[Make resultR1=
00H]BACK:MOVXA,@DPTR;getthenumber
ADDA,R1 ;AResult+A
MOVR1,A ;ResultA
ADDCR2, #00 ;ifcarryexists,add ittoMSD
INCDPTR ;Incrementthearraypointer
DJNZR0, BACK
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VDPTR, #2300H ;Initializememorypointer

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MOVA,R1 ; Get the lower byte of
resultMOVX@DPTR,A
;StorethelowerbyteofresultIN
CDPTR ;Incrementmemorypointer
MOVA,R2 ;Getthehigherbyteofresult
MOVX@DPTR,A ;Storethehigherbyteofresult

************************************************************************************
Designamicrocontrollerbasedwater levelcontrolsystem indetail. (April 2018)
************************************************************************************
6. WaterLevelControllerusing8051CircuitPrinciple

 This system mainly works on a principle that “water conducts electricity”. The four wires which
aredipped into the tank will indicate the different water levels. Based on the outputs of these
wires,microcontroller displayswater level onLCDaswell ascontrols themotor.

 Initially when the tank is empty, LCD will display the message LOW and motor runs
automatically.Whenwater level reachestohalflevel,nowLCD displaysHALFandstillmotorruns.

 When the tank is full, LCD displays FULL and motor automatically stops. Again, the motor runs
whenwater level in thetank becomesLOW.

 The water level probes are connected to the P0.0, P0.1 and P0.2 through the transistors (they
areconnectedtothebase
ofthetransistorsthroughcorrespondingcurrentlimitingresistors).P0.0forLOWlevel,P0.1
forHALFLevelandP0.2forHIGH Level.

 TheCollectorterminals oftheTransistorsareconnectedtoVCCand
theEmitterterminalsareconnectedto PORT0terminals(P0.0, P0.1andP0.2).

 PORT1 of the microcontroller is connected to the data pins of LCD and the control pins RS,
RWandENoftheLCDDisplay areconnectedto theP3.6,
 GNDandP3.7respectively.

AlgorithmforWaterLevelControllerCircuit

 Firstconfigure thecontroller pinsP0.0,P0.1andP0.2asinputsandP0.7as output.

 Now,initializetheLCD.
 Continuouslycheckthewater levelinputpinsP0.0,P0.1andP0.2. 
 If all the pins are low, then display tank as “EMPTY” on the LCD and make P0.7 pin HIGH to run
themotorautomatically. 

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Figure:WaterLevelControllerusing8051

 Ifthe levelislowi.e.ifP0.0isHIGH,displaythewater levelas“LOW”and continuetorunthemotor. 

 A HIGH pulse on the pin P0.1 indicates that water has reached half level. So, display the same
thingonLCDand run themotornormally. 

 IfP0.2isHIGH,thenthewaterlevelinthetank isFULL. 
 Now,make theP0.7pinasLOW toturnoff themotorautomatically

*****************************************************************************************
Develop a 8051 ALPto evaluate an arithmetic expression (A–B) XC Where A,B,C are8 bit data
ininternalmemory.Assme A>Bandstoretheresultin externalmemory.Explaintheprogram
developed.(Dec 2018)
MOV
A,#DATA1MOV
B,DATA2MOVC
,#DATA3
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SUBBA,B
JCL1MOV
B,CMULA
B
LI MOV
DPTR,#4500MOV
@DPTR,A
L2 SJMP L2

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