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Design and Analysis of Approximate Multipliers

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 IJRECE VOL. 6 ISSUE 4 ( OCTOBER- DECEMBER 2018) ISSN: 2393-9028 (PRINT) | ISSN: 2348-2281 (ONLINE)

Design and Analysis of Approximate Multipliers

Priyadarshini.V1, V. Sreelakshmi 2, S.Bhavani3
1,2,3
Asst.prof Department of ECE, Gudlavalleru Engineering College, Gudlavalleru

Abstract— Approximate computing is a computation An nxn multiplication is conventionally composed of three

technique which returns a possibly inaccurate result rather operational phases: Partial product generation, Carry-free
than the guaranteed accurate result and can be used for reduction of partial products and Carry propagating
applications where an approximate result is sufficient for its addition. The Partial product reduction phase has been the
purpose. Approximate multipliers are widely being used for subject of most research and design efforts on parallel
energy efficient computing in applications that exhibit an multipliers mainly because it is the most area and power
inherent tolerance to inaccuracy. Besides the performance of consuming part among the three.
the multiplier, the area and delay makes the identification of In this paper we mainly focus on approximation in the
suitable approximate multiplier is quite challenging. Hence, partial product tree of approximate multiplier. For the
we identified the type of approximate full adder will be one of partial product summation and carry free addition we
the major decision making factor for the selection of proposed different approximate full adders and half adders.
approximate multipliers. Approximate adders are used for the To improve the speed of operation we proposed a new
partial product summation in the multiplier. In this paper, an approximate 4x2 compressor.
approximate multiplier is designed and analyzed with four The rest of this paper is organized as follows. In Section II,
different approximate adders. The design is simulated and approximate adders are briefly reviewed. Approximate 4x2
synthesized using Xilinx Vivado. Compared with previously compressors is described in Section III. The Approximate
presented approximate multiplier, the proposed circuits multiplier using approximate adder and compressor is
provide significant reduction in area and power. described in Section IV. Section V deals with the
Keywords— Approximate computing, Approximate full comparison results. Finally, this paper is concluded in
adder, Partial product, Approximate multiplier. Section VI.
II. APPROXIMATE ADDERS
I. INTRODUCTION
In this section we discuss different approximations applied to
At the Nano scale era, improving performance of digital
conventional adders for designing approximate adders.
circuits and systems becomes increasingly difficult. Energy
efficiency is of paramount concern in digital system design.
Approximation I
Computing becomes increasingly heavy with multimedia
processing (audio, video, graphics, and image), recognition,
Approximation cannot do in arbitrary fashion. We need to
search, machine learning and data mining. Researchers and
make sure that the resulting simplification should introduce
designers started to search novel solutions to compute
minimal errors in the FA truth table. Here, Approximation is
efficiently. One of the most promising solutions is given by
done for both half adder and full adder by replacing XOR gate
the approximate computing. A common characteristic is
of sum with OR gate, as XOR gate tends to occupy more area
that a perfect result is not necessary and an approximate or
and produces long delay. This approximation results in one
less-than-optimal result is sufficient. Approximate
error in sum computation. [7]
computing reduces the hardware required for design of the
After approximating, the half adder equations are given in (1)
system as compared to accurate computing.
Sum= A+B
Adders and multipliers are the basic fundamental units in
Carry=A.B .......... (1)
each and every digital circuit used for performing the
In full adder, any one of the XOR gates is replaced by the OR
calculations. With the rapidly growing trends in scaling up
gate in Sum calculation. This results error in last 2 cases out of
to nanometer scale, the arithmetic circuits need to be
8 cases. Carry is modified as in (2)
implemented with low power, compact size, and less
P=A+B
propagation delay. These are the reasons for realizing the
Sum=P XOR C
adders and multiplier blocks using approximate computing.
Carry= AB+BC ........ (2)
Multipliers are key components of many high performance
digital systems. A system’s performance is generally
Approximation II
determined by the performance of the multiplier as the
multiplier is generally the slowest element in the system The truth table of Full adder shows that Sum= Cout for six
and generally consumes more area and power and long out of eight cases, except for the input combinations A = 0,B =
latency. Therefore, low-power multiplier design has been 0,Cin = 0 and A = 1,B = 1,Cin = 1.With this approximation
an important part in low-power VLSI system design. sum has two errors and carry has no error for all the cases.[2]

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considered same as carry in exact compressor. No
Approximation III approximation is applied for the Carry. [5]
A close interception of Full Adder truth table shows that Carry = Cin
Cout=A for six out of eight cases or Cout =B for 6 cases. so Sum= (A⊕B) l+ (C⊕D)l
in Approximation III Sum is calculated as in Approximation I Cout=A.B+C.D ……… (3)
with three errors and Cout=A.
Table II
Approximation IV Truth table of 4:2 Approximate Compressor
For more error tolerant Applications, We can extend
Approximation IV with Sum= B by allowing one more error.
And Cout=A.[3]
Table I
Truth table of adders with Approximation I -IV

III. APPROXIMATE COMPRESSOR

The number of partial products in the multiplication process

can be reduced by using the compressors. In general the
compressor size can be represented as m:n ,where m
represents the number of input bits and n represents the
number of output bits. Compressors are of two types Low
order compressors and High order compressors. In this Table III
approximate multiplier design we used a low order Synthesis Results of 4 : 2 Compressor
approximate compressor (4:2) for reducing the partial
products. [3] Area in terms of
Compressor Type Delay in ns
The low order approximate compressor is designed with the LUT’s
two approximate full adders. Exact 4: 2
6.582 4
compressor
Approximate
compressor 4 : 2 5.103 2
compressor

IV. APPROXIMATE MULTIPLIER

Exact 8x8 multiplier:

Compared to other implementation techniques for

multiplication process, Dadda technique for multiplication
process decreases the number of adder stages. In this
Fig 1: 4:2 Compressor techniques half adder and full adders are used for summation
of the partial products. Due to this hardware complexity is
To maintain minimal error difference , In sum computation reduced.
the XOR gate can be replaced by an OR gate. This The Dadda multiplication process is shown in Fig 2.
approximation results 5errors out of 16 cases. Carry is

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The expression for the partial products of a and b is
am,n=am. bn............................(5)
by equ(5) parial products can be obtained as in fig 3.

Fig 3: Partial product generation for Dadda Multiplier

Reduction in partial product tree:

suppose if we have multiplier and multiplicand bits n =4, the

partial products may be from 0-15. if n=8, partial product
terms ranges from 0-63. for n=16, the partial products ranges
from 0-255 i.e, as the number of bits in inputs are increasing
the number of partial products are greatly increasing. For
summation of all the partial products multiplier requires more
number of half and full adders which in deed increase the
hardware complexity of the multiplier circuit. So there is need
Fig 2: Exact Multiplier to reduce the partial products in the multiplication process.
The reduction in the terms can be done from the stastical point
Approximate 8x8 Mulitplier: of view. The probability of getting partial product should be 1
is 1/4. Partial products reduction can be done in column wise.
In this paper an 8x8 multiplier is proposed using dadda The column which is having more than three partial products
multiplication techniques. Approximation techniques are can be altered. [1]
applied at different stages in the multiplication process. In this architecture column 3 to column 11 partial products are
changed.
Different approximation techniques are proposed for the The partial products am,n and an,m are combined together to
summation of the partial products. get propagate term and generate term. The propagate and
generate terms are represented as Pm,n and g m,n.
Multiplication process basically divided in to three steps The mathematical expressions for Pm,n and g m,n. are
1. Generation of partial products
2. Reduction in the partial product tree by applying Propagate term= am,n or an,m...................(6)
approximate compressor generate term= am,n and an,m.....................(7)
3. Addition of the partial products
The generate signal g m,n. has the probability of being 1/16
Generation of the partial product: which is less than the probability of Pm,n which is significantly
In this paper we considered an 8 bit multiplicand and an 8 bit lower than 1/4 of am,n. The probability of altered partial
multiplier. Let us say a is multiplicand and b is the multiplier. product pm,n being one is 1/16 + 3/16 + 3/16 =7/16, which is
the mathematical representation of the multiplicand and higher than gm,n. These factors are considered, while applying
multiplier are as follows approximation to the altered partial product matrix.
The accumulation of generate signals is done column wise. As
a=∑7m=0am2m ............................ (3) each element has a probability of 1/16 of being one, two
b=∑7n=0an2n ............................. (4) elements being 1 in the same column even decreases. As the
number of generate signals increases, the error probability
increases linearly. For a column having m generate signals,
Partial product is generated by logical AND operation
m/4 OR gates are used.
between Multiplier and Multiplicand bits.

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Table IV
Synthesis Results of Approximate Multipliers
Area in
Approximate Delay Power in PDP
terms of
Multipliers in ns mw (p J)
LUT’s
Approximation
23 3.977 78 310.206
I
Approximation
26 4.003 87 348.261
II
Fig 4: Reduction of partial Product Tree Approximation
19 3.879 56 217.224
III
Addition of the partial products: Approximation
16 3.853 53 189.899
IV
To perform the addition of the partial products we used
different approximate adders and approximate compressors. If high approximation can be tolerated for saving more power
The structure is shown in Fig.5 [7] and delay Approximation IV has to used. Approximation IV
offers 43% area savings and 68% power savings over
Approximation I.
Table III gives a comprehensive comparison of approximate
multipliers to get an idea of tradeoff between Area, power and
delay.
For applications where high power savings are desired with
less area, Approximation IV can be used. For moderate power
savings with better performance, Approximation II is
suggested.

VI. CONCLUSION
In this paper, we have presented different approximate
multipliers, for partial product addition different
approximation techniques have applied on adders.
Approximation III and IV achieve significant reduction in area
and power consumption compared with Approximation I. The
proposed multiplier designs can be used in applications with
minimal loss in output quality while saving significant power
and area.
REFERENCES
References:
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and 3 approximate half and full adders in first stage. The Kaushik Roy Fellow,IEEE
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