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Assignment Title: SPICE Simulation of Universal Gates
Assignment No: 3 Date of Submission: 21 November 2024
Course Title: VLSI CIRCUIT DESIGN
Course Code: EEE4217 Section: B
Semester: Fall 2023-24 Course Teacher: Dr. Shahriyar Masud Rizvi

Declaration and Statement of Authorship:

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2. This Assignment/Case-Study is my/our original work and no part of it has been copied from any other student’s work or from
any other source except where due acknowledgement is made.
3. No part of this Assignment/Case-Study has been written for me/us by any other person except where such collaborationhas
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* Student(s) must complete all details except the faculty use part.
** Please submit all assignments to your course teacher or the office of the concerned teacher.

Group Name/No.: 3

No Name ID Program Signature

1 Hamim Ibrahim 22-48533-3 BSc [EEE]
2 Tareq Abir Tonmoy 20-42471-1 BSc [EEE]
3 Sadia Tasnim Shara 22-48622-3 BSc [EEE]
4 Md. Atikur Rahman 22-49785-3 BSc [EEE]

Faculty use only

FACULTYCOMMENTS

Marks Obtained

Total Marks

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Abstract:
This experiment uses NGSPICE to simulate a 6-transistor inverter circuit and universal gates
(NAND and NOR). The main goals are to comprehend how CMOS logic gates work, identify
their transient behaviors, and contrast their voltage transfer characteristics (VTC) with those of a
typical CMOS inverter. On the basis of a reference inverter, transistor size for best performance
is also examined.

Introduction:
The purpose of the project is to introduce digital designers to CMOS universal gates, their
modeling and simulation, and their function as building blocks in logic circuits. Understanding
how transistor-level designs affect circuit behavior and figuring out how to maximize transistor
sizing for symmetrical functioning are the driving forces. This useful knowledge is essential for
creating CMOS circuits that are scalable and effective.

Theory:
The design, functionality, and function of universal gates (NAND and NOR) in CMOS
technology are the main topics of the experiment. Because they may be combined to produce any
logic function, including AND, OR, and NOT, universal gates are essential to digital logic. To
accomplish logic functionality, these gates in CMOS rely on pull-up (PMOS) and pull-down
(NMOS) transistor networks. NAND and NOR gates are inherently made possible by the
inverting nature of CMOS logic. To get the necessary logic out of complicated gates like AND &
OR, an extra inverter step is needed at the output.

The performance of CMOS circuits is significantly influenced by transistor size. The pull-up and
pull-down networks of NAND and NOR gates can be made to match these timing features by
utilizing a reference inverter with symmetrical rise and fall periods. The NMOS transistors in the
pull-down network, for instance, are connected in series in a 2-input NAND gate, which raises
the equivalent resistance. By keeping the same aspect ratio (W/L), the parallel PMOS transistors
in the pull-up network guarantee that the pull-up delay is equal to that of the reference inverter.
This symmetry guarantees dependable and effective circuit operation.

A more intricate configuration of transistors intended to improve switching characteristics is

introduced by a 6-transistor inverter or trigger circuit. In contrast to a typical CMOS inverter,
this circuit generates sharper voltage transitions by varying the aspect ratios of its transistors. By
examining these circuits' voltage transfer characteristics (VTC) and transient behavior, designers
may assess how well they function under changing circumstances. This knowledge is essential
for improving the speed, power efficiency, and dependability of CMOS circuits in sophisticated
digital architectures.

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Methodology:

Fig 1: A 2-input NAND gate’s transistor architecture

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Fig 2: A 2-input NOR gate’s transistor architecture

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Fig 3: A 6 transistor Inverter Architecture

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 1. Truth-table for the 2-input NAND gate

Logic-Level Logic-Level State of State of State of State of Logic-Level

of Input of Input MPU1 MPU2 MPD1 MPD2 of Gate
VA VB Output

0 0 ON ON OFF OFF 1

0 1 ON OFF OFF ON 1

1 0 OFF ON ON OFF 1

1 1 OFF OFF ON ON 0

2. Truth-table for the 2-input NOR gate

Logic-Level Logic-Level State of State of State of State of Logic-Level

of Input of Input MPU1 MPU2 MPD1 MPD2 of Gate
VA VB Output

0 0 ON ON OFF OFF 1

0 1 ON OFF OFF ON 0

1 0 OFF ON ON OFF 0

1 1 OFF OFF ON ON 0

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Simulation and Results:
Spice Code for NAND Gate:

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Transient Analysis of NAND Gate:
e

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Spice Code for NOR Gate:

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Transient Analysis of NOR Gate:

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Transient analysis of 6-Transistor Inverter Circuit:

Results Analysis:
1. Fall Time (tf) and Rise Time (tr) for NAND and NOR gates (Procedures 3 and 4):
Fall Time (tf): The time taken for the output voltage to drop from 90% of the high logic level to
10%.
Rise Time (tr): The time taken for the output voltage to rise from 10% of the low logic level to
90% .
For NAND gate,
Fall Time: Approximately 1.5 ns
Rise Time: Approximately 1.5 ns

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For NOR gate,
Fall Time: Approximately 1.5 ns
Rise Time: Approximately 1.5 ns
NGSPICE was used to simulate 2-input NAND and NOR gates in order to examine their timing
properties, transistor behavior, and functioning. Both gates' truth tables were finished,
demonstrating that their outputs matched theoretical predictions. The output of the NOR gate
was low unless both inputs were low, whereas the output of the NAND gate was high unless both
inputs were high.

By monitoring the transition points between 10% and 90% of the output voltage, the rise time (tr)
and fall time (tf) of the output waveforms were determined. These timing features demonstrated
how transistor size affects circuit performance. Additionally, the simulation confirmed that pull-
up and pull-down networks operated as intended, guaranteeing symmetrical rise and fall delays.
All things considered, the experiment showed how useful universal gates are in CMOS design
and how crucial proper transistor size is to maximizing logic gate performance.

2. Gate Threshold Voltage for the Trigger Circuit (Procedure 5):

VDD= 5V, VTH= VDD/2 = 2.5 V
With NMOS and PMOS transistors (designated MPU1, MPU2, MPD1, MPD2, etc.), this circuit
looks to be a CMOS inverter chain or a comparable setup, maybe a complicated gate, or a multi-
stage inverter. We must comprehend how the output voltage VOUT fluctuates in relation to the
input voltage VIN in order to examine its Voltage Transfer Characteristics (VTC).

Each transistor (PMOS and NMOS) may be in the cut-off, linear (triode), or saturation zone,
depending on the input voltage VIN. The transistors that are on or off at each step will determine
the VTC. The VTC plot would display the response of VOUT to variations in VIN. Around a
halfway voltage, VOUT in an ideal inverter would abruptly transition from VDD to 0 V.
However, because of the stages and transistors used in this circuit, the VTC may have many
slopes. The VTC of this circuit may change from that of a basic CMOS inverter if it is designed
to be a more complicated gate or has extra transistors for different functions. Its switching
thresholds, noise margins, and transition sharpness can all vary when compared to a simple
inverter.

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Recommendations:
Consider increasing simulation accuracy in the lab experiment by utilizing smaller time steps in
NGSPICE and verifying findings using other tools such as LTSpice. Adding parasitic effects to
simulations can increase their realism. Rise time, fall time, and threshold voltage analysis may be
streamlined by automating data extraction using programs like MATLAB. Investigating various
transistor sizes and testing circuits with noisy inputs can yield important information about the
performance and robustness of the circuit. The experiment's scope may be increased by adding
simulations of more complicated gates, such as XOR and XNOR, and by include power usage
analysis. The experiment may be more closely aligned with real-world manufacturing issues by
updating lab materials with contemporary CMOS design methodologies and taking process
variances into account. Lastly, adding overlay plots and thorough explanations to the lab report
can help readers better comprehend the theoretical and practical findings.

Conclusion:
This experiment gave a thorough grasp of the design and behavior of universal gates and a 6-
transistor inverter by successfully simulating them. With distinct insights into transistor-level
optimization and circuit performance assessment, the goals were completely achieved. Analyzing
power consumption and scaling implications on performance could be part of future
enhancements.

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