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Vlsi Lab Manual

The document outlines the design and layout procedures for CMOS NAND, NOR gates, and inverters using Microwind software. It details the theory behind each gate's functionality, including their circuit diagrams and simulation steps. The results confirm successful design and layout for the specified digital components.

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velumuritejo04
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13 views12 pages

Vlsi Lab Manual

The document outlines the design and layout procedures for CMOS NAND, NOR gates, and inverters using Microwind software. It details the theory behind each gate's functionality, including their circuit diagrams and simulation steps. The results confirm successful design and layout for the specified digital components.

Uploaded by

velumuritejo04
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment –01 Universal gates.

Aim: To design schematics and layout for CMOS NOR and NAND
using Microwind.
Apparatus: A personal computer with Microwind 3.9 installed in it.
Theory:
CMOS NAND Gate:
The CMOS NAND gate is a fundamental component in digital circuit
design, vital for logical conjunction and universal computation. It
consists of multiple series connected NMOS (N-type Metal-Oxide-
Semiconductor) transistors at the pull-down network and parallel-
connected PMOS (P-type Metal-Oxide-Semiconductor) transistors at
the pull-up network. When all inputs are high (logic 1), the NMOS
transistors provide a low-impedance path to ground, pulling the
output to a low state (logic 0). Conversely, if any input is low (logic
0), at least one NMOS transistor is off, enabling the PMOS transistors
to provide a high-impedance path to VDD (the power supply voltage),
driving the output to a high state (logic 1). This gate's design ensures
that it produces a low output only when all inputs are high,
embodying the NAND logic function. The CMOS NAND gate's
versatility and ability to realize any logical function make it a
fundamental building block in digital systems, widely employed in
arithmetic circuits, memory arrays, and microprocessors.
CMOS NOR Gate:
The CMOS NOR gate is another fundamental component in digital
logic design, essential for logical disjunction and universal
computation. It comprises parallel connected NMOS transistors at the
pull-down network and series-connected PMOS transistors at the pull-
up network. When at least one input is high (logic 1), the
corresponding NMOS transistor conducts, providing a low-impedance
path to ground and pulling the output to a low state (logic 0).
However, if all inputs are low (logic 0), the pull-up network of PMOS
transistors conducts, providing a high impedance path to VDD (the
power supply voltage) and driving the output to a high state (logic 1).
Thus, the CMOS NOR gate generates a low output whenever at least
one input is high, embodying the NOR logic function. The versatility
and simplicity of the CMOS NOR gate make it a fundamental
component in digital systems, playing critical roles in logic circuits,
memory arrays, and complex computational units.
Circuit diagram:

FIG.1.1: NAND GATE DIGITAL SCHEMATICS


FIG.1.2: NAND GATE DIGITAL SCHEMATICS

Procedure:
1. Open DSCH 3.9.
2. Navigate to file and Click Save as.
3. Now give a name and the file will save as Schematic(.sch).
4. Place the required components on field and connect them using "Add a line"
(wire).
5. After completion of connections Navigate to simulate and check the floating
line and critical path.
6. Now Start simulate and check the outputs.
7. Click on truth table at Simulate and check the truth table and waveforms.
8. Now convert the file into Verilog file by clicking at file and Make Verilog
file, then it creates a Verilog file at same path.
9. Open Microwind.
10. Navigate on Compile and click on Compile Verilog file.
11. Select the Verilog file and compile and click on back to editor.
12. Now the Layout is ready to use.

Observations:

FIG.1.3: NAND GATE CMOS LAYOUT DIAGRAM

FIG.1.4: NAND GATE OUTPUT WAVEFORM


FIG.1.5: NOR GATE CMOS LAYOUT DIAGRAM

FIG.1.6: NOR GATE OUTPUT WAVEFORM


Result:
Hence, designed schematics and layout for CMOS NOR and NAND
gates using Microwind.
1b).CMOS inverter.

Aim: To design schematics and layout for CMOS inverter using Microwind.
Apparatus: A personal computer with Microwind 3.9 installed in it.
Theory:
CMOS Inverter:
The CMOS inverter stands as a cornerstone in digital circuitry, serving
as a fundamental building block for logical inversion operations. Its
architecture consists of a PMOS (P-type Metal-Oxide-Semiconductor)
transistor connected in series with an NMOS (N-type Metal-Oxide-
Semiconductor) transistor. When the input signal is low (logic 0), the
PMOS transistor conducts, providing a path to the power supply voltage
(typically denoted as VDD), resulting in a high output (logic 1).
Conversely, when the input signal is high (logic 1), the NMOS
transistor conducts, creating a path to ground (typically denoted as
GND), resulting in a low output (logic 0). This inherent behavior of the
CMOS inverter is key to its role in logic inversion, where it transforms
input signals into their logical complements. The CMOS inverter's
simplicity, low power consumption, and compatibility with
semiconductor fabrication processes make it a fundamental component
in digital systems, essential for tasks ranging from signal buffering to
complex logic functions.
Circuit diagram:

FIG.1.7: NOT GATE DIGITAL SCHEMATICS

Procedure:
1.Open DSCH 3.9.
2. Navigate to file and Click Save as.
3. Now give a name and the file will save as Schematic(.sch).
4. Place the required components on field and connect them using "Add a line"
(wire).
5. After completion of connections Navigate to simulate and check the floating
line and critical path.
6. Now Start simulate and check the outputs.
7. Click on truth table at Simulate and check the truth table and waveforms.
8. Now convert the file into Verilog file by clicking at file and Make Verilog
file, then it creates a Verilog file at same path.
9. Open Microwind.
10. Navigate on Compile and click on Compile Verilog file.
11. Select the Verilog file and compile and click on back to editor.
12. Now the Layout is ready to use.

Observation:
FIG.1.8: NOT GATE CMOS LAYOUT DIAGRAM

FIG.1.9: NOT GATE OUTPUT WAVEFORM


Result:
Hence, designed schematics and layout for CMOS inverter using Microwind.

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