Getting Started with the LabVIEW FPGA IP

Export Utility
March 2020
The LabVIEW FPGA IP Export Utility allows you to develop an FPGA algorithm in the LabVIEW
FPGA Module and export the algorithm as IP (Intellectual Property) to be used on Xilinx Vivado FPGA
devices. The Utility provides two editions: LabVIEW FPGA Netlist Export Utility and LabVIEW FPGA
VHDL Export Utility. Use the LabVIEW FPGA Netlist Export Utility to export the algorithm in
encrypted netlist format. Use the LabVIEW FPGA VHDL Export Utility to export the algorithm in
encrypted netlist or plaintext VHDL format. You can then integrate the IP in your Vivado project and use
the IP on any Xilinx Vivado FPGA device of the same family.
This getting started manual assumes you are familiar with the LabVIEW FPGA module and Vivado
Design Suite.

Contents
Installation..................................................................................................................................................... 2
Getting Started with an Example .................................................................................................................. 2
Developing FPGA Algorithm ....................................................................................................................... 2
Determining Run-Time Behavior of Your FPGA VI ............................................................................... 2
Creating FPGA VIs ................................................................................................................................... 4
Exporting IP .................................................................................................................................................. 6
Choosing an Export Mode ........................................................................................................................ 6
Exporting IP .............................................................................................................................................. 6
Understanding IP Ports ................................................................................................................................. 8
Clock Ports ................................................................................................................................................ 9
Reset and Enable Ports.............................................................................................................................. 9
Data Ports .................................................................................................................................................. 9
Using IP in a Vivado Project ...................................................................................................................... 10
Importing IP Source Files ....................................................................................................................... 10
Instantiating IP ........................................................................................................................................ 10
Running Behavioral Simulation .............................................................................................................. 13
Appendix A, Using Single Shot IP ............................................................................................................. 13
Appendix B, Handling Multiple Clock Domains........................................................................................ 14
Exporting Every Clock Domain Separately ............................................................................................ 14
Using Synchronous Clocks ..................................................................................................................... 15
Installation
Refer to the readme file at labview\readme\readme_FPGA_IPExport.html for information about
system requirements, installation and activation instructions.

Getting Started with an Example

This getting started manual provides an example that demonstrates exporting an FPGA algorithm as IP.
NI recommends that you start with the example and refer to this manual to meet different needs for your
IPs.
You can find the example in the labview\manuals\LabVIEW FPGA IP Export Utility\Example
directory. The example develops a simple Multiplier in LabVIEW FPGA, allows you to export the IP to a
netlist, and guides you to integrate the netlist into a Vivado project.
Refer to the IP_Export_LV directory in the example for information about how to start in LabVIEW
FPGA. Refer to the IP_Export_Vivado directory in the example for information about how to use the
exported IP in Vivado. Follow the instructions in the example files to understand the basic workflow and
refer back to this manual for design details when needed.

Developing FPGA Algorithm

While developing an FPGA algorithm for exporting as IP is similar to general FPGA programming, you
must plan and design the algorithm in a way that makes the exported IP easy to integrate.

Determining Run-Time Behavior of Your FPGA VI

You can design a free running VI that processes data stream continuously or a single shot VI that stops
after processing one data sample and restarts when new data sample comes in.
The following figure shows an FPGA VI that runs continuously. The controls and indicators are placed
inside a single-cycle Timed Loop (SCTL). The controls are read and the indicators are updated at every
clock cycle. When input valid is asserted, the input data is fed into the multiplier. When the multiplier
produces a valid output, it sends the output data to the x*y indicator and asserts output valid.

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If you export this VI as IP, the IP runs freely and does not stop.

Figure 1, free running VI

The following figure shows a VI that stops after the For Loop completes. The control and indicator are
placed outside a SCTL. The control is read once, and the indicator is updated once in a single run. After
the VI stops, you can restart the VI when new data is ready.
If you export this VI as IP, the IP stops running after the For Loop completes and you can restart the IP
when new data is ready.

Figure 2, single shot VI

NI recommends that you design and export free running VIs by placing controls, indicators, and the
majority of your FPGA code inside a SCTL so that the VI runs continuously. Doing so makes the IP
interconnect easy and provides better throughput. Refer to the Dataflow and the Enable Chain in FPGA
VIs (FPGA Module) topic in the LabVIEW Help for more information about the differences between
inside a SCTL and outside a SCTL.
To export a single shot IP, refer to Appendix A, Using Single Shot IP.

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Creating FPGA VIs
Creating an FPGA VI for IP export is similar to creating any other FPGA VI. The following are special
considerations for creating an FPGA VI for IP export:
FPGA Target Family
Make sure the FPGA target that your FPGA VI runs on belongs to the same FPGA family as the target
where you will run the exported IP.
To check the family of your FPGA target in LabVIEW, right click the FPGA target in the project tree and
select Properties.

Figure 3, FPGA target family

Clocks
NI recommends using a single clock in your FPGA VI for easier integration. Unless explicitly specified,
this document assumes the FPGA VI includes only one clock domain. To use multiple clocks in your IP,
refer to Appendix B, Handling Multiple Clock Domains.
o Make sure the FPGA VI runs at a clock rate that matches the frequency at which you want the
exported IP to run. The exported IP will have the same behavior as the FPGA VI only if the FPGA VI
runs at the specified clock rate.
To check at which clock rate your FPGA VI runs, right-click the FPGA target in the project tree and
select Properties>>Top-Level Clock. To run your FPGA VI at a different clock rate that matches the
clock rate of your exported IP, create the clock in the project tree, right-click the FPGA target, select

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 Properties>>Top-Level Clock, and select the clock that you created as the top-level clock.

Figure 4, top-level clock for IP export

o Ensure the clock constant wired to the SCTL is the top-level clock or leave the Source Name
terminal unwired. Failing to do so results in clock domain crossing paths between SCTL control logic
and user logic on the SCTL diagram.
Controls and Indicators
o Place controls and indicators in the top-level FPGA VI. In the exported IP, controls become input
data ports and indicators become output data ports.
o The way you place the controls and indicators affects the way the exported IP behaves. If the controls
and indicators are placed inside a SCTL, the corresponding ports are accessed at every clock cycle
when the IP runs. If the controls and indicators are placed outside a SCTL, the corresponding ports
are accessed when dataflow execution reaches them. However, there is no external indication of at
which clock cycles they are accessed. Use the following guidelines to determine where to place
controls and indicators in the top-level FPGA VI:
o Create valid in / valid out signals or use four-wire handshaking signals for controls and
indicators inside a SCTL.
o Do not place controls and indicators outside SCTL unless your application can tolerate the
uncertainty of when the input ports are read and output ports are updated.
Loop Iteration
For every SCTL in the VI, create an indicator for the loop iteration terminal. When using the exported IP,
if the value of the corresponding port is greater than 0, the SCTL starts running and you can read or write
other ports inside the same SCTL. You can also use the First Call? node and wait until the port is de-
asserted. NI recommends that you use common prefix or suffix for the names of all controls and
indicators inside the same SCTL so that the corresponding ports are grouped together.
Unsupported Features
While you can use most nodes available on the palette as building blocks for your algorithm, you cannot
use the following nodes or features:
o Nodes that access external resources of FPGA chip:
o DMA FIFO

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 o Peer-to-Peer (P2P) FIFO
o DRAM Memory
o I/O nodes
o Interrupt
o User-Defined Variable
o User-defined component level IP (CLIP)
o Local variables in the top-level FPGA VI. You can use local variables in non top-level VIs.
Refer to the FPGA Module Help for more information about creating FPGA VIs.

Exporting IP
After you complete your FPGA algorithm in the FPGA Module, you can export the algorithm as IP for
integration with your Vivado project.

Choosing an Export Mode

The LabVIEW FPGA IP Export Utility provides two export modes: encrypted netlist mode and plaintext
mode. While the exported IP has the same functionality and interface in both modes, the two modes differ
in the following ways:
Encrypted netlist mode Plaintext mode
IP format Xilinx Design Checkpoint Primarily in VHDL (.vhd)
(.dcp) format. The code is in register
transfer layer (RTL) style. Some
functionalities are saved in
Xilinx Core Instance (.xci) or
Coefficients (.coe) format.
Encrypted? Yes. The LUT configuration is No. You can view exported files
protected from viewing. And in text editors.
ChipScope probing is
prohibited.

Exporting IP
In LabVIEW, complete the following steps to export your FPGA VI as IP:
1. From the Project Explorer window, right-click Build Specifications under your FPGA target
and select New>>Compilation from the shortcut menu.
2. In the Compilation Properties dialog box, specify the following options that configure how to
export the FPGA algorithm as IP. Ignore the other options.
o Information page
o Build specification name
o Allow removal of implicit enable signals inside single-cycle Timed Loops
Note This option is only visible for targets that support removing implicit enable
signals.
o
Source Files page
o Top-Level VI
3. Click OK to close the dialog box.
4. Right-click the build specification you created and select one of the following options:
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 o Export VI to Netlist File—Exports the IP in encrypted netlist mode.
Note If you do not see this option, check the activation status of the FPGA IP Export
Utility in NI License Manager.
o Export VI to Intermediate Files—Exports the IP in plaintext mode.
Note This option is available only if you have a valid license for the LabVIEW FPGA
VHDL Export Utility. Refer to the readme file at
labview\readme\readme_FPGA_IPExport.html for activation instructions.

Figure 5, Compilation build specification shortcut menu

5. The Generate Intermediate Files dialog box appears, indicating the progress of the export.
Depending on the complexity of your VI, this process may take a couple of minutes.
When the Generate Intermediate Files dialog box disappears, the output files are saved to the
intermediate files directory with the following pattern X:\NIFPGA\compilation\<project-
name>_<target-name>_<build-spec-name>_<unique-string>\source_files, where
X is the drive location where LabVIEW is installed. The following screenshot is an example of
the output files directory.

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 Figure 6, output files for encrypted netlist mode
If you export the IP in encrypted netlist mode, the intermediate files directory includes two files.
NiFpgaIPWrapper_<name>.vhd is the VHDL wrapper to help you integrate the IP in Vivado. Use it as
the top-level entity of exported IP. NiFpgaAG_<name>.dcp is the implementation of exported IP.

If you export the IP in plaintext mode, the intermediate files directory includes more files. The VHDL
wrapper is the same the encrypted netlist mode. The other files are IP source files. You can synthesize the
IP source files into an unencrypted netlist by running the .tcl file from Vivado Tcl Console. The netlist
file has same name as the one generated in encrypted netlist mode.
Notes

• LabVIEW overwrites the intermediate files directory the next time you build or export your
FPGA VI.
• LabVIEW does not export Xilinx design constraints (.xdc). Exported IP does not have physical
constraints. If the algorithm is contained in one clock domain, the IP does not require extra timing
constraints. If there are multiple clock domains, refer to Appendix B, Handling Multiple Clock
Domains.

Understanding IP Ports
The VHDL wrapper file provides detailed description for each port of exported IP. They are organized in
three groups: reset and enable ports, data ports, clock ports. Here is an example port description, exported
from the VI in Figure 1.

Figure 7, header in VHDL wrapper

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Clock Ports
This group contains all clocks in design. The VHDL wrapper shows the clock names and the frequencies
as configured in LabVIEW. One clock is marked with “base clock”, which is the top-level clock of the
FPGA target in LabVIEW. enable_in, enable_out, enable_clr ports belong to this clock domain.

If your algorithm uses multiple clocks, refer to Appendix B, Handling Multiple Clock Domains for more
information.

Reset and Enable Ports

The reset and enable ports control the execution of the IP. They exist for all exported IP and they are
active high.

• reset: asynchronous reset port. Use this port in combination with the enable_in port to reset
the IP.
• enable_in: enable in port. Must be synchronous to the base clock. Assert this signal to start
running the IP. This signal must remain asserted when the IP is running. De-assert this signal
when you reset the IP.
• enable_out: (output) enable out port. It is synchronous to the base clock. When this signal is
asserted, the IP stops. Ignore this signal for free running IP.
• enable_clr: enable clear port. Must be synchronous to the base clock. Assert this signal for one
cycle to prepare the single shot IP for restart. Tie this signal to ‘0’ for free running IP.

Data Ports
Data ports map to user-created controls and indicators in the top-level VI. The VHDL wrapper shows the
name, data type, and clock domain defined in your FPGA VI for every data port. The VHDL port name
has the “ctrlind_” prefix to avoid name conflict with non-user ports.
A LabVIEW data type is mapped to an std_logic_vector in VHDL. The direction of range is
descending, or (X downto 0). For scalars, Most Significant Bit (MSB) is placed at the left side of the
std_logic_vector. For arrays and clusters, the first element maps to the left-most bits and the last
element maps to the right-most bits. In the following example, Cluster has 33 bits. Bit 32 downto 25 is
Elem 0. Bit 24 downto 17 is Elem 1. Bit 16 downto 1 is Numeric. Bit 0 is Boolean.

Figure 8, cluster with multiple fields is mapped to std_logic_vector in VHDL

When reading or writing data ports, if the corresponding controls and indicators are placed outside a
SCTL, there is no external indication at which clock cycles they are accessed by the IP. If the

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corresponding controls and indicators are placed inside a SCTL, the ports are accessed at every clock
cycle when the corresponding SCTL is running.

Using IP in a Vivado Project

After you export your FPGA VI as IP, you can integrate the IP in your Vivado project using Vivado
Design Suite.
Vivado Design Suite is installed with the LabVIEW FPGA Module Xilinx Vivado Compilation Tool at
X:\NIFPGA\programs\Vivado<version>\ directory, where X is the drive location where LabVIEW
is installed. Launch Vivado Design Suite by double-clicking bin\vivado.bat.

Note NI recommends that you use the Xilinx Vivado version that’s compatible with the corresponding
LabVIEW version. Visit ni.com/info and enter the Info Code XilinxCompileTools for the version of Xilinx
Vivado compilation tool that’s recommended by each NI hardware and LabVIEW version.
Behavioral correctness and synthesizability of IPs exported from FPGA IP Export Utility are all validated
against the version of LabVIEW FPGA Module Xilinx Vivado Compilation Tool that is released together
with the same version of LabVIEW FPGA Module. Please note that this Vivado tool can contain patches
specific to NI and be different from the standard Xilinx Vivado version.

Importing IP Source Files

Import all exported IP source files from the intermediate files directory into your Vivado project. NI
recommends that you copy the source files into your Vivado project.
If your Vivado project includes multiple exported IPs, the IPs may contain subcomponents with conflict
names, which can cause problems in Vivado Design Suite. NI recommends that you export the IP in
encrypted netlist format and assign the exported IPs to different libraries in Vivado Design Suite, which
is a typical way to handle the potential name conflict issue.

Instantiating IP
After you import the IP source files into your Vivado project, complete the following steps to instantiate
the top-level entity of exported IP (NiFpgaIPWrapper_<name>.vhd) in your design:

1. Connect the clock port to the existing clock signal in your design. NI recommends that you use
a frequency that matches the one defined in your FPGA VI and set proper timing constraints for
the clock signal. Otherwise, some functions may not behave in the same way as in the FPGA VI.
2. Connect the reset signal to the reset port. Connect enable ports to appropriate signals.
3. Connect data ports to appropriate signal sources and sinks. Make sure the clock domains are
correct.

Resetting IP
You need to reset the IP after power on or when you want to re-initialize the internal states. In your
VHDL code, complete the following steps to reset an IP:
1. De-assert reset, enable_in and enable_clr.
2. Wait until clock signal is available.
3. De-assert all data valid signals on input data ports.
4. Assert reset for minimum reset assertion length clock cycles.
5. De-assert reset for minimum reset de-assertion length clock cycles.

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 6. Keep enable_in de-asserted for minimum re-initialization length clock cycles.

You can find the minimum clock cycles information in the VHDL wrapper.
The following figure shows a typical reset sequence for the IP exported from the VI in Figure 1. You can
see its VHDL wrapper in Figure 7. Minimum reset assertion length is 1 base clock cycle. De-assertion
length is 40 base clock cycles. Minimum enable_in re-initialization length is 7 base clock cycles.

Figure 9, typical IP reset sequence

Starting IP
In your VHDL code, complete the following steps to start a free running IP:
1. Tie enable_clr to ‘0’, leave enable_out open, and keep reset and enable_in de-
asserted.
2. De-assert all input valid signals on data ports.
3. Assert enable_in to start the IP and keep it asserted.
4. Monitor the output ports that correspond to the indicators that are connected to the SCTL loop
iteration
5. When the values start changing, read or write other data ports.
, as described in the Creating FPGA VIs section.The following figure shows a typical startup sequence for
the IP exported from the VI in Figure 1. The ctrlind_06_teration signal corresponds to the
iteration indicator in Figure 1. Do not change any data input signals or read any data output signals
until iteration is greater than 0.

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Figure 10, typical IP start sequence

Interfacing AXI IP
Complete following actions if your VI uses four-wire handshaking signals and you want to interface the
exported IP with another AXI4-Stream IP in VHDL. Four-wire protocol and AXI protocol have the
following differences:

• AXI data signals are byte aligned. The bit width must be integer multiple of 8 bits.
• ready for input in four-wire means the IP is ready to accept new data in the next clock cycle.
s_axis_tready in AXI means the IP is ready to accept new data in current clock cycle.

Four-Wire to AXI Interconnect

Pad data signals with ‘0’ to match the down-stream IP data widths. Connect output valid to
s_axis_tvalid. Connect s_axis_tready of the down-stream IP to ready for output.

Figure 11, four-wire to AXI interconnect

AXI to Four-Wire Interconnect
Discard padding bits from the up-stream IP data signals. Connect m_axis_tvalid to input_valid.
Connect ready_for_input through a register, then to m_axis_tready of the up-stream IP.

Figure 12, AXI to four-wire interconnect

Refer to the Scheduling Timing Using Handshaking Signals (FPGA Module) topic in the LabVIEW Help
for more information about the four-wire handshaking protocol.
Refer to the AXI Reference Guide, available on the Xilinx Web site at www.xilinx.com, for an in-depth
explanation of the AXI protocol and its benefits.

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Running Behavioral Simulation
NI recommends that you create a VHDL test bench for the exported IP and run behavioral simulation to
verify that its functionality matches your expectation before integrating the IP in your design. After the
integration, create test benches at different levels of your design to verify the IP works correctly with
other parts of your design.

Obtaining Behavioral Simulation Models for Netlists

If your exported IP is in netlist format, complete the following steps to obtain a behavioral simulation
model:
1. Start a new Vivado session.
2. In the Tcl Console window, enter the following Tcl commands:
open_checkpoint {path_to_dcp_file}
write_vhdl -force {path_to_new_file}
3. Close the Vivado session when the commands complete.
4. Return to your original Vivado project and add the .vhd file to the simulation sources.

Appendix A, Using Single Shot IP

Using single shot IP is similar to using free running IP with the following differences:

• You need the enable_out signal to indicate the IP is stopped and the enable_clr signal to
restart the IP.
• Do not change input data when the IP is running because you do not know at which clock cycles
the input data is read.
• Do not read output data until enable_out asserts for the same reason.
• Just like re-running a VI in LabVIEW, First Call? and Feedback Node configured with Initialize
on First Call are re-initialized after IP restarts.
In your VHDL code, complete the following steps to restart the IP after it is stopped:
1. When the IP is running, ensure enable_in is asserted, reset, enable_clr and enable_out
are de-asserted.
2. When enable_out asserts, the IP is stopped. Then read output data signals.
3. Assert enable_clr for one clock cycle. The earliest time to assert enable_clr is the same
clock cycle when enable_out asserts.
4. De-assert enable_in signal at the same cycle enable_clr asserts. Keep enable_in de-
asserted for minimum re-initialization length clock cycles.
5. Set new input data signals.
6. Assert enable_in to restart the IP. You can set input data signals and assert enable_in at the
same clock cycle.
The following figure shows the header of VHDL wrapper for the IP exported from the VI in Figure 2.
You can see the minimum re-initialization length is 7 clock cycles.

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Figure 13, VHDL wrapper for the IP exported from the VI in Figure 2
The following figure shows a typical restart sequence for the IP.

Figure 14, typical IP restart sequence

Appendix B, Handling Multiple Clock Domains

Note
When an FPGA design has multiple clock domains, all clock domain crossing paths need to be
constrained properly to ensure the design works as expected on real hardware. Refer to the
following Xilinx documents for information about timing analysis and timing constraints:
• Vivado Design Suite User Guide: Using Constraints (UG903)
• Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
• UltraFast Design Methodology Guide for the Vivado Design Suite (UG949)
Using multiple clock domains in your IP is an advanced use case. Successful compilation does
not mean the design will work properly on hardware. To avoid metastability or data corruption,
you must use tools provided by Vivado to analyze and debug timing issues and ensure all clock
domain crossing paths are constrained and meet timing requirements.
When there are multiple clock domains in your FPGA VI, the exported IP contains clock domain crossing
paths. Because the IP is generated by LabVIEW, it would be very difficult for you to create proper timing
constraints for paths inside the IP, especially if the IP is in encrypted netlist format. You can work around
this situation in two ways.

Exporting Every Clock Domain Separately

Complete the following steps to export every clock domain separately:
1. Rewrite your VI so that each portion of your algorithm runs in a single clock domain.

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 2. For every portion, set the top-level clock of the FPGA target to the clock you intend to use. Then
export that portion into an IP.
3. In Vivado, re-create all clocks with the same frequencies as in LabVIEW. Create clock period
timing constraints for each clock.
4. Import all IPs, implement clock domain crossing in VHDL with appropriate methods.
5. Create appropriate timing constraints for the implemented clock domain crossing paths.
The following is an example of rewriting your FPGA VI to export every clock domain separately.
In the original VI, as shown in the following figure, there are two SCTLs running at 90 MHz and 70
MHz, respectively. The FIFO implements the clock domain crossing.

Figure 15, original FPGA VI with two clock domains

The following figure shows the result of the rewrite with two separate VIs running in their own clock
domains. You need to remove the FIFO and replace it with controls and indicators for FIFO interface
signals. Remember to set the top-level clock when exporting each new VI.

Figure 16, split original VI to two separate VIs running in their own clock domains
In Vivado, connect the two IP blocks with a FIFO, as depicted in the following figure.

Using Synchronous Clocks

When two clocks originate from the same source, and their relative phase is predictable, Vivado
recognizes them as synchronous clocks and can analyze paths between the two clocks. If you use
synchronous clocks, you need to create clock period timing constraint only for the source clock. Refer to
Vivado documents UG903 for more information about synchronous clocks.

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In the following example, the 80 MHz clock is derived from 40 MHz Onboard Clock and frequency
multiplier is 2, hence the two clocks are synchronous. You can select 40 MHz Onboard Clock as the top-
level clock for the FPGA target and then export this VI.

The following figure shows the ports of exported IP.

In Vivado, complete the following steps to connect the clock signals:

1. Derive 80 MHz clock signal from a 40 MHz clock to match the clock hierarchy in the FPGA VI.
You can instantiate MMCM or PLL primitive or use Clocking Wizard LogiCORE IP to create the
derived clock.
2. Create clock period timing constraint for the 40 MHz clock.
3. Connect Clk40 to the 40 MHz clock.
4. Connect Clk40Derived2x1I0MHz to the 80 MHz clock.

Since the two clocks are synchronous, Vivado is able to analyze all clock domain crossing paths between
the two clock domains.

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