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Advanced ASIC Verification

Professional Growth Course - Course Curriculum

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 COURSE MODULES

Module 1 Module 2
SystemVerilog for Verification UVM for Verification

Module 3 Module 4
Perl Language for Scripting Design & Verification Projects
& Protocols
Module 5 Module 6
Advanced SystemVerilog & SOC Design & Verification
Advanced UVM Labs Debugging Techniques

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 Module 1 - SystemVerilog for Verification
SystemVerilog Overview
Standard Data types & Literals & Operators
User-Defined Data types & Structures
Testbench Architecture & Connectivity
Testbench Components
Static, Dynamic, Associative Arrays
Queues
Tasks & Functions
Interfaces, Virtual Interface Verification Features
Clocking Blocks, Mod ports
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 Module 1 - SystemVerilog for Verification
Object Oriented Programming, Classes | Objects
Polymorphism and Virtuality
Inheritance, Encapsulation
Random Stimulus
Class-Based Random Stimulus
Systemverilog Coverage analysis
Code Coverage, Cross Coverage
Deep into Functional coverage
Toggle Coverage
Assertion Based Verification(ABV)
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 Module 1 - SystemVerilog for Verification
SystemVerilog Assertions
Direct Programming Interface(DPI)
Interprocess Synchronization
Testbench Components
Testbench Examples
Testplans, Testcases
All topics theory + Lab sessions
Regular assignments
Mock tests
Interview Preparation
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 Module 2 - UVM for Verification
Indepth of UVM in SOC | IP level Verification
Detailed explanation on UVC in SOC | IP Verification
Introduction to UVM, Features
Testbench Hierarchy, Components
UVM Sequence Item, Sequence, Sequencer
Configuration, UVM config_db
UVM Phases
UVM Driver
UVM Monitor
UVM Agent
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 Module 2 - UVM for Verification
DTPs(Detailed Test Plan Explanation)
Testcase scenarios
Detailed feature wise test implementation
All topics theory + Lab sessions
Regular assignments
Mock tests
Interview Preparation

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 Module 3 - Scripting Language - Perl
Introduction to Linux Setup
Importance of Perl Scripting
How to run the commands
Idea on Coverage analysis
Upload and extract the coverage report
Walk through perl concepts
Coding standards
Importance of Regressions | How to Run the Regression
How to check test pass or fail in SOC | IP Level
Idea on debugging testcases, execution flow
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 Module 4 - Projects & Protocols
Project 1- UART Protocol - RTL Design Using Verilog HDL
Theory
Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram
Implementation
Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver
Testbench Creation and Simulation
Debugging and Waveform Analysis

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 Module 4 - Projects & Protocols
Project - 2 I2C Protocol Implementation and Verification
Theory
I2C Protocol Overview: Features, Signals, and Modes of
Operation
Multi-Master and Multi-Slave Configurations
Timing Diagram and Bit-Level Analysis
Implementation
RTL Design of I2C Controller
Writing Test Cases in SystemVerilog
Testbench Creation and Verification using SystemVerilog
Coverage Metrics and Analysis

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 Module 4 - Projects & Protocols
Protocols - AMBA Protocols (APB, AHB, AXI)
Theory
Deep Dive into AMBA Protocols: Overview and Features
Detailed Signal Features of APB, AHB, and AXI Protocols
Comparison and Use Cases in Industry
Functional Features of APB, AHB, AXI
Detailed understanding on Master & Slave transactions
Pipeline & Non-pipeline structure, Burst transfers
Out of order transaction features, Multiple outstanding etc..

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 Module 4 - Projects & Protocols
Project -3 AMBA Protocols (APB, AHB, AXI)
Implementation
APB Protocol: RTL Design and Verification using
SystemVerilog
AHB Protocol: RTL Design and UVM-Based Verification
AXI Protocol: Advanced RTL Design and UVM-Based
Verification
Developing Comprehensive Test Plans and Writing Test Cases
Debugging and Coverage Analysis for AMBA Protocols
Developing our own testcases & testplans

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 Module 4 - Projects & Protocols
3 Major Projects - Selective Projects

DMA Controller
Router
Digital Alarm, Traffic light controller
4 Port Calculator
RISC V Project
Advanced Protocols like PCIE | USB | Ethernet | DDR..

All Projects are implemented in RTL design & Verification using SV,
UVM

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 Module 5 - Advanced SV & UVM Lab Sessions

Deep into Object oriented programing Problem Statements

Advanced Coverage Analysis
Industry insights of Coverage driven verification
Assertion based verification Problem statements
SV Testbench creation for Various designs
Deep into Coverage & Assertions based verification
Development of Test plan, Test cases and Test suits
Verification Environment for a Protocol Design
Running regression suits & Debugging techniques

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 Module 5 - Advanced SV & UVM Lab Sessions
Deep into TLM Ports, Configuration database and all UVM
Concepts Lab sessions
More into developing RTL Design & Creating UVM Tb environment
for Adders, Memories, Registers
Developing Test plan, Test cases, Test suits
Deep into Coverage & Assertions in UVM testbench
Debugging techniques
Our own testcase development for Protocol designs & Creating
RAL models for Memories

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 Module 6 - SOC Design & Verification
Going to Design a Processor based SOC., which involves Memory
controller, DDR Memory and IO Peripherals
AXI Bus connection in a SOC Design
RTL Design of each block and verification of every block using
Systemverilog & UVM Methodology
Deep into Industrial approaches, Development of Linux
Environment and running regressions
Coverage & Assertion based Verification
SOC | IP level Verification techniques, writing C based testcases
Debugging Techniques, SOC
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 Module 6 - SOC Design & Verification
Deep into Running regressions
Development of configuring files, make file
SOC Level functionality verification using SV & UVM
Industrial Verification approach
Coverage bug analysis
Assertion based verification in UVM at SOC Level

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 Why ProV Logic ?

Structured
Course Tool Access Lab
Curriculum Sessions

Placement
Assistance

Best Live Sessions 1:1 Mentorship

Doubt discussions Mock Interviews Resume
guide
 Excellence in World class
VLSI Training & Placements

+91- 9182280927