ANALOG ELECTRONICS CIRCUITS LABORATORY

MANUAL
FOR
III SEM B.TECH. (ELECTRICAL & ELECTRONICS
ENGINEERING)

DEPARTMENT OF ELECTRICAL ENGINEERING

UNIVERSITY VISVESVARAYA COLLEGE OF
ENGINEERING
BENGALURU-01

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 1

Expt. Experiment Title Page
No. No.
COURSE OBJECTIVES & COURSE OUTCOMES
SCHEME OF EXAMINATION
1. (a) Clipping circuits using Diodes 03
(b) Clamping circuits using Diodes 05
2. Design and testing of Single stage RC coupled amplifier 07
3. Direct coupled amplifier 12
4. Transformer coupled amplifier 13
5. (a) Emitter follower 15
(b) Darlington Emitter follower
6. Differential amplifier 17
7. Tuned amplifier 20
Single tuned amplifier
8. Wein Bridge oscillator using BJT 25
9. (a) Transistor Hartley Oscillator 29
(b) Colpitt’s Oscillator 36
(c) Piezo crystal Oscillator 44
10. Diode FWR with and without capacitor filter 45
11. Series Voltage regulator 47
12.
13.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 2

 Expt.1: (a) CLIPPING CIRCUITS USING DIODES

Aim: To study basic clipping circuits and observe the output waveform.

Apparatus required: Two RPS (0-30V), Signal generator, Bread board, CRO with probes, Diode
(1N4007)-3 Nos., Resistance (1KΩ) – 2 Nos.

Circuit diagram:
Vin
R=1KΩ A Vm

1N4007 0
10Vp-p + V0 t
Signal ~
generator VR
Vin -Vm Clipping level
V0
VR+Vγ
VR t
0
Fig 1. Positive shunt clipper

-Vm

R=1KΩ A Vin
Vm
D
1N4007
10Vp-p 0
V0 t
Signal ~
generator VR
Vin -Vm V0
Vm

Fig 2. Negative shunt clipper 0 t

VR
-(VR+Vγ)

Vin
Vm
10KΩ

D1 D2 0 t
1N4007 1N4007
Vin V0
-Vm
10Vp-p ~ V0
Signal VR1 VR2 VR1+0.7
generator
0
t
Fig 3. Parallel clipper -( VR1+0.7)

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 3

Theory: Fig.1. shows the basic parallel positive clipper circuit with reference voltage VR. The
potential of node A is VR + 0.7 for the silicon diode. During the positive half-cycle of the input
voltage Vin as long as Vin < VA, the diode will not conduct. But when Vin=VA, the diode starts
conducting and the output voltage V0 = VA = VR + 0.7.When Vin < VA and throughout negative half
cycle the diode is reverse biased and acts as open circuit and hence V0 = Vin.
Fig.2. shows the basic parallel negative clipper circuit with reference voltage VR. The potential of
node A is –VR-0.7. During the positive half cycle, the diode is reverse biased and the diode D acts as
an open circuit. Hence V0 = Vin. When Vin<VA, then the diode becomes forward biased. Hence,
V0 = Va=-VR-0.7.
Fig.3. shows the circuit diagram of two way parallel clipper. Diode D1 turns on when the input
voltage exceeds VR1 +0.7, this is the positive clipping level. Similarly, diode D2 conducts when the
input is more negative than –VR2-0.7, this is the negative clipping level.
Procedure:
1. Check all the component using multimeter, before connecting the circuit.
2. Make the connections as shown in circuit diagram.
3. Apply input wave, usually a sine wave at 1KHz and amplitude of 10Vp-p to the circuit and
observe the clipped output waveform on CRO.
4. Note the reference voltages on the CRO.
5. Apply Vi and V0 to the X and Y channel of CRO and observe the transfer characteristic
waveform and verify it.
Tabular column:
Positive shunt clipper:
Vin Vp-p (V) VR VA

Negative shunt clipper:

Vin (V) VR VA

Parallel clipper:
Vin (V) VR1 VR2 VA VA
VR1+0.7 -(VR2+0.7)

Conclusion:
Clipping circuits can be used to clip off any unwanted portion of the waveform, without distorting
the remaining portion of the input waveform.
Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 4
Expt.1: (b) CLAMPING CIRCUITS USING DIODES

Aim: To study the different clamping circuits using diodes.

Apparatus required: RPS (0-30V), Signal generator, Bread board, connecting wires, Diode
(1N4007), Capacitor (0.01μF)

Circuit diagram:
0.01μF Vin
Vm
C

0 t
Vi ~ 1N4007 D V0
Signal
generator -Vm
V0
0.7
t
0
Fig.1. Negative Clamper
Negative
0.01μF clamping

C -(2Vm-0.7)

V0
Vi ~ 1N4007 D V0 2Vm-0.7
Signal Positive
generator clamping

0
Fig.2. Positive d.c. Clamper t
-0.7
Fig.3. Clamper waveforms

Theory: Fig.1. shows a negative clamper which adds a negative level to the a.c. output as shown in
Fig.3. During the first positive half cycle of the input voltage Vi the capacitor C gets charged through
forward biased diode D upto the maximum value Vm of the input signal Vi. The capacitor once
charged to Vm acts as a battery of voltage Vm. Thus when Vi=Vm, the output voltage V0 is zero. As
input voltage decreases after attaining its maximum value Vm, the capacitor remains charged to Vm
and the diode D becomes reverse biased. And the output voltage V0 is now given by V0=Vi-Vm. This
is as good as adding a negative d.c. level equal to –Vm to the output. In the negative half cycle of Vi,
the diode will remain reverse biased.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 5

Fig.2. shows a positive d.c clamper. On the first negative half cycle of input voltage Vi, the diode D
turns on. At the negative peak, the capacitor C must charge to Vm with the polarity shown. Slightly
beyond the negative peak, the diode D shuts off. The capacitor acts like a battery of Vm volts. This is
why the output voltage in Fig.3 is a positively clamped signal. Since the diode drops 0.7V when
conducting, the capacitor voltage does not quite reach Vm. For this reason, the d.c. clamping is not
perfect, and the negative peaks are at -0.7V (see Fig.3)

Procedure:
1. Make the connections as shown in the circuit diagram (Fig.1 and Fig.2).
2. Input sinusoidal signal of 1KHz frequency and amplitude of 10Vp-p may be applied.
3. The output is displayed on CRO. Compare the output and input waveforms.
Tabular column:
Negative clamping:
Input voltage Output voltage
Vi (V) –(2Vm-0.7) (V)

Positive clamping:
Input voltage Output voltage
Vi (V) (2Vm-0.7) (V)

Conclusion:
By implementing a capacitive and diode network, the d.c. level of an a.c. signal can be adjusted to a
required value in a clamping circuit.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 6

Expt. No.2 SINGLE STAGE RC COUPLED AMPLIFIER
+VCC =12V

R1 1KΩ RC CC
22KΩ V0
0.47μF 0.47μF
SL100

Vi ~
Signal R2 4KΩ RE CE=47μF
Generator 270Ω

Design:
VCC = 12V , hfe = 100
VCE = VCC / 2 = 6V
VRE = 10% of VCC = 1.2V
IE = IC = 5mA
RE = VRE /IE = 1.2 / 5mA = 240Ω Select RE = 270 Ω
VCC = VRC + VCE +VRE
12=VRC + 6 + 1.2
VRC =4.8V
RC = VRC /IC = 4.8/5Ma = 960 Ω Select RC = 1K Ω
R1 = VCC – VR2 / 10IB = 12-1.9 / 10x50μA = 20.4KΩ Select R1 = 22K Ω
IB = IC / β = 5mA / 100 = 50 μA
R2 = VR2 / 9IB = 1.9 / 9 x 50 μA = 4KΩ

f Hz V0 AV = V0 /Vi Gain = 20 logAV

Plot Gain V/s frequency

f1 f2

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 7

f1 = Lower cut off frequency
f2 = upper cut off frequency
Bandwidth = f2 – f1
Gain Bandwidth product GBW = Amid x BW
Aim: Design of a RC coupled single stage BJT amplifier and determination of gain frequency
response, input and output impedances
Apparatus required: Signal generator, bread board, CRO with probes, connecting wires,
Resistances: 22KΩ, 4KΩ, 1KΩ, 270Ω one each
Capacitors: 0.47μF-2 Nos., 47 μF – 1 No.
BJT: SL100 Transistor (NPN) – 1 No.
Design: For the design of RC coupled amplifier we assume following parameters that amplifier
should satisfy. VCC=12V, fL=500Hz, IC=5mA, S=10 and AV=40.
Step 1: Determine RE and RC
For an amplifier we choose operating point at the center of the DC load line. When operating point is
at the center of the DC load line VCE (active) is nearly equal to VCC / 2. To have sufficient negative
feedback and hence the stability. We assume VE = VCC / 10.
Therefore VCE = VCC /2= 12/2=6V and
VE = VCC/10 = 12/10 = 1.2V
RE = VE/IE ≈ VE/IC = 1.2/5x10-3 =240Ω
Applying KVL to output circuit we have,
VCC – IC RC –VCE –VE = 0
Therefore, RC = VCC – VCE – VE/ IC = 12-6-1.2 / 5X10-3 = 960Ω
Step 2: Determine R1 and R2
For RC coupled amplifier stability factor is given by

Since β>>1 we have,

Therefore, RB = 2.16KΩ
Looking at the circuit diagram we have,
VB = VBE + VE = 0.7+1.2 = 1.9V

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 8

The voltage VB can also be calculated by applying the voltage divider rule to base which is given by

Step 3: Determine input and output impedance

To find input impedance
DRB

~
Vi =10mV RC coupled V0
amplifier

Fig.2
Input impedance Zi = hie

For transistor BC 147B we have hie =4.5KΩ

To find output impedance

RC coupled
Vi ~ V0
amplifier

Step 4: Determine RL
For common emitter RC coupled amplifier the voltage gain using approximate analysis is given as,

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 9

The known quantities are AV and RC and we get hfe and hie from the data sheets of selected transistor.
Let us assume the transistor is BC147B. For BC147B, hfe = 240 and hie = 4.5KΩ.

RL = 3.428KΩ

Procedure:
1. Make connections as per the circuit diagram, shown in Fig.1.
2. Maintain the input signal Vi at a constant value of 10mV from the signal generator.
3.Vary the frequency in step (without changing Vi) and note down the corresponding output
voltages with the help of CRO.
4.Calculate the gain corresponding to different values of frequencies and corresponsing input and
output voltages.

5. Plot a graph of frequency verses gain and find the half power frequencies (3db) down of the
maximum.

To find input impedance

1. Make connections as shown in Fig.2.
2. Connect DRB (Decade Resistance Box) in series with input signal and observe the output
voltage at constant gain frequency say 1KHz.
3. Increase the resistance such that voltage across RL is exactly half of the value when
resistance is near to zero.
To find output impedance
1. Make connections as shown in Fig.3.
2. Connect DRB (Decade Resistance Box) across output of the circuit and observe voltage at
constant gain frequency say 1KHz.
3. Decrease the resistance such that output voltage is exactly half of the value when the
resistance is maximum.
4. Note down the resistance value from DRB which gives output impedance.

Tabular column:
Frequency (Hz) Output voltage in V Gain = V0/Vi Gain in dB 20log10(V0/Vi)
100
1K
10K
100K
500K
900K
1M

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 10

Nature of graph:
Voltage gain

Mid freqency region

AV(mid)

0.707AV(mid)

Bandwidth

0 f1 f2 Frequency

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 11

Exp. No.3 DIRECT COUPLED AMPLIFIER

Aim: To obtain the frequency response for a direct coupled amplifier.

+VCC =12V

820Ω RC2
22KΩ R1 1.5K RC1

P Q2
100KΩ

R3
1KΩ RE2
Vi ~
4.7KΩ R2 270Ω RE1

Design:
VCC = 12V , IC2 = IC1 = 4.5mA
VCE1 = VCE2 = VCC/3 = 4V
VRE1 = 1.2V
RE1 = VRE1 / IE1 = 1.2 / 4.5mA = 266.67Ω Select 270Ω
VRC1 = VRC1 / IC1 = 6.8 / 4.5mA = 1.511KΩ Select 1.5KΩ
IB1 = IC1 / hFE1 = 4.5 mA / 100 = 45μA
VR2 = VRE1 + VBE1 = 1.2 + 0.7 = 1.9V
R2 = VR2 / 9IB1 = 1.9 / 9 x 45μA = 4691Ω Select 4.7KΩ

Vp = VCC – VRC1 = 12-6.8 = 5.2V

VRE2 = VP – VBE2 = 5.2 – 0.7 = 4.5V
RE2 = VRE2 / IE2 = 4.5/4.5mA = 1KΩ
VRC2 = 12-VCE2 – VRE2 = 12-4-4.5 = 3.5V
RC2 = VRC2 /IC2 = 3.5 / 4.5mA = 777.77Ω Select 820Ω
Select R3 = 100KΩ

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 12

Expt. No.4 TRANSFORMER COUPLED AMPLIFIER
+VCC =12V

2:1

27KΩ R1 10KΩ RL V0

0.47μF

C1
Vi
~ 33KΩ R2
2.7KΩ RE CE

Fig. 1 Circuit Diagram of Transformer Coupled Amplifier

Design:
VCC = 12V , IC = 2 mA, hfe = 100
VCE = VCC / 2 = 6V
IB = IC / hfe = 2mA/100 = 20μA
VRE = VCC – VCE [DC drop across transformer = 0] = 12-6=6V
RE = VRE/IC = 6/2mA = 3KΩ Select RE = 2.7 KΩ
VR2 = VRE + VBE = 6 + 0.7 = 6.7V
R2 = VR2 / 9IB = 6.7/9 x 20μA = 37.2KΩ Select R2 = 33KΩ
R1 = VCC – VR2 / 10IB = 12 – 6.7 / 10 x 20μA = 26.5 KΩ Select R1 = 27KΩ
Transformer turns ratio = N1 / N2 = V1 / V2 = n
n2 RL = 1 / h0e
Assume 1 / h0e = 40KΩ
N = 2/1 =2
RL = 40KΩ / 4 = 10KΩ

The transformer used is a step down transformer with the turns ratio as 2:1. For the a.c. analysis, the
load on the secondary is the load resistance RL ohms. And the reflected load on the primary is RL’ =
n2RL. The a.c. power developed is on the primary side of the transformer. While calculating this
power, the primary values of voltage and current and reflected load RL’ must be considered. The a.c.
power delivered to the load is on the secondary side of the transformer. While calculating load
voltage, load current, load power the secondary voltage, current and the load RL must be considered.
Maximum possible theoretical efficiency in case of transformer coupled class A amplifier is 50%.
For practical circuit it is about 30 to 35%, which is still much more than the directly coupled
amplifier.
Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 13
The advantages of transformer coupled class A amplifier circuit are:
1. The impedance matching required for maximum power transfer is possible.
2. The efficiency of the operation is higher than directly coupled amplifier.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 14

 Expt. No.5 EMITTER-FOLLOWER

Aim: To experimentally obtain the input impedance (Zi) and output impedance (Z0) of an emitter
follower
+VCC

R1 27KΩ

Ci
0.47μF C0
V0
Vi ~ RL 39KΩ
signal
generator

Fig.1. Circuit diagram of Emitter Follower

Design:
VCC = 12V , IC = 2mA, β = 100
VCE = VCC / 2 = 6V
VRE = VRE / IE = VRE / IC = 6/2 = 3kΩ Select RE = 3.3kΩ
IB = IC / β = 2Ma / 100 = 20μa
VR2 = VBE + VRE = 0.7 + 6 = 6.7v
R2 =VR2/9IB = 6.7/9X20Μa = 37.2kΩ Select R2 = 39KΩ
R1 = VCC –VR2 / 10IB = 12-6.7 / 10X20Μa = 5.3/20μa = 26.5kΩ Select R1 = 27KΩ

To find Zi and Z0

10KΩ A
B
Vi Amplifier
~ V0
A’ B’

Increase the potentiometer till output voltage falls to half the previous reading.
V01 =VA V02 = VA/2
Now measure resistance of the potentiometer to get input impedance of the amplifier.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 15

Output impedance Z0
A B

IV Amplifier 10KΩ
~ V0 =VA =1V

A’ B’

Initially keep the potentiometer to maximum Decrease the potentiometer till output voltage becomes
half the previous value. Now measure resistance of the potentiometer to get output impedance.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 16

Expt. No.6 THE DIFFERENTIAL AMPLIFIER

+VCC

RC RC
_ +
Vout

V1 V2

RE

-VEE
Fig.1. Differential amplifier: Double-ended input
Double-ended output

Theory: Fig.1. shows the most general form of a differential amplifier (diff amp). It has two inputs
V1 and V2. Because of the direct coupling, the input signals can have frequencies all the way down
to zero, equivalent to d.c. The output voltage Vout is the voltage between the collectors. Ideally, the
circuit is symmetrical, with identical transistor and collector resistors. As a result, the output voltage
is zero when the two inputs are equal. When V1 is greater then V2, an output voltage with the
polarity shown appears. A diff amp amplifies the difference between the two input voltages,
producing an output of Vout = Ad(V1 –V2)
where Vout = voltage between collectors
Ad = RC / re’ is called the differential voltage gain

Common-Mode Gain (ACM)

A common-mode signal is one that drives both inputs of a diff amp equally. When a common-mode
signal drives a diff amp, a large unbypassed emitter resistance RE appears in the a.c. equivalent
circuit. Therefore, the voltage gain for a common-mode signal is
ACM = -RC / 2RE
where
ACM = common-mode voltage gain
RC = collector resistance
RE = emitter resistance

Common-Mode Rejection Ratio (CMRR)

Common-mode rejection ratio (CMRR) is defined as the ratio of differential voltage gain (Ad) to
common-mode voltage gain. In symbols,
CMRR=Ad /ACM

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 17

Expt. No.7 TUNED AMPLIFIER

+VCC

r
C
RB
L

+ V0 RL
VS
~
_
-

Fig.1. CE Tuned amplifier

Theory: Tuned amplifier is meant to amplify signal of a particular frequency. In order to reject other
frequencies a resonant circuit (LC in parallel is connected at the amplifier output, wherein capacitor
C of the circuit is adjustable so that the amplifier can be turned to various frequencies. The resonant
circuits gain (amplitude) vs frequency response is drawn in Fig.2.
|V0|/|VS|
AV0

AV0/√2
Q= 1/BW = Quality factor

W1 f0 W2
BW

Fig.2.

Voltage gain is maximum at resonant frequency (f0) and falls off sharply on either side of this
frequency. The fall in gain is governed by the quality factors (Q) of the circuit, higher the Q, higher

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 18

the circuit selectivity. As infinite Q is not possible in a practical circuit; so the circuit is designed to
have a narrow band of frequencies (BW).
BW=W2 –W1 = 1/RC
Quality factor is given as Q=W0 / BW = W0RC

Aim: To obtain frequency response of Tuned Amplifier and measure its bandwidth

Design: Same as transformer coupled amplifier

Assume L and find C.

+VCC =12V

L 25mH C 0.25μF
R1 22KΩ
CC V0
0.47μF

0.47μF

Vi ~ R2 33KΩ
signal RE CE
generator 3.3KΩ 47μF

Fig.3. Circuit diagram

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 19

Expt. No. 7
To realise a single tuned amplifier circuit and verify its working and frequency response

Apparatus:
VRPS (0-30V), CRO
Resistors, Capacitors
L-C bank circuit (DLB, DCB)
Transistor SL100

Procedure: +12VCC
Rr L
C 0.47μ
V0
Vi B
47μ
0.47μ
E

R2 RE

GND

1. Design a proper value of ‘R’ and ‘LC’ circuit assuming a frequency. The circuit is connected as
shown in the circuit diagram.
2. VCC is adjusted to 12 volts. The DC bias conditions are checked and varified.
3. The input is given from a variable frequency function generator / signal generator.
4. The frequency is increased in steps of 100 Hz from 0 to say 10MHz. Each time the output of the
amplifier is measured and readings are tabulated.
5. The frequency response plot is drawn on a semilog sheet.
6. It is noted that max gain (A≈1) is realised only at the designed frequency.

Design:
Part A: Amplifier design is same as in case of Hartley’s oscillator
“Please refer expt. No.13(a)
Exception: ‘RC’ is not included.

Part B: ‘L-C’ tuning circuit design

We know that for an L-C circuit the frequency of oscillation is given by

Choose the value of ‘f0’ and ‘C’ calculate ‘L’.

OR
Choose the value of ‘f0’ and ‘L’ calculate ‘C’

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 20

Tabular Column:
F (Hz) V0 (dB)

Specimen Graph:

A 0 dB line
(dB)

f0
f
log scale

Result:
The frequency response plot of the given tuned amplifier is as shown in the graph.
The frequency pertaining to max gain is ___________ KHz.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 21

OSCILLATORS
Oscillators are electronic circuits, which produce an output without an input signal. When a DC bias
is given to a circuit, it sets into oscillations resulting in an output signal. Basically, an oscillator
consists of an amplifier and a feedback network, which introduces positive feedback. The feedback
network consists of either RC or LC network.
Conditions for oscillations:
*The frequency of oscillation for an oscillator is the frequency at which the phase shift of the loop is
zero or even multiples of 2π.
*Oscillations will be sustained only if the loop gain is equal to unity.
The above two conditions are known as Barkhausen criterion and these are the condition to be
satisfied for sustained oscillations.
Condition in practical situation:
Since the circuit elements and devices are non-linear, the loop gain has to be slightly greater than
unity for having sustained oscillations.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 22

Expt. No.8 OSCILLATORS

In an oscillator the value of loop gain AB is greater than 1 when the power is first turned on. A small
starting voltage is applied to the input terminals and the output voltage builds up, as shwon in Fig. 1d.
After the output voltage reaches a desired level, the value of AB automatically decreases to 1 and the
output amplitude remains constant. Fig.1c.

x y

+ Vin Vout
ABVin ~ A A

B B

(a) (b)

(c) (d) (e)

Fig.1.(a) Positive feedback returns a voltage of ABVin to point x.

(b) Connecting points x and y.
(c) Oscillations die out.
(d) Oscillations increase
(e) Oscillations are fixed in amplitude

Fig.1.a shows a voltage source Vin driving the input terminals of an amplifier. The amplified output
voltage is Vout =AVin . This voltage drives a feedback circuit that is usually a resonant circuit.
Because of this, we get maximum feedback at one frrequency. The feedback voltage returning to
point x is given by
Vf = ABVin
If the phase shift through the amplifier and feedback circuit is 00 , then ABVin is in phase with the
signal Vin that drives the input terminals of the amplifier.
Suppose we connect point x to point y and simultaneously remove voltage source Vin. Then the
feedback voltage ABVin drives the input terminals of the amplifier, as shown in Fib. 1(b).
What happens to the output voltage?
If AB is less than 1, ABVin is less than Vin and the output signal will die out as shown in Fig.1(c). On
the other hand if AB is greater than 1, ABVin is greater than Vin and the output voltage builds up (Fig
1(d)). If AB equal 1, then ABVin equals Vin and the output voltage is a steady sine wave like Fig.1(e).
In this case, the circuit supplies its own input signal and produces a sine wave output.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 23

Expt. No.8 THE WEIN-BRIDGE OSCILLATOR

The Wein-bridge oscillator is the standard oscillator circuit for low to moderate frequencies, in the
range of 5Hz to about 1 MHz.

Lag Circuit R

Vin
Vin C Vout
~
f

Vout
Fig.8-1(a) Bypass capacitor (b) Phasor diagram

The voltage gain of the bypass circuit of Fif 8-1a is:

and the phase angle is:

Where ø is the phase angle between the output and the input. Notice the minus sign in this equation
for phase angle. It means that the output voltage lags the input voltage, as shown in Fig.8-1b.
Because of this, a bypass circuit is also called a lag circuit. In Fig. 8-1b, the half circle shows the
possible positions of the output phasor voltage. This implies that the output phasor Vout can lag the
input phasor Vin by an angle between 00 and -900.

Lead circuit

C Vout

f
Vin Vout
~ R
Vin

Fig.8-2(a) Coupling circuit (b) Phasor diagram

Fig.8-2a shows a coupling circuit. The voltage gain in this circuit is:

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 24

And the phase angle is:

Notice that the phase angle is positive. It means that the output voltage leads the input voltage, as
shown in Fig.8-2b. Because of this, a coupling circuit is also called a lead circuit. In Fib.8-2b, the
half circle shows the possible positions of the output phasor voltage. This implies that the output
phasor can lead the input phasor by an angle between 00 and +900.

Lead-Lag circuit
The Wien-bridge oscillator uses a resonant feedback circuit called a lead-lag circuit (Fig. 8-3)
B

R C 1/3

f
Vin R C Vout (a) fr

+900

00 f
fr
Fig8-3 Lead-Lag circuit
-900 (b)

Vout

Vin

(c)
Fig.8-4 (a) Voltage gain (b) phase response (c) phasor diagram
At very low frequencies, the series capacitor C appears open to the input signal and there is no
output signal (XC = 1/ωC).
At very high frequencies, the shunt capacitor C looks shorted (XC≈0) and there is no output. In
between these extremes, the output voltage reaches a maximum value (see Fig. 8-4a).

The frequency where the output is maximum is the resonant frequency fr. At this frequency, the
feedback fraction B reachers a maximum value of 1/3.
Fig.8.4b shows the phase angle ø of the output voltage Vout versus input voltage Vin. At very low
frequencies, the phase angle ø is positive (leading). At very high freqeuncies, the phase angle ø is
negative (lagging). At the resonant frequency fr, the phase shift is 00.
Fig. 8-4c shows the phasor diagram of the input Vin and output voltages Vout. The tip of the phasor
can lie anywhere on the dashed circle. Because of this, the phase angle ø may vary from +900 to -900.
The lead-lag circuit of Fig.8-3 acts like a resonant circuit. At the resonant freqeuncy fr, the feedback
fraction B reaches a maximum value of 1/3, and the phase angle equals 00. Above and below the
resonant frequency fr, the feedback fraction B is less than 1/3, and the phase angle no longer equals
00.
Formula for Resonant Frequency

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 25

By analyzing Fig8-3 with complex numbers, we can derive these two equations:

and

Graphing these equations (1) and (2) produces Fig 8-4a and b. The feedback fraction B given by
Eq.(1) has a maximum value at the resonant frequency. At this frequency,
XC = R

Solving for fr gives:

Aim: To Design and Construct a Wien-Bridge oscillator for a given cut-off frequency
+VCC

R1 RC1 R3 RC2

+ -
Ci CC2
+ - + - Q2
Q1 CC
R2 R4 +
RE2 _ CE2

R R5 10KΩ
C

R
C R6 (DRB)

Fig.8-5 Circuit diagram

Design: Given VCC=12V, fr =2KHz; Stability factor S=10 Lower cut off frequency fL=50Hz; IC1=
IC2=1mA
Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 26
When the Wien bridge is balance,

Assume, C=0.1μF ; Find R

Given data: AVr=3, AV1=2, AV2=1

Gain formula is given by,

Effective load resistance is given by, RLeff = RC2 | | RL2

hfe1 and hfe2 from transistor data manual
hfe2 = 200 (from multimeter)
Emitter resistance is given by,

where re2 is the internal resistance of the transistor Q2.

hie2 = hfe2 x re2 = 200 x 26 = 5.2KΩ
From d.c bias analaysis, on applying KVL to the output loop, we get
VCC = IC2 RC2 + VCE2 +VE2
Assume VCE2 = VCC / 2 ; VE2 = VCC /10 ; IC2=1Ma ; Find RC2
Since IB is very small when compared with IC , IC ≈ IE

Find RC2 | | RL2 from the above equation. Since RC2 is known, calculate RL2
VE2 = iE2 rE2 Calculate RE2

Find RB2
RB2 = R3 | | R4

VB2 = VBE2 + VE2

Let VBE2 =0.7V Find R3 = ? Therefore, find R4 =
Zi2 = hie2 | | RE2 Find Zi2 = ?
Effective load resistance for transistor Q1 , RLeff1=Zi2 | | RC1
Find RLeff1 from the gain formula given by

On applying KVL to the first stage, we get

VCC =IC1RC1 + VCE1 + VE1; Assume VCE1 = VCC/2 ; VE1 = VCC/10
Find RC1= ?
Since IC1 ≈ IE1 ; Find RE = RE1 = VE1 / IE1 = ?

Find RB1 = ?
RB1 = R1 | | R2

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 27

VB1 = VBE1 + VE1

Let VBE1 =0.7V Find R1 = ? Therefore, find R2 =

Zi1 = hie1 | | RB1
R5 = RL2 – R6

Apparatus required: DC Power supply (0-30)V – 1 No. ; CRO with probes; Bread board and
connecting wires, BJT: SL100 Transistor (NPN) – 2 Nos.

Resistances: R1 = ,R2= , R3 = , R4= , R5=

RC1= , RC2= , RE2=

Capacitors: Ci =
CC2 = CC2 =
CE2 =

Procedure:
1. Rig up the circuit as per the circuit diagram.
2. Switch on the power supply and observe the output on the CRO (sine wave).
3. Note down the practical frequency and compare it with its theoretical frequency fr.

Result:
Theoretical Practical
Frequency

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 28

Exp. No. 9(a) TRANSISTOR HARTLEY OSCILLATOR

+VCC = +12V
RF CHOKE
22KΩ R1 RC 1KΩ

0.47μF
100μH
L1 RL = 6.8KΩ
0.47μF C=1800pF

4.7KΩ R2 270Ω R3 47μF

100μH L2

Fig 5 (a) Hartley oscillator circuit

Theory: When the LC tank is resonant, the circulating current flows through L1 in series with L2 .
So the equivalent L to use in Eq.

[Note: Most LC oscillators use tank circuits with a Q greater than 10. Because of this, we can
calculate the approximate resonant frequency as above]
is L = L1+ L2 ----------- (2)
In a Hartley oscillator, the feedback voltage is developed by the inductive voltage divider, L1 and L2.
Since the output voltage appears across L1 and the feedback voltage across L2, the feedback fraction
is
---------(3)
As usual, this ignores the loading effects of the base. For oscillations to start, the voltage gain must
be greater than 1/B.
Often, a Hartley oscillator uses a single tapped inductor instead of two separate inductors. The action
is basically the same either way.
Given fr = 100KHz
Design: Same as RC coupled amplifier

L1 and L2 = 100μH or 1mH

C=1800pF

Procedure:
1. Circuit connections are made as shown in the circuit diagram.
2. Check the dc biasing. For VCC =12V, VCE = 6V.
3. Now connect the feedback circuit and switch on the d.c. power supply.
4. Observe the output voltage V0 for various values of VCC AND RL.
5. Plot the graph of V0 v/s VCC and V0 v/s RL.
V0 V0
Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 29
 VCC RL
Aim: To determine the frequency of oscillations of Hartley oscillator

Apparatus required:
VRPS: (0-30V) DC; CRO with probes, Bread board, Transistor SL100
Decade boxes: Decade inductance box (DLB). Resistors: 22KΩ, 4.7KΩ, 1KΩ, 270Ω, 1KΩ
Potentiometer. Capacitors: 0.47μF, 4.7μF, Decade Capacitance Box (DCB)

Circuit diagram:
+VCC=12V

R1 = 22KΩ RC =1KΩ
V0
CC=0.47μF

CC BJT

R2 =4.7KΩ 1K pot

270Ω RE CE = 47μF

L1 L2

Design: The Hartley oscillator is also a LC oscillator which uses two inductive reactances and one
capacitive reactance in its feedback network. The practical circuit is shown in Figure.
The resistances R1, R2 and RC are biasing resistances. RE and CE are bypass resistance and capacitor
CC are the coupling capacitors.
The frequency of oscillations are given by

The BJT amplifier (CE mode) stage provides 1800 phase shift while the tank circuit adds further
1800 phase shift to satisfy 3600 phase shift as per Barknausen criteria.
Amplifier design:
Transistor SL100
Assume VCC=12V, IC=4.5mA, β=100
RE: ? VRE = VCC/10 = 12/10 = 1.2V

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 30

IE≈IC = 4.5mA

Select RE = 270Ω

Determine RC
Applying KVL to the loop consisting of VCC, Collector, Emitter and RE as a dc analysis we have
VCC-ICRC-VCE-VRE=0
For an amplifier we choose operating point at the centre of the DC load line. So
VCE = VCC/2 = L2/2=6V

Select RC = 1KΩ

Determine R1 and R2
Looking at the circuit diagram we have
VB+ VBE +VRE = 0.7 + 1.2 = 1.9V
IB =IC/β =4.5mA/100 = 0.045mA
Let 10IB flow through R1 which means current through R2 is 10IB – IB = 9IB

Select 4.7KΩ

Select R1 = 22KΩ

‘TANK CIRCUIT DESIGN:

For Hartley oscillator, frequency of oscillation is given by

Choose a particular frequency and value of capacitor C say ‘200KHz’ (This is either specified or
assumed)
Let us assume ‘C’ value as 0.01μF

Choose L1 say 30μH and L2 = 33μH. This depends on the availability of values of L on the decade.
Inductance box (DLB)
Normally L2 ≈ 2L1 . But this is not a rule. Measure Fp (Practical) on the CRO.

Procedure:
1. Rig up the circuit without the coupling and bypass capacitors (CC and CE) and check the D.C
bias.
2. Using Digital Multimeter (DMM) measure the DC voltages VCC, VCE, BBE, VE.
3. Note the operating point (VCE , IC) wotj VCC=12V/ IC is given by

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 31

 4. The 1K potentiometer is adjusted to get a stable output on the CRO.
5. Connect the complete Hartley circuit and measure the frequency of oscillation on the CRO
and compare with the theoretical value.
6. Vary the supply VCC in steps of 1 volt and note down the output voltage on the CRO. Take
care while increasing VCC transistor may go to cutoff or while decreasing VCC transistor may
go to saturation.
7. A decade resistance box is connected as Load Resistance RL at the output point (other
terminal of RL is ground).
8. The DRB is varied and the output voltage amplitude is noted. A graph of load voltage vs load
resistance RL is plotted.

Tabular column:
VCC (V)
V0 (V)

V0 (V)
RL (KΩ)

Result: The performance characteristics of the designed Hartley’s oscillator is shown in the graph
enclosed.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 32

HARTLEY OSCILLATOR

Aim: To design & verify the performance of a ‘HARTLEY’ OSCILLATOR

Apparatus:
VRPS: (0-30V) DC, CRO, Resistors, Capacitors, Inductors (decade boxes) (DCB, DRB,DLB),
Transistor (SL-100)

Procedure:
+VCC

RC
R1 0.47μ
V0
C
B

E
47μ
1K pot

R2
RE
GND

0.47μ

L1 L2

GND

1. The suitable design calculations are done and the connections are made as shown in the diagram.
The DC conditions are checked (i.e., the DC voltages at ‘B’, ‘E’, & ‘C’ of the transistor are
measured). The operating point (VCE, IC) is noted and varified, with VCC=12 volts.
VCE=VC-VE , IC=VCC-VE/RC
2. The 1K ‘pot’ is adjusted to get a stable output on the ‘CRO’.
3. The frequency of oscillation is measured on the CRO and compared with the theoritical value.
4. The supply VCC is varied in steps ( or ) (care should be taken while ing or ing as the
transistor may go to cut off (due to ) or saturation (due to ing) regions) and the corresponding
output is noted on the ‘CRO’. A graph of VCC vs output is plotted of load voltage vs load (RL) is
plotted.
5. A load resistance (DRB) is connected to the output terminal (other terminal is ground). The DRB
is varied and in each step the output (amplitude) is noted. A graph of load voltage vs load (RL) is
plotted.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 33

 VCC (υ) V0 (υ) V0 (υ) RL (KΩ)

Specimen Graph:

υ0 υ0

0 VCC 0 RL

Design calculations:
Part 1: Amplifier design
VCC = 12V, IC = 4.5 mA , β=100 (SL 100)
RE: VRE = VCC/10=1.2V
RE=1.2/IE AS IE ≈ IC ; RE = 1.2/IC= 1.2V/4.5mA=267Ω
Choose RE = 270Ω
RC = VCE= VCC/2 = 6V
By KVL (C-E loop) : VCC-ICRC-VCE –VRE=0

Choose RC=1K
R1 & R2:
By KVL (C-B loop) : VB = VBE + VRE = 0.7+1.2= 1.9V
IB=IC/β = 0.045mA
Let 10IB flow through ‘R1’

Choose R1 =22K
R2:

Choose R2 =4.7K

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 34

Part 2: ‘TANK’ circuit design
The combination of R,L & C elements are called as ‘TANK’ circuit.

For HARTLEY’s Oscillator:

Freqeuency of oscillation ‘F’ is given by

Choose a particular frequency and value of capacitor ‘C’

Say ‘200KHz’ (This is either specified or assumed) and ‘C’ value sya 0.01μF

Choose L1 say 3mH and L2 say 4mH

This depends on the availability of values of ‘L’ on the decade inductance box (DLB)
Normally ‘L2 ≈ 2L
This is not a rule
So, ftheoritical =20KHz
Fpractical = 1/T (measured on the CRO)

Result: The practical value of the frequency of the given Hartley’s oscillator is _____ KHz.
The performance characteristics of the designed Hartley’s oscillator is as shown in the graph.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 35

Expt. No. 9 (b) COLPITT’S OSCILLATOR
Aim: To design and verify the performance characteristics of a given ‘COLPITT’S OSCILLATOR’

Apparatus:
VRPS: (0-30V) DC, CRO with probes, Bread board, connecting wires, Capacitors: 0.47μF (2 Nos.),
Transistor SL100
Decade Boxes: Decade Capacitance Box (DCB)
Resistors: 22KΩ, 4.7KΩ., 1KΩ, 270Ω, 1KΩ Potentiometer, 10KΩ Potentiometer

Circuit diagram:
+VCC =12V

22KΩ R1 1KΩ RC 0.47μF

C V0
0.47μF CC
B
CC
E
4.7KΩ R2 1KΩ pot

270Ω RE CE

C1 C2

L
Procedure: Same as in Hartley’s oscillator. Please refer expt. No. 9(a)

Design: Amplifier circuit design same as in 9(a)

Tank circuit design

We know that for a given Colpitt’s oscillator the frequency of oscillation f is given by

Choose a value of ‘L’ and ‘f’

Note: Value of ‘L’ is subject to availability on the DLB. Then find the value of ‘CT’
Choose C1 = C2 = C [Note: This is not a rule. It is taken for convenience]
Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 36
Alternate method:
Choose ‘C’ find CT=C/2
Then choose’f’ and calculate ‘L’ using

ftheoretical = _________ KHz

fpractical = __________ KHz

f0 = 100KHz

Circuit diagram:
+VCC =12V

22KΩ R1 1KΩ RC 0.47μF

C V0
0.47μF CC
SL100
CC Rl =10K pot

4.7KΩ R2 1KΩ pot

270Ω RE CE 47μF

0.1μF 0.1μF

C1 C2

L 0.05mH
VCC V0 RL V0

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 37

 V0 V0

VCC RL

Theory: Figure shows a Colpitt’s oscillator. The voltage-divider bias sets up a quiescent operating
point. Because the base and collector lag networks, the high frequency voltage gain is less than RC/re’.
The circulating or loop current in the tank flows through C1 in series with C2. Notice that υout equal
the ac voltage across C2. Also, the feedback voltage υf appears across C1. This feedback voltage
drives the base and sustains the oscillations developed across the tank circuit, provided there is
enough voltage gain at the oscillation frequency. Since the emitter is at ac ground, the circuit is a CE
connection. In the Colpitt’s tank circuit, the circulating current flows through C1 in series with C2.
Therefore the equivalent capacitance is

We can calculate the approximate resonant frequency as

Result: The graph of V0vs VCC is as shown.

The frequency of oscillation of the designed Colpitt’s oscillator is frealised = _______ KHz.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 38

Expt. No. 9(b)
Aim: To design and verify the performance characteristics of a given ‘COLPITT’S OSCILLATOR’

Apparatus:
Same as in Hartley’s oscillator excepting in DCB and DLB

Procedure: +12VCC

R1 RC
0.47μ
C
V0
B
E
1K pot

R2
RE
C1 C2

0.47μ
L

1. Procedure is same as in Hartley’s Oscillator.

*Please refer Expt. No. 9(a)

Design:
PART A: Amplifier circuit design
*Same as in Hartley’s oscillator

PART B: ‘TANK’ circuit design

We know that for a given Colpitt’s oscillator the frequency of oscillation
f is given by

Choose a value of ‘L’ and ‘f’

(against value of ‘L’ is subject to availability of ‘L’ on the DLB)
Then find out value of ‘CT’
Choose C1 = C2 = C
Again this is not a rule only taken for convinience
Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 39
Or

Aliter:
Choose ‘C’ i.e., calculae C1 and C2 (as C1 = C2) choose ‘f’ and calculate ‘L’.
Ftheoritical : ___________ KHz
fpractical : ____________ KHz

Result: The graph of V0 vs VCC is as shown.

The frequency of oscillation of the designed Colpitt’s oscillator is fthe = __________ KHz.
frealised (practical)= _______________ KHz

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 40

Expt. No. 9(c) CRYSTAL OSCILLATOR
Select 1MHz or 2MHz crystal and output frequency

Circuit diagram:
+VCC =12V

22KΩ R1 XTAL 820Ω RC 0.47μF

C V0
CC
0.01μF
B
RL 10K pot
E
4.7KΩ R2 1KΩ pot

270Ω RE CE 47μF

Plot the graphs

VCC V0 RL V0

Theory:
When accuracy and stability of the oscillation frequency are important, a quartz-crystal oscillator is
used. The crystal (abbreviated XTAL) acts like a large inductor in series with a small capacitor.
Because of this, the resonant frequency is almost totally unaffected by transistor and stray
capacitances.
Some crystals found in nature exhibit the piezoelectric effect; when you apply an ac voltage across
them, they vibrate at the frequency of the applied voltage. Conversely, if you mechanically force
them to vibrate, they generate an ac voltage. The main substances that produce this piezoelectric
effect are quartz. Rochelle salts, and tour maline. Quartz is widely used for RF oscillators.

Apparatus required:
VRPS: (0-30V) DC, CRO with probes, Bread board, Connecting wires, Transistor (SL 100) Crystal-
2MHz, Resistors:22KΩ, 4.7KΩ, 820Ω, 270Ω, 1K pot, 10K pot, Capacitor: 0.47μF (2 Nos.);
0.01μF.

Procedure:
1. Connections are made as shown in the circuit diagram.
2. The DC bias conditions are checked as in case of Amplifier design experiment. The Q point
is determined.
3. The 1K- pot is adjusted to get a stable output on the CRO.

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 41

 4. The frequency of oscillation (fpractical) is measured on the CRO and compared with the
‘crystal’ frequency (i.e., 2MHz).
5. VCC is varied from 12 ± 4V (8,9,10,11,12,13,14V) and in each step the output is noted.
6. A graph of V0 vs VCC is drawn.

Tabular Column
Sl.No. VCC (V) V0
1 8
2 9
3 10
4 11
5 12
6 13
7 14

Result: The graph of V0 vs VCC is as shown.

The crystal frequency fpractical = ________ MHz

Specimen Graph:

V0

0 VCC

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 42

9 (c) Name: To realise a Crystal oscillator circuit

Apparatus:
Power supply (0-30V DC), CRO, Resistors, Capacitors, ‘Pots’, Transistor (SL 100), Crystal-2MHz

Procedure:
+12VCC
RC
R1 0.47μ
V0
Transistor SL100 C
B
E

1K pot
Crystal oscillator
R2
RE
GND

1. Connections are made as shown in the circuit diagram.

2. The DC conditions are checked as in case of Amplifier design experiment. The Q point is
determined.
3. The 1K- pot is adjusted to get a stable output on the CRO.
4. The frequency of oscillation (fpractical) is measured on the CRO and compared with the ‘crystal’
frequency (i.e., 2MHz).
5. VCC is varied and in each step the output is noted.
6. A graph of V0 vs VCC is drawn.

Tabular column:
V0 (V) VCC (V)

Specimen Graph:
V0

0 VCC

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 43

Design:
Amplifier Design same as in Hartley’s oscillator
Refer Expt. (a)

Ftheoritical = Fcrystal = 2MHz

Frealised (practical) = _______ MHz

Result: The graph of V0 vs VCC is as shown as in the graph.

The crystal frequency ftheoritical = 20 x 10-1 MHz fpractical = ________ MHz

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 44

Expt. No. 10 Diode rectifier with and without capacitor filter

Aim: To determine ripple factor of full wave rectifier ‘C’ filter using centre tap transformer. Also to
draw a graph of Idc vs VDC , Idc vs r , Idc vs rL and Idc vs regulation

Circuit diagram:
0-200mA
1N4001 + -
A
15V 470μF
D1 65V C Idc 100Ω +
0V
240V50Hz 5W V 0-30V CRO
15V D2 DRB RL

1N4001

Apparatus required:
1. Centre-tap-transformer 240V/15V-0-15V – 1 No.
2. Diodes BY127 or 1N4001 – 2 Nos.
3. Resistor 100Ω /5W – 1 No.
4. Capacitor (Electrolytic) 470μF/65V – 1 No.
5. Decade resistance box (DRB) - 1 No.
6. Connecting wires

Theory: This full-wave rectifier uses 2 diodes D1 and D2. A centre-tapped secondary winding is
used with 2 diodes connected so that each uses on half cycle of input ac voltage. The most
commonly used filter circuits are capacitor filter. Capacitor C is placed across the rectifier output in
parallel with load RL.
The ratio of r.m.s value of ac component to the dc component in the rectifier output is known as
ripple factor.

Design:
Choose a ripple factor of <0.01 , Let Vdc =14V, Icmax=100mA, RLmin = Vdc /ILmax = 14V/100x10-3 =
140Ω.

C= 484.9μF or 470μF/65V

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 45

Procedure:
1. Wire up the circuit as shown in the circuit diagram.
2. Switch on the mains supply to the transformer.
3. Note down the output voltage in no-load condition.
4. Connect the load parallel to capacitor and note down the reading of load current, ripple
voltage (vr), and output voltage in load condition.
5. Repeat the experiment for different load values.
6. Plot the graphs Idc vs Vdc , Idc vs r, Idc vs η and Idc vs Regulation.

Tabular column:

RL (Ω) Vr V Idc mA Vdc Vdc VRMS = η% %Reg r pract r theory

N.L F.L. Vr /2√3
V

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 46

Expt. No. 11 SERIES VOLTAGE REGULATOR

Aim: To design a series voltage regulator circuit and (i) to determine the line regulation and to plot
the characteristics of V0 vs Vin.
(ii) to determine load regulation and to plot the characteristics of V0 vs IL.
(iii) to calculate the resistance and stability factor SV.

Circuit diagram: (0-100mA)

SL100 + - IL
+ A

1KΩ
Vi 22KΩ pot +
(15±5V) V (0-15V)
VZ = 12V -

-
(without feedback)

(0-100mA)
SL100 + - IL
+ A

15KΩ RD 680Ω 150Ω

Vi 220Ω
(15±5V) 1KΩ
SL100 V (0-25V)

1KΩ
820Ω
VZ=7.5V

-
(with feedback)

Apparatus required:
1) Zener diode – 1 No.
2) NPN transistor –SL100 – 2 Nos.
3) Ammeter (DC) 0-100mA – 1 No.
4) Voltmeter (DC) 0-25V – 1 No.
5) Resistors 100Ω, 150Ω, 680Ω, 820Ω, 1KΩ, 1.5KΩ
6) Potentiometer 1KΩ - 1 No.

Theory: A simple voltage regulator circuit is as shown in the circuit diagram. Transistor is the series
control element and zener diode VZ provides the reference voltage. If the output voltage decreases,
the increased base-emitter voltage causes transistor to conduct more, thereby raising the output

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 47

voltage maintaining the output constant, If the output voltage increases, the decreased base-emitter
voltage causes transistor to conduct less,thereby reducing the output voltage.

Design: For voltage regulator with feedback

Choose a zener diode with a breakdown voltage = V0/2

To calculate R1 and R2
Assume hfe1 = hfe2 =100

Transistor Q1 will have emitter current IE1 = IL+I1 +ID.

Current through resistor R3 is I3 = IB1 + IC2 = 1.15+5 =6.15mA

R3 corresponding to Vi = 17V and IL = 100mA

Procedure:
1. The series voltage regulator circuit without feedback is rigged up as shown in the circuit
diagram.
2. Vary the input voltage and note down the output voltage V0.
3. Adjust the potentiometers to vary the load current IL and note down V0 for different values of IL.
4. Plot the characteristics of V0 vs Vi and IL vs V0..
5. From the graph calculate the stability factor

and output resistance

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 48

6. The connections with feedback are made as shown in circuit diagram (2) and the above
procedure is repeated.

Result: Variation of output voltage with input voltage and load current are plotted as shown in the
graph. R0 = ________ SV = ________

Analog Electronics Circuits Manual III Sem B.Tech. (EEE) Page 49