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Modified DLD Awneet Final

The document describes the implementation of a 2-to-4 decoder and a 1-bit ALU using VHDL. The decoder outputs a specific binary value based on the input and enable signal, while the ALU performs various operations (addition, subtraction, AND, OR) based on control signals. The architecture includes instantiation of the decoder within the ALU to handle different operations and produce the appropriate outputs.

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aryan090920
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17 views3 pages

Modified DLD Awneet Final

The document describes the implementation of a 2-to-4 decoder and a 1-bit ALU using VHDL. The decoder outputs a specific binary value based on the input and enable signal, while the ALU performs various operations (addition, subtraction, AND, OR) based on control signals. The architecture includes instantiation of the decoder within the ALU to handle different operations and produce the appropriate outputs.

Uploaded by

aryan090920
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Awneet(2341011150)

Decoder
library ieee;

use ieee.std_logic_1164.all;

entity decoder_2to4 is

port ( enable : in std_logic; input : in std_logic_vector(1 downto 0);

output : out std_logic_vector(0 to 3) );

end entity decoder_2to4;

architecture dataflow of decoder_2to4 is

begin

output <= "1000" when enable = '1' and input = "00" else

"0100" when enable = '1' and input = "01" else

"0010" when enable = '1' and input = "10" else

"0001" when enable = '1' and input = "11" else

"0000";

end dataflow;

ALU
library ieee;

use ieee.std_logic_1164.all;

entity alu_1bit is

port (

control : in std_logic_vector(1 downto 0);

A : in std_logic;

B : in std_logic;

O1 : out std_logic;
O0 : out std_logic

);

end entity alu_1bit;

architecture dataflow of alu_1bit is

component decoder_2to4 is

port ( enable : in std_logic;

input : in std_logic_vector(1 downto 0);

output : out std_logic_vector(0 to 3));

end component;

-- Signals for decoder outputs

SIGNAL INPUT_DEC: STD_LOGIC_VECTOR(1 DOWNTO 0);

signal control_decoder_out : std_logic_vector(0 to 3);

signal add_decoder_out : std_logic_vector(0 to 3);

signal sub_decoder_out : std_logic_vector(0 to 3);

signal and_decoder_out : std_logic_vector(0 to 3);

signal or_decoder_out : std_logic_vector(0 to 3);

begin

INPUT_DEC<= (A&B);

-- Instantiate the control decoder

control_decoder: decoder_2to4 port map (input => control,enable => '1',output =>
control_decoder_out);

-- Instantiate the decoders for each operation output

add_decoder: decoder_2to4 port map(input =>INPUT_DEC, enable =>


control_decoder_out(0),output => add_decoder_out);

sub_decoder: decoder_2to4 port map (input => INPUT_DEC,enable => control_decoder_out(1),


output => sub_decoder_out);-- Enabled when control = "01" (Subtraction)

and_decoder: decoder_2to4 port map ( input => INPUT_DEC, enable =>


control_decoder_out(2),output => and_decoder_out); -- Enabled when control = "10" (Logical AND)

or_decoder: decoder_2to4 port map ( input => INPUT_DEC, enable => control_decoder_out(3),
output => or_decoder_out); -- Enabled when control = "11" (Logical OR)
-- Assign the outputs directly from the operation decoders

O1 <= add_decoder_out(3) or sub_decoder_out(1); -- Carry or Borrow

O0 <= add_decoder_out(1) or add_decoder_out(2) or -- Addition Sum

sub_decoder_out(1) or sub_decoder_out(2) or -- Subtraction Difference

and_decoder_out(3) or -- AND Result

or_decoder_out(1) or or_decoder_out(2) or or_decoder_out(3); -- OR Result

end dataflow;

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