Control Loop Cookbook

Lloyd H. Dixon

INTRODUCTION: KEA(S) Error amplifier with compensation

Switching power supplies use closed-loop KMOD Pulse width modulator
feedback to achieve design objectives for line and
load regulation and dynamic response. KPWR Power switching topology
Fortunately, the closed-loop systems used in KLC(S) Output power filter
switching power supplies are usually not very com-
plicated, permitting the use of simple analytical KFB Feedback
techniques to achieve loop stabilization. A simpli- Although the pulse width modulator and power
fied version of the Nyquist stability criteria can be switching circuit are really not linear elements, their
used because unity gain crossover occurs only state-space averaged linear equivalents can
once in the gain vs. frequency characteristic. Bode be used at frequencies below the switching
plots provide a simple and powerful method of dis- frequency, fS.
playing and calculating the loop gain parameters Open-loop and closed-loop gain:
(see Appendix B). This paper begins with a quick The open-loop gain, T, is defined as the total
review of basic control loop theory. gain around the entire feedback loop (whether the
Linear Control Loop Theory loop is actually open, for purpose of measurement,
As shown in Figure 1, a power supply feedback or closed, in normal operation).
loop can be described in terms of small-signal lin-
T(s) = KEA • KMOD • KPWR • KLC • KFB (1)
ear equivalent gain blocks. The (s) appended to
certain gain blocks indicates that the gain varies as Closed-loop gain, G, defines the output vs.
a function of frequency. control input relationship, with the loop closed:

Figure 1. - Feedback Loop

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 1 T “Gain” elements as shown in Figure 1 need not
G(s) = (2)
KFB 1 + T have the same units for their output and input
(such as Volts/Volt). If Fig. 1 is a current mode con-
At low frequencies, open-loop gain T is nor- trol loop, “Output” is a current source, and KFB is
mally very much greater than 1, so that closed-loop most likely a current sense resistor. KFB “gain” is
gain G approaches the ideal 1/KFB. At higher fre- then expressed in Volts/Amp, and closed loop gain
quencies, T diminishes, mostly because of the G(s) is actually a transconductance (Amps/Volt).
low-pass filter characteristic KLC(S). The frequency Pulse width modulator KMOD has its gain
where T has diminished to 1 (0dB) is defined as the expressed as d/V (Duty cycle/Volt). This discrep-
crossover frequency, fC. Referring to Eq. 2 and ancy in “gain” units is resolved in the next gain
Figure 2, at fC (where T = 1, with associated 90° block, KPWR, whose characteristic is V/d.
phase lag), the closed-loop gain G(s) is 3db down Overall open-loop gain T(s) determines how
(with 45° phase lag). Thus, the open-loop cross- much output error results from a disturbance intro-
over frequency is also the closed-loop “corner duced at any point in the loop compared to the result
frequency”, where G(s) rolls off. if the loop was open. Project the disturbance forward
In a power supply voltage control loop, G(s) to the output (multiply by the gain between the dis-
defines the power supply output vs. the reference turbance and the output), then divide by total
voltage. KFB is usually a simple voltage divider. For open-loop gain, T. For example, with no feedback
example, if VREF is 2.5 V, a 2:1 divider (KFB = 0.5, G (open loop, constant duty cycle), a 10% change in
= 2) results in VOUT = 5 Volts. (Refer to Appendix A.) VIN results in a 10% VOUT change. With the feed-
In a two-loop system (as with current-mode back loop closed, if T is 100 at the frequency of the
control, to be discussed later) the closed-loop gain disturbance (DC in this example), then the VOUT
G(s) of the inner loop is one element of the open- change is only 0.1% (10%/100). Note that the
loop gain T(s) of the outer loop. Output accuracy does not depend significantly on
open-loop gain accuracy. In the example above, if T
was 80 instead of 100, VOUT would change by
0.125% (10% ³VIN/80), instead of 0.1%. However,
output accuracy does depend directly on the accu-
racy of the feedback portion of the control loop, KFB.
Alternatively, a disturbance can be projected
back to the summing point at the input of the error
amplifier. For example, the 1Volt “valley” voltage of
the sawtooth ramp applied to the PWM compara-
tor is effectively a 1Volt DC offset or “disturbance”.
If the E/A gain is 1000, this 1V error is equivalent
to a 1mV error in the reference voltage, and trans-
lates into the same percentage error at the output.
Nyquist Stability Criteria:
Referring to Figure 2, if the open-loop gain T
crosses 1 (0 dB) only once, the system is stable if
the phase lag at the crossover frequency, fC, is less
than 180° (in addition to the normal 180° phase
shift associated with any negative feedback sys-
tem). Let us define the term “phase lag” to refer to
any additional amount of phase lag beyond the
Figure 2. - Open & Closed Loop Gain 180° inherent with negative feedback. If the (addi-

Control Loop Cookbook 5-2

tional) phase lag at fC exceeds 180°, the loop will bounds, such as when a large step load change
oscillate at frequency fC. occurs. The system will then oscillate and probably
The “phase margin” is the amount by which the never recover. So it is not a good practice to
phase lag at fC is less than the critical value of depend upon a conditionally stable loop.
180°. The ‘gain margin’ is the factor by which the How can the loop be stable with 180° phase
gain is less than unity (0 dB) at the frequency lag and gain much greater than 1 ??
where the phase lag reaches 180°. If the phase lag Figure 3 shows the summing point voltage
at fC is only a few degrees less than 180° (small vectors at a frequency where the open loop gain is
phase margin), the system will be stable, but will 10, for three different amounts of phase lag around
exhibit considerable overshoot and ringing at fre- the loop.
quency fC. A phase margin of 45° provides for Figure 3a shows the vector relationship with
good response with a little overshoot, but no zero additional phase lag. This condition usually
ringing. occurs at low frequencies where there are no
Note that Nyquist’s 180° phase limit applies active poles, so that the gain characteristic slope is
only at fC. At frequencies below fC, the phase lag zero (flat). The feedback voltage vFB is 10 times
is permitted to exceed 180°, even though the open- greater than error voltage vE and 180° out of
loop gain is very much greater than 1. The system phase. (Note that with an open-loop gain of only
is then said to be conditionally stable. But if the 10, the vE magnitude causes vC to be less than
loop gain temporarily decreases so that fC moves vFB. This inequality diminishes with higher loop
down into the frequency range where the phase gain.)
lag exceeds 180°, conditional stability is violated Figure 3b shows the vector relationship with a
and the loop becomes unstable. This actually does gain of 10 but at a frequency where one pole is
occur whenever the system runs into large signal active, resulting in –1 gain slope and 90° phase

Figure 3. - Vector Diagrams - Gain = 10

5-3 Control Loop Cookbook

lag. Feedback voltage vFB is 10 times greater than is 1. The system is definitely unstable.
vE, but lags by 270°. Note that vE now causes very How to design a stable loop:
little inequality between vC and vFB because of its The first step in the design of a stable, high per-
phase. This situation is perfectly stable. With vC = formance feedback loop is to define the gain/phase
1 V and open-loop gain of 10 with 90 ° phase lag, characteristic of each of the known loop elements
only this outcome is possible. (usually everything except the error amplifier, KEA).
In Figure 3c, two poles are active at the fre- Then, the characteristic of the remaining elements
quency where the gain is 10, resulting in –2 gain (KEA) is tailored to complement the combined
slope and 180° additional phase lag. Feedback characteristics of the other elements in a way that
voltage vFB is now in-phase with vE and 10 times will meet the overall loop stability criteria while
greater. Our intuition tells us that this should be a achieving the highest possible loop gain and band-
runaway situation. But intuition is wrong, when our width.
thinking is restricted to this one frequency. The In a switching power supply, the loop elements
vector relationships in Fig. 3c are perfectly stable. which actually handle the power are mostly defined
They are locked in to each other. This is the only by the parameters of the application. However,
way they can exist, under the defined conditions. many options do exist, and they should be
Note that vE now causes vFB to be greater than vC. explored. (Design experience helps to narrow
This does not signify instability – in fact, if the gain down the list of possible options.) Bode plots
is increased further, vFB becomes smaller, reduc- (Appendix B) are used to display the overall char-
ing the error without becoming unstable. acteristics of all of the loop elements except KEA.
Why does oscillation occur only at fC, where With performance objectives and stability require-
the open loop gain equals 1 ?? ments in mind, a strategy for closing the loop is
The vectors of Figure 4a show the stable con- developed and a tentative gain characteristic is
dition that exists when the gain slope is –1 as it plotted to define the goal for the entire loop. The
passes through the crossover frequency. The sin- required KEA characteristic (Appendix B) is then
gle active pole results in 90° phase lag. Feedback deduced from the difference between the Bode
voltage vFB is equal to vE, but lags by 270°. Again, plot of the overall loop goal and the plot of the
this is the only possible relationship between these known loop elements without KEA.
vectors under the conditions defined. Note that Limitations on crossover frequency:
vFB, which represents the output, lags control volt-
age vC by 45° (plus 180° negative feedback), and
the magnitude is down 3dB to .707 (compared with
Fig. 3). This represents the closed-loop gain corner
at the open loop crossover frequency, as shown in
Fig. 2.
The vector diagram for a –2 gain slope at fC
where open-loop gain equals 1 cannot be drawn,
as it is unstable. Figure 4b shows the vectors at a
gain of 1.2, instead. With a –2 slope, vE and vFB
are in-phase. With a control voltage vC of 1V, a
feedback voltage of 6 V with an error voltage of 5 V
is required to resolve the vector diagram. As the
loop gain approaches 1, it can be seen that either
vC must become zero, or vE and vFB must become
infinite. Thus, the closed loop gain, vFB/vC
becomes infinite, even though the open-loop gain Figure 4. – Vector Relationships at Crossover

Control Loop Cookbook 5-4

 Achieving a high fC is a worthwhile objective characteristic, in the frequency domain, with the
because the system can respond more rapidly to transient response in the time domain. For exam-
minimize the effects of high frequency and tran- ple, the initial slope of the transient response to a
sient disturbances. In a purely linear feedback step change is directly related to the crossover fre-
loop, fC is limited by cumulative phase lags in var- quency.
ious system elements. These phase lags inevitably The simple single pole characteristic of Fig. 5a
increase with frequency in a manner that often has an exponential characteristic with a time con-
varies unpredictably. Compensation becomes stant equal to 1/2πfC, as shown in Figure 5b. In
impossible, forcing the designer to set fC at a fre- responding to a step change, the initial slope would
quency where the phase lags are still manageable. reach the final value in exactly one time constant
In switching power supply loops, an additional (16µsec in this example), but like any exponential,
important limitation occurs. Sampling delays inher- it falls away to 63% of the final value at 1 time con-
ent in any switched system introduce additional
phase lags that force the crossover frequency to
be well below the switching frequency. This will be
discussed later.
Transient Response:
Transient behavior, in the time domain, is pre-
dictably related to the shape of the loop frequency
domain characteristics as shown in the Bode plot.
A power supply can function without the help of
a feedback loop. The duty cycle could be adjusted
manually to the value that would provide the
desired VOUT. But without feedback, even small
changes in VIN or IOUT (the usual disturbances in
a power supply application) would send VOUT
careening out of spec. With a functional feedback
loop, when an ac disturbance at a specific fre-
quency is introduced, the open-loop gain
magnitude at the frequency of the disturbance
defines how much the output disturbance is
reduced compared to what would have occurred
without feedback.
Figure 5a is the Bode plot of a loop having the
Figure 5a. – Single Pole Characteristic
gain characteristic of a single pole (–1 slope,
20dB/decade). A crossover frequency of 10kHz is
shown, with the open-loop gain rising to 1000 at
10Hz. The gain shown at each frequency indicates
the amount by which the feedback loop will reduce
a disturbance at that frequency.
The gain vs. frequency plot can also be used to
show the reduction in the Fourier components of a
transient disturbance, or how the loop will respond
to the Fourier components of a step change in the
control signal. Fortunately, Fourier analysis is usu-
ally not required to interrelate the Bode plot Figure 5b. – Single Pole Characteristic

5-5 Control Loop Cookbook

stant and reaches 98% (2% error) in 4 time con- filter capacitor, whose voltage sags as a result.
stants (64µsec). It takes a long time for the error to Ultimately, the output voltage is restored and the
diminish ultimately to 0.1% because the loop gain charge deficit made up only because the voltage
reaches 1000 only for the Fourier components loop responds to the voltage sag and calls for
below 10Hz. source current temporarily greater than the final
The single pole characteristic depicted in value. However, this voltage loop intervention
Figure 5 is extremely conservative. The –1 slope takes considerable additional time.
with its 90° phase margin results in the exponential Figure 6b shows that with two active poles, not
characteristic which takes a long time to achieve only is the charge deficit “A” reduced, but the over-
good accuracy. shoot results in a charge excess “B” which cancels
Figure 6 shows a less conservative approach all or part of the charge deficit immediately, without
which reduces the error much more rapidly. Two
active poles provide a –2 slope below fC raising
the gain below fC. This improves audio susceptibil-
ity at these frequencies, and improves response to
the higher frequency Fourier components of a tran-
sient disturbance or control signal. As shown in
Fig. 6a, the gain reaches 1000 at 300Hz, rather
than at 10Hz. Note that at fC, the –2 gain slope
transitions to a single pole –1 slope. This is neces-
sary because if the –2 slope continued above fC,
the phase margin would be too small, resulting in
severe underdamped oscillations at fC. The transi-
tion to a single pole at fC results in an acceptable
phase margin of 52°.
Figure 6b shows that the initial slope is the
same as in Figure 5b, because fC is the same in
both cases. But the transient response holds up
better because the gain rises more rapidly at the
frequencies below fC. However, this results in 16%
overshoot, which occurs at .58/fC (58µsec in this
example).
Although the peak error with the –2 slope
Figure 6a. – Two Pole Characteristic
exceeds the error at the same time with the –1
slope, it subsequently diminishes more rapidly.
What is more, the overshoot is actually beneficial in
some situations.
For example, in a power supply application
with an inner current control loop and an outer volt-
age control loop, assume Figure 5b shows the
transient response of the current control loop to a
step change in load current at time 0. The load cur-
rent rises immediately to the final value, but the
source current follows the transient response char-
acteristic. Area “A” shows the charge deficit that
results. The load draws this deficit from the output
Figure 6b. – Two Pole Characteristic

Control Loop Cookbook 5-6

requiring voltage loop intervention. controlling the output. An output filter averages the
Switching Power Supply Loops
power pulses to obtain a DC output with acceptable
Power Circuit Design: ripple.
Just as the power supply is often the step-child
Continuous Current Mode (CCM):
in the design of the complete system, the control
This operating mode occurs, by definition,
loop is often the step-child in the design of the
when inductor current flows continuously through-
power supply. The power handling circuit topology
out the switching period. The CCM current
with its associated components is the most signifi-
waveforms, shown in Figure 8, apply to all three
cant portion of the control loop design, causing
topologies. But, referring to Figure 7, input and out-
most of the problems and complexity. The power
put currents differ for each topology because of the
circuit is usually defined first, attempting to imple-
different locations of the inductor, switch and diode.
ment system requirements in the most cost-
There are two operational states –Switch ON,
effective way, with little consideration given to con-
when it carries the inductor current, or Switch OFF,
trol loop closure. The control loop design usually
when the diode carries the inductor current.
must adapt to a predefined power circuit.
Under steady-state conditions, inductor volt-
Before proceeding with the control loop it is
age VL must average zero during each switching
necessary to examine some of the power circuit
period. With only two states, a specific, rigid rela-
choices that must be made. This is a difficult sub-
ject to organize, because of the complex
interactions between these choices.
Choices:
• Power Circuit Topology
• Control Method
• Transformer Turns Ratio
• Switching Frequency
• Filter Capacitor
• Filter Inductor

Considerations:
• Cost
• Size/Weight
• Efficiency
• Noise

Switchmode Topologies:
In the basic buck, boost and flyback power cir-
cuit topologies, shown in Figure 7, the inductor is
the element which transfers power from the input to
the output. (In the unique Cuk converter — a dual
of the flyback — a capacitor is the energy transfer
element.) The power switch is turned on and off
during each switching period by a Pulse Width
Modulator (PWM). The duty cycle, D, (the percent-
age of time the switch is ON) is the basis for Fig. 7. - Basic Buck, Boost, Flyback Topologies

5-7 Control Loop Cookbook

 switch turns on at the beginning of the next switch-
ing period. This zero current interval is a third
operating state in addition to the two that exist with
CCM, and the additional degree of freedom that
this provides destroys the rigid VI, VO, and D rela-
tionship. With DCM operation, the small signal gain
of the power circuit is much less than in the contin-
uous mode, and DCM gain varies considerably
with load.
However, the DCM control characteristic is
simpler, especially with the boost and flyback
topologies because the right half-plane zero does
not exist. For this reason, the flyback topology is
often used in the discontinuous mode at low power
levels where noise and filtering problems are not
as severe.
The Pulse Width Modulator controls the duty
cycle of the power switch — the fraction of time
that the switch is ON during each switching period.

Fig. 8. - Continuous Mode Waveforms

tionship exists between input voltage VI, output

voltage VO and duty cycle D, a relationship that is
independent of load current and is unique for each
topology:
Most switching power supplies are designed to
operate in the continuous mode, especially at high-
er power levels, because filtering is easier and
noise is less. Boost and flyback circuits operated in
the CCM have a unique problem — their control
loop characteristic includes a right half-plane zero
that makes loop compensation very difficult.
Discontinuous Current Mode (DCM):
As shown in Figure 9, the discontinuous induc-
tor current mode occurs when the inductor current,
flowing through the diode, reaches zero before the
end of the switching period. The diode prevents the
current from continuing in the negative direction.
Thus, the inductor current remains at zero until the Fig. 9. - Discontinuous Mode

Control Loop Cookbook 5-8

The ON/OFF action of the power circuit is aver- preferred because it permits the switching frequen-
aged and filtered to provide a dc output. The output cy to be synchronized with other power supplies in
magnitude is related to the duty cycle, D, thus the a system, or with video terminal horizontal sweep
pulse width modulator (PWM) provides the basis frequency, to prevent spurious beat frequencies
for control and regulation of the output. and other undesirable effects. Also, fixed frequen-
There are many varieties of pulse width modu- cy control loops have simpler relationships which
lators: Fixed frequency - variable duty cycle, Fixed are much easier to understand and optimize.
ON-time (Variable Frequency), Fixed OFF-time Fixed frequency PWMs function on the basis of
(VF), Hysteretic (VF), The choice of PWM method a latching comparator as shown in Figures 10 and
significantly affects power circuit behavior and 11. (Latching prevents spurious reset due to
small-signal characteristics and thus on the strate- noise.) A control voltage, Vc, (usually the amplified
gy for closing the feedback loop. error signal from the controlled output) is compared
This paper considers only fixed frequency to a fixed frequency linear sawtooth ramp, Vs. The
PWM methods, which are used in the great major- comparator output provides fixed frequency pulses
ity of control ICs. Fixed frequency operation is of variable duty cycle which drive the power switch-
ing transistors. The duty cycle D of the power
switch conduction is thereby controlled by varying
VC according to the relationship shown in Eq. 3.
(D, VC, VS are dc values, d, vC are small-signal ac
or incremental values.)

VC v
D= ;d= C (3)
VS VS

The PWM waveforms of Fig. 11 can be

observed only in very low bandwidth loops. In a
high-performance loop with fC near optimum, con-
trol voltage vC is not flat, as shown, but has a
Figure 10. - PWM Comparator
superimposed triangular waveform (derived from
inductor ripple current) that approaches the magni-
tude of sawtooth voltage VS. The superimposed
triangular waveform modifies the duty cycle rela-
tionship of Eq. 3, and can also cause subharmonic
oscillation. This will be discussed later. Until then,
the idealized waveforms of Fig. 11 will be used.
Modulator Phase Lag:
Virtually all fixed-frequency PWM control ICs
use the simple comparator method shown in Figs
10 and 11. The output pulse is terminated according
to the instantaneous value of the feedback control
voltage at the moment of pulse termination. This
“naturally sampled” method of pulse width modula-
tion ideally results in zero phase lag in the modulator
and in the converter power switching stage.(1) In
practice, however, comparator delays and turn-off
Figure 11. - PWM Waveforms delays in the power switch will cause a phase lag

5-9 Control Loop Cookbook

 Fig. 12. - Forward Converter

directly proportional to the delay time, td, and signal VImin = VO/Dmax (6)
frequency, f, according to the relationship:
Duty Cycle Range:
øm = 360tD/T = 360tDf (4) It is theoretically possible for the basic buck
This additional phase lag reduces the phase regulator and its push-pull transformer-coupled
margin at the unity gain crossover frequency and derivatives to utilize the full 0 to 1 duty cycle range,
theoretically may contribute to control loop instabil- but D close to 1 is best, as it results in the lowest
ity. However, the additional lag is usually negligible. primary-side current and lowest secondary volt-
For example, at an fC of 25kHz, consistent with fS ages. (The boost topology functions most
= 200kHz, a turnoff delay of 0.4 µsec in the IC and effectively with D close to 0, the flyback with D
the power switch causes only 3.6° additional phase close to 0.5.)
lag, reducing phase margin by that amount. As shown in Eq. 6, for the buck regulator, the
Most control ICs have additional “housekeep- minimum VI at which the circuit can function is
ing functions” such as UVLO - UnderVoltage defined by DMAX. In transformer coupled topolo-
LockOut, HVLO - HighVoltage LockOut, and Soft gies, the minimum VI defines the transformer turns
Start, which are not discussed in this paper as they ratio.
are not directly relevant to control loop design. DMAX can never reach 1 because of practical
limitations. Some of these limitations are: turn-on
Design Relationships –
propagation delays and switch delay & rise times,
Buck-Derived Topologies:
resonant transition times, and reset time for the
In addition to the basic buck regulator, trans-
current sense transformer, if a CT is used. DMAX is
former-coupled buck-derived topologies include
typically limited to between 0.85 – 0.95. Any appli-
the single-ended Forward Converter and a variety
cation involving a transformer must provide time to
of push-pull converters: Center-tap, Full Bridge,
reset the transformer core – the reverse volt-sec-
and Half-Bridge.
onds must equal the forward volt-seconds to get
The basic relationship governing the power cir-
the flux back to the starting point. Push-pull circuits
cuit of all buck-derived topologies operated with
automatically reset the core by driving it in opposite
continuous inductor current is:
directions during successive switching periods.
VO = VID; vO = VId (5) The Forward Converter has the most serious prob-
lem – it is driven in only one direction, and the
subsequent voltage reversal required for core reset
typically equals the time driven in the forward direc-

Control Loop Cookbook 5-10

tion, thus limiting DMAX to less than 0.5. This clock cycle.
means that the minimum VIN referred to the sec- Transformer Turns Ratio:
ondary side must be greater than twice VOUT. First, the minimum input voltage referred to the
Minimum Duty Cycle: secondary side, min VI, is determined. Using Eq. 6,
Likewise, DMIN cannot reach zero. Once the calculate min VI based on DMAX, then add full load
switch is turned ON to initiate a power pulse, the switch, diode and IR drops. Allow for some addi-
switch is committed to stay ON for a certain mini- tional voltage across the inductor, or its current
mum time. This minimum pulse width at a fixed cannot increase rapidly under min VI conditions
switching frequency equates to a minimum duty when necessary to keep up with a load current
cycle. Some of the items that contribute to DMIN increase. With this adjusted min VI value, and the
are: Turn-off propagation delays and switch delay minimum source voltage, VIN, the turns ratio can
& fall times, resonant transition times, and noise be calculated:
blanking (which disables the PWM comparator for VIN Np
VI = ; (n = )
a short time after turn-on to prevent a spurious n NS
noise pulse from causing premature turn-off). In this paper, to minimize the complexity of the
In normal operation, D is always much greater control loop relationships, all circuit values are
than zero. Certain events will cause D to approach referred to the secondary side. Thus, turns ratio n
zero temporarily, such as when load current dimin- and actual input source VIN do not appear, only VI,
ishes at a rate faster than inductor current can the input voltage referred to the secondary.
decrease (max diL /dt = VOUT /L). In this situation For low voltage outputs, accuracy is improved
the DMIN value attained is not critical. The DMIN by adding the output rectifier forward drop to the
value does become critical when the output is actual output voltage, using this “corrected” value
short-circuited. When VOUT is pulled down to zero, of VO in the design equations.
and VIN is at its normal value, then D must be Inductor Ripple Current is inversely propor-
brought to zero to maintain control and keep the tional to inductance value. In buck-derived
current within the limit. This bleak situation is topologies a small inductor with large ripple current
remedied by the output rectifier forward drop which has these disadvantages: (1) a bigger output filter
acts as a minimum VOUT. But when VIN is near capacitor is required, (2) large ripple dictates a
maximum, and especially when VOUT is 28 V or large minimum load current to avoid discontinuous
higher and the rectifier drop has less significance, operation. (This disadvantage is overcome by
the required D value may still be less than DMIN. using Average Current Mode Control.)
This is then a serious problem. Many control ICs Advantages of the smaller inductor are: (1)
always initiate an output pulse at the beginning of Lower size and cost, (2) inductor current can
each clock cycle, relying on current limiting to turn change more rapidly in response to a sudden load
off the power pulse quickly under overload or short change and (3) together with the larger CO,
circuit conditions. But “quickly” may not be quick reduces over/undershoot occurring with a large
enough. step load change.
The solution employed in many modern ICs is The inductance value obviously plays a key
to skip pulses, or shift the frequency downward. role in the control loop design.
Under overload conditions, if pulses are skipped
entirely, the switching frequency effectively adjusts Filter Capacitors
downward. The minimum pulse width does not get Output filter capacitors are almost certainly the
smaller, but D does become small enough to retain most troublesome element in the control loop. In
control. Pulse skipping requires a control IC that their power filtering role, they typically absorb
has the logic to completely inhibit switch turn-on if Amperes of ripple current and hold the output rip-
current exceeds the limit at the beginning of the ple voltage to a small fraction of a Volt. The low

5-11 Control Loop Cookbook

impedance required usually dictates the use of inversely with frequency, which makes ESR
electrolytic capacitors. Ceramic capacitors are not appear to vary inversely with frequency squared.
usually considered practical unless the switching In a switching power supply application, the
frequency is well over 500kHz and/or with high out- actual series resistance SR is of key importance,
put voltages. but the parallel resistance is of little or no signifi-
Electrolytic Capacitors – cance (except possibly for reliability concerns). So
Series Resistance: ESR data is very misleading until the frequency is
At the 50-400kHz switching frequencies main- high enough that the converted parallel resistance
ly used in today’s SMPS applications, electrolytic becomes smaller than the true series resistance.
capacitor impedance is determined by its series At higher frequencies, the ESR characteristic flat-
resistance, SR. As frequency is increased, when tens out at the true SR value. Capacitors intended
capacitive reactance drops below series resis- for high frequency application are measured and
tance, the impedance curve tends to flatten out at specified at 100kHz which reveals the true series
the SR value. The frequency at which this occurs resistance. Low frequency ESR measurements
(the ESR zero frequency) is 1 to 10kHz for are totally irrelevant. However, bowing to common
Aluminum electrolytics, 10 to 60kHz for Tantalum. usage, this document uses “ESR” to refer to the
Almost all power supplies today switch at frequen- actual series resistance evident at high frequency.
cies well above this. Electrolytic capacitors must Capacitance and ESR variation:
then be selected and specified on the basis of their The impedance transition from capacitive (with
series resistance. The resulting capacitance val- –1 slope) to resistive (with 0 slope) puts a zero in
ues are much greater than would be required if the the control loop Bode plot. The frequency at which
SR were not dominant – often 100 times greater this occurs is called the ESR zero frequency, fESR.
with aluminum electrolytics at 200kHz switching
frequency. 1
fESR = (7)
At switching frequencies above fESR, the
impedance characteristic flattens out at the SR
value, so that the same capacitor is required
The problem with aluminum electrolytics in the
regardless of the frequency. Going to a higher fS
control loop is that fESR is usually near or below the
does not change the filter capacitor or reduce its
desired crossover frequency. ESR variation caus-
cost.
es a corresponding fESR variation. This results in
SR or ESR?? variable loop gain and variable phase margin,
Electrolytic capacitors have both series and making it difficult to cross over above fESR. If the
parallel resistance components. At low frequencies supply must operate over a wide temperature
where capacitive reactance is large, the parallel range, the large ESR variation with temperature
resistance (leakage through the dielectric) domi- can make it impossible, forcing the design to cross
nates, and true series resistance (mostly in the over at a low frequency (probably below 1kHz).
electrolyte) is negligible. Measurements taken on a Capacitance variation is quite small, so that
bridge cannot distinguish between actual parallel below fESR the characteristic is stable and pre-
and actual series resistance. Bridge measure- dictable. Data from Panasonic on the FA Series
ments lump both resistances together – the actual Aluminum Electrolytics:
series resistance plus the parallel resistance con-
Capacitance:
verted to its series equivalent. This combination is
20°C distr.: 100%–120% of spec. value
called “Equivalent Series Resistance”, or ESR. At
+10% @ 105°C; –10% @ –55°C
low frequency (50-60Hz), the converted parallel
resistance dominates. Capacitive reactance, the ESR:
fulcrum of the parallel to series conversion, varies 20°C distr.: 60% – 85% of specified max.

Control Loop Cookbook 5-12

 x.33 @105°C; x2 @ –10°C; x12 @ –55°C are usually adequate for their purpose. To calculate
the rms equivalent of the peak-peak triangular
A Little Trickery:
inductor ripple current waveform:
Electrolytic capacitors with the same case size
and manufacture but with different voltage ratings Irms = Ipp (8)
and capacitance values all tend to have the same 2 3
ESR. The dielectric oxide thickness which deter-
mines the voltage vs. capacitance tradeoff is Capacitor Inductance:
“formed” late in the manufacturing process. The The path for ac current flow within an aluminum
dielectric thickness does not significantly affect electrolytic capacitor is quite long, simply because
ESR. For example, in a 16x20 mm case size, of their relatively large size. This results in larger
Panasonic FA series 10V, 3300µF and 50V, 680µF series inductance than other capacitor types. The
capacitors have the same ESR: 25 mΩ max. impedance characteristic is determined by ESR
For SMPS ripple filtering, electrolytic capacitor above fESR, but at approximately 500kHz, the
selection is based entirely on the ESR require- impedance rises because the series inductance
ment. A 5V output requiring 25 mΩ max. ESR becomes dominant. Other capacitor types then
could use either of the above capacitors. The become more advantageous.
3300µF, 10V capacitor puts a 2kHz ESR zero into Tantalum Capacitors:
the control loop, But the 680µF, 50V puts the ESR Characteristics are similar to aluminum elec-
zero at 10kHz. Thus, if it is necessary or desirable trolytics, but tantalum electrolytics are better: The
to make the loop gain crossover below fESR to ESR zero frequency is 5-10 times higher than alu-
avoid the problems caused by ESR variability and minum, making it easier to achieve greater loop
unpredictability, the smaller capacitance value with bandwidth, with improved dynamic response. (But
the higher fESR is clearly the better choice. ESR remains the impedance determining factor for
There is a downside to this choice, however. In ripple filtering at SMPS switching frequencies.) The
the continuous conduction mode, the filter induc- ESR has a much lower temperature coefficient,
tance prevents the inductor current from making tantalum much better suited to military and
responding rapidly to a step load current change. other wide temperature range applications. Size is
The output filter capacitance (not the ESR) much smaller for the same ESR. The smaller size
absorbs the load current change while the inductor also results in lower inductance, enabling opera-
current catches up. The extravagantly excessive tion up to 1MHz.
capacitance value necessary with electrolytic The downside for tantalum capacitors is sub-
capacitors does become very useful by providing a stantially higher cost for the same ESR required.
very low output surge impedance – it “holds the Also, the lower capacitance value associated with
fort” until reinforcements arrive. The faster control the necessary ESR (the reason why fESR is
loop does nothing to help in this situation – this is greater) results in a higher output surge imped-
a large-signal limitation dictated by inadequate ance, so the output does not stand up as well to a
inductor current slew rate, during which the control large step load change.
error amplifier is driven to its limits and the loop is Ceramic Capacitors:
temporarily open and non-functional. Radically different from the electrolytics, ESR
Ripple Current Rating: is negligible — an ESR zero frequency doesn’t
AC ripple current flowing through the capacitor exist. Impedance is not determined by ESR, but by
ESR generates heat. Temperature rise and reliabil- capacitance (or by inductance at frequencies
ity considerations are the basis for an rms current above 1-2MHz). Small size, surface mount pack-
limit. The low ESR capacitors normally used in aging keeps inductance the lowest of all the
SMPS applications have rms current ratings that alternatives.
But the cost of obtaining the necessary capac-

5-13 Control Loop Cookbook

itance with ceramic is excessive at switching fre- by raising the frequency have helped the most to
quencies below 500kHz. Even at higher achieve these goals. But at frequencies above
frequencies, to achieve the required capacitance at 500kHz, core losses in today’s best magnetic
a reasonable cost, high K dielectrics are used. The materials (1996) rise to the point where this trend
large temperature coefficients of these dielectrics slows down and then reverses — the magnetic
make it difficult to optimize the loop over a wide components start to get larger. The filter capacitor
temperature range. Also, the C value required to might be expected to get smaller with increased
obtain the required ripple reduction is much less frequency, but it does not because its impedance
that the capacitance obtained by default with the depends on ESR, not capacitance – until the fre-
electrolytics. This results in relatively high output quency is reached where ceramic capacitors
surge impedance and little tolerance for step load become economically feasible. At higher switching
changes. frequencies, there is more high frequency noise
Polymer Aluminum Electrolytics: generated, but less low frequency noise, so that
Similar to ceramics, these new arrivals in the conducted EMI is easier and less costly to filter.
capacitor catalog have negligible ESR, small size, The control loop bandwidth can of course be raised
low inductance, but high output surge impedance. proportional to fS, but this is seldom part of the
But here the similarity ends. Available capacitance rationale for increased frequency.
values are not only much greater than ceramics, The obstacles to achieving higher switching
but capacitance distributions are tight, and temper- frequencies at reduced cost all seem to boil down
ature coefficients are low. Polymer aluminum to one thing: increased losses, which lower effi-
electrolytics approach the ideal for filter capacitors. ciency and raise the cost of heat removal. Ongoing
The limitations of the existing devices are: Low improvement involves circuit topologies and innov-
voltage ratings:16V max. One small size surface ative techniques such as the recently popular
mount package available: (8mm x 5.3mm x 3.3mm “resonant switching transitions” which reduce loss-
high) limits C values to the range of 6 - 33 µF. es and noise. Improved high frequency magnetic
Higher cost unless the switching frequency is high materials are needed, as well as faster semicon-
enough to overcome this. ductors. New concepts in the “wiring” and layout of
In a 200kHz power supply, one of the present- high frequency circuits and magnetic components
ly available polymer aluminum electrolytics will are needed to reduce parasitic inductances which
handle the filtering of a 5V, 25A buck regulator out- increase losses, impair regulation, and radiate
put at perhaps twice the cost (in Jan’96) of a EMI.
competitive (but much larger) aluminum electrolyt- Control Methods
ic. At fS of 400kHz, they are probably
Voltage Mode Control:
cost-competitive.
The earliest control method, implemented in
Panasonic states that their polymer electrolyt-
most older control IC’s. This was discussed previ-
ics are now being used as output filters in switching
ously (refer back to Figs. 10 and 11). The fixed
power supplies. If these devices fulfill their promise
amplitude sawtooth ramp is usually taken from the
and are made available in larger sizes with greater
control IC’s clock generator. VMC disadvantages
capacitance values and/or if switching frequencies
are: (1) No voltage feedforward to anticipate the
continue to rise, perhaps they will some day come
affects of input voltage changes. Thus, slow
to dominate this application.
response to sudden input changes, poor audio
Switching Frequency: susceptibility and poor open loop line regulation,
The rationale for the inexorable rise in SMPS requiring higher loop gain to achieve specifica-
switching frequency over the years has been tions. (2) In continuous mode regulators, provides
reduced cost as well as reduced size and weight. no help in dealing with the resonant two pole filter
The smaller magnetic components made possible characteristic with its sudden 180° phase shift.

Control Loop Cookbook 5-14

Control changes must propagate through these Voltage Mode Control. The ramp is actually the
two filter poles to make a desired output correction, inductor ripple current, as it rises while the switch is
resulting in poor dynamic response. While VMC ON, translated into a voltage by a current sense
might appear to be less costly because there is no resistor. This ramp, representing the inductor cur-
current loop with its need for current sensing, but rent, is fed back to the PWM comparator, forming
current limiting is almost always required, and this an inner current control loop. When the current
requires the current to be sensed. With Current rises to the level of the control voltage, the switch is
Mode Control, current limiting is automatic and turned off. The control voltage (which is the ampli-
“free”. fied output voltage error), thus defines the peak
(Peak) Current Mode Control: inductor current. The outer voltage control loop pro-
This control method (CMC) also controls the grams the inductor current via the inner loop while
duty cycle by comparing the control voltage to a the current loop directly controls the duty cycle .
fixed frequency sawtooth ramp, but the ramp is not In the forward converter shown in Figure 13,
derived artificially from a ramp generator, as with the inductor is on the secondary side. But since the

Figure 13. - Peak Current Mode Control

5-15 Control Loop Cookbook

control IC is on the primary side, it is easier to tendency to oscillate (or a full-blown oscillation) at
sense primary-side switch current. This works frequency fS /2.
because the switch current is the inductor current Figure 14 shows the subharmonic instability in
(while it is rising) divided by the transformer turns a peak CMC loop. Normal operation is shown by
ratio. This eliminates the problem of bringing the the solid triangular waveform labeled iL. This volt-
current information across the isolation boundary. age, representing the inductor current, is applied to
The advantages of CMC are profound. Most of one side of the comparator. The switch is turned on
the problems of Voltage Mode Control are elimi- by a clock pulse, and iL rises until it reaches con-
nated or reduced. CMC has inherent voltage trol voltage VC at the other comparator input. The
feedforward and responds instantaneously to input switch turns off, and the current decreases until the
voltage changes. The inductor pole is now located next clock pulse occurs. (It does not matter of the
inside the current loop. Instead of the two pole sec- current downslope is observed through the current
ond order filter of the VMC loop the outer voltage sense resistor—referring to Fig.13—because
loop now has a single pole (the filter capacitor), switch turn-on is by the clock, and not dependent
greatly simplifying loop compensation. The capac- on the current level.)
itor ESR with its variability remains in the voltage Using perturbation analysis, a small deviation,
loop. ∆, is assumed in the inductor current. The deviated
The CMC closed loop is part of the outer volt- waveform has the same slopes as before, because
age control loop. The CMC closed-loop the voltages across the inductor have not changed
characteristic approaches an ideal transconduc- – just the initial current has been changed. The
tance amplifier. Closed-loop gain is flat up to its dash line in Fig. 14 reveals the instability. In a sta-
open-loop crossover frequency, which is optimally ble system, the perturbation gets smaller every
1/3 to 1/6 of the switching frequency. At the CMC switching period.
crossover frequency, its closed-loop gain rolls off True subharmonic instability can be eliminated
with a –1 slope, adding a second pole into the using a slope compensation technique, discussed
outer voltage loop, but at a much higher frequency below. Sometimes, what appears to be subhar-
than the capacitor pole. monic instability is really noise at the comparator
Peak current mode control does have its own input. When the clock pulse turns the power switch
set of problems: Average current is what should be on, much noise is generated. A noise spike at the
controlled, but peak is controlled instead. The comparator input can easily turn the switch off
peak-to-average error is quite large, especially at immediately, effectively causing one or more entire
light loads, and the voltage loop must correct for switching period to be skipped.
this, which hurts response time. Open loop gain of Latching Comparator:
the CMC loop is already quite low (5 - 10) in the When the voltages at the PWM comparator
continuous current mode, but when the load dimin- inputs intersect, and the power switch is turned off,
ishes to the point where inductor current becomes the comparator must be designed to latch in that
discontinuous, the CMC loop gain plummets and
the peak-to-average error becomes huge.
Operation becomes unsatisfactory in the discontin-
uous mode.
Subharmonic Instability:
Switching power supply control loops are all
subject to subharmonic instability if the waveforms
applied to the two inputs of the PWM comparator
do not cross over each other at their points of
intersection. This instability is observed as a Figure 14. - Peak CMC Subharmonic Instability

Control Loop Cookbook 5-16

state until reset by the next clock pulse. Otherwise, match.
if the waveforms trajectories diverge without The crossover frequency is directly related to
crossing over, as in Fig. 14, the switch will turn the gain. Middlebrook has shown that for a buck-
back on immediately. Even if the waveforms do derived regulator with optimum slope
cross over, a noise spike could cause the com- compensation, the crossover frequency is:
parator to reset and turn on the power switch
prematurely. The latching comparator prevents fc = fs (9)
these undesired occurrences.
Slope Compensation:
Thus, depending on duty cycle D, fC ranges
Subharmonic instability is eliminated simply by
from 1/3 to 1/6 of fS.
forcing the waveforms at the two inputs of the com-
Although Fig. 15 shows a ramp with a negative
parator to cross over each other at their points of
slope added to the control voltage waveform
intersection. This can be accomplished by adding
(because it is easier to visualize), in practice a pos-
an artificial ramp to one of the comparator inputs.
itive ramp slope is usually added to the inductor
Figure 15 shows an optimum slope compensation
current waveform, simply because a positive ramp
ramp added to the control voltage comparator input,
is available in the IC’s clock generator.
labeled “VC + VS”. The optimum ramp, as shown,
It can be argued whether subharmonic instabil-
causes the two waveforms at the comparator inputs
ity results from the sampling delays inherent in a
to coincide during the interval when the switch is off
switched system, or whether it is just a geometry
and the inductor current is decreasing, rather than
problem. Certainly this instability can either be gen-
actually cross over. This is ideal, because, as
erated or corrected by adding a purely artificial
shown, a perturbation is erased in the very first
ramp, unrelated to the loop elements.
switching period after its occurrence!!
Linear models have been attempted so that the
The compensation ramp reduces the current
effects of subharmonic instability can be included
loop gain. If the ramp slope is increased further so
in frequency domain analysis. However, these
that the waveforms actually cross over, the system
empirical models lose sight of the underlying
is stable but the gain is reduced below optimum
causes and are blind to the slope manipulation
(and it actually takes longer for the perturbation to
techniques which can optimize bandwidth without
be erased). Optimum is when slopes coincide, or
instability. The underlying causes of instability are
best demonstrated and corrected in the time
domain, observing and appropriately modifying the
waveform trajectories on opposite sides of the
PWM comparator.
Average Current Mode Control:
The deficiencies of the Peak CMC loop basi-
cally relate to its low internal loop gain. Average
CMC, as shown in Figure 16, eliminates this prob-
lem by adding an error amplifier to the current loop
(in addition to the amplifier in the outer voltage
loop). Inductor current is sensed through a resistor.
The resulting voltage is compared with voltage
VCP which sets the desired inductor current. The
differential, representing the current error, is ampli-
Figure 15. - Peak CMC with Slope fied by CA, the current error amplifier. The CA
Compensation
output is compared to a sawtooth ramp taken from
the IC clock generator to determine the duty cycle

5-17 Control Loop Cookbook

 Figure 16. – Average Current Mode Control
– the same technique commonly used with Voltage attributes – it has the same crossover frequency,
Mode Control. the same instantaneous response to a current
Figure 17 shows the comparator voltage wave- overload, etc. But at frequencies below fC, where
forms when the E/A gain is optimized using the the peak CMC loop gain flattens out at a gain of
slope matching criteria discussed below. Note that only 5 or 10, the gain of the average CMC loop
amplifier CA inverts the error signal, so the trian- keeps rising, ultimately to a gain of more than 1000
gular waveform VCA is an upside-down if desired. This much higher loop gain at lower fre-
representation of the inductor ripple current. The quencies eliminates the peak-to-average error and
rising portion of the VCA waveform (coincident with enables the average CMC loop to function well at
sawtooth waveform VS) represents falling inductor light loads when the inductor current becomes dis-
current, when the switch is OFF. As Figure 17 continuous.
shows, where the waveforms intersect (near the Reference (2) describes Average CMC in detail.
midpoint of the sawtooth ramp) and the switch
turns OFF is where the inductor current is at its Slope Matching:
peak (the waveform is inverted). Why is this called In the basic PWM system used with Voltage
average CMC if it really functions at the peak?? Mode Control (Fig. 10 and 11), and with peak CMC
Actually, average CMC when optimized is identical (Fig. 14 and 15), the error signal applied to one
in its behavior to peak CMC with all of its positive side of the comparator is usually thought of as a dc
level crossing over the sawtooth ramp, as shown in
Fig. 11. This is only true if the open loop band-
width, fC, is extremely low — at least a factor of 10
below optimum. As the error amplifier gain is
increased (and bandwidth along with it), the trian-
gular inductor ripple current becomes evident at
the output of the error amplifier. In Figure 17, where
gain and bandwidth are optimum, the inductor rip-
ple current (seen as vCA) has become quite large.
Optimum error amplifier gain is achieved when the
slopes of the two waveforms coincide as shown in
Figure 17 during the interval preceding the next
Figure 17. – Average CMC Waveforms clock pulse. In this case, it also happens to be the

Control Loop Cookbook 5-18

interval following switch turn-off when the inductor How to Implement Slope Matching:
current is falling (the amplifier inverts the wave- The inductor current downslope is translated
form). into a voltage downslope by a current sense resis-
Note that when the slopes coincide, the peaks tor, RS. The gain of the Current amplifier, CA, (at
also must coincide. Also, a perturbation applied to the switching frequency fS) is set so that the slope
the VCA waveform is eliminated in the very first at CA output equals the ramp slope at the other
switching period, just like with optimum slope com- input of the PWM comparator. For buck and boost
pensation with peak CMC (Ref. Fig. 15). topologies, the inductor current downslope is VO/L.
If the amplifier gain is increased beyond this opti- The ramp slope is VS/TS, or VSfS. Therefore:
mum condition, two bad things happen:
VORS VSfSL
GCA = VSfS; GCA = V R (10)
(1) The triangular waveform VCA increases, mak- L O S
ing its positive peak exceed the positive peak
of sawtooth VS. Depending upon the IC
Slope Matching with Voltage Mode:
design, the E/A output may clamp VCA at a
The slope-matching criteria for loop bandwidth
voltage not much larger than the VS peak. (The
optimization applies not only to the Average CMC
amplifier should be designed to clamp at this
loop, but to any system that uses a similar PWM
level. Otherwise during large signal events
technique. For example, the single-loop Voltage
when the amplifier is “in the stops”, the E/A out-
Mode Control described earlier benefits from the
put would rise substantially, increasing the time
same strategy. With VMC, an electrolytic output
required to recover from such an event.) If the
capacitor appears resistive at fS, so the triangular
waveform becomes clamped, the gain will sud-
inductor current waveshape appears across the
denly appear to drop. Slope matching is
capacitor ESR, just as it does across the Average
consistent with the vC waveform not exceeding
CMC current sense resistor. The voltage error
the sawtooth VS.
amplifier gain is adjusted until its output slope coin-
(2) Even if clamping does not occur, the increased cides with the sawtooth ramp slope. The
triangular amplitude means the waveforms do comparator waveforms look exactly like the Avg.
not cross over or coincide after the switch turns CMC waveforms in Figure 17. The result is that,
off, and a tendency toward subharmonic insta- when optimized by slope matching, the lowly sin-
bility begins. gle-loop Voltage Mode Control not only has (a) the
It should be obvious that slope matching and same crossover frequency as Current Mode
slope compensation are closely related. In fact Control,[3] the optimized VMC loop has (b) con-
they are two sides of the same coin – the problems stant gain, independent of VIN. Even more
are identical, the optimization criteria are identical, importantly, the optimized VMC control loop (c)
and the benefits are identical. The only difference responds instantly to changes in VIN, just like
is that with Peak CMC, the triangular voltage rep- CMC. The advantage of CMC remains that it is
resenting inductor current is fixed, and a sawtooth easier to implement, because the frequency
compensating ramp is introduced whose magni- dependent elements are apportioned between the
tude is adjusted to obtain coincident slopes. With two loops, thus are easier to deal with.
Average CMC, the sawtooth ramp is fixed, and the Slope Matching Effect on PWM Gain:
triangular voltage representing inductor current is It was not recognized until recently that the
adjusted (by varying the E/A gain) to obtain coinci- optimized triangular waveform applied to the PWM
dent slopes. In both systems, when the slopes are comparator causes a change in the PWM gain
made to coincide, their crossover frequencies will characteristic. The relationship given in Eq. 3 is
not only be optimum, they will be the same. correct for low-gain, low-bandwidth loop whose
amplified error signal appears as a dc level, as

5-19 Control Loop Cookbook

shown in Fig. 11. But when the E/A gain is opti-
mized, the slope of the initial portion of the Using the modified PWM characteristic in Eq.
triangular waveform, when the switch is ON, varies 10 above, instead of Eq. 3, the power circuit plus
as a function of duty cycle. As shown in Figure 18, PWM gain becomes:
when the slope is relatively flat with D almost 1, an
incremental change in the control voltage, vC, vRS R VO
= S corrected Ref. (2), Eq.(2)
causes a large incremental change in the duty vCA sL
cycle, d. When D is near zero, the initial slope is
steep, so the same incremental vC change causes Replacing VIN by VOUT may seem like a minor
a much smaller change in d. By inspection, it can correction, but VIN changes, VO is fixed. Thus in
bee seen that with slope-matched waveforms, the the optimized version, gain is constant, with the
PWM “gain” is directly proportional to the duty original version, gain varies directly with VIN.
cycle D: Also, in Reference (2), Eq. (3) changes:

vC
d= D (11) fs fs
VS fc = 2šD becomes: fc = 2š (12)

Whereas the PWM characteristic with a low-

bandwidth “flat” control voltage from Eq. 3 does not With the loop gain and crossover frequency
change with D. now constant and independent of VIN, closing the
This modified PWM characteristic was not current loop and the outer voltage loop become
known at the time several earlier papers on much easier.
Average CMC were written, and some of their gain Interaction in Two-Loop Systems:
expressions are in error. For example, with a Buck- In a two-loop system, the inner current control
derived regulator, duty cycle D = VO/VI. In loop determines the response to input voltage
Reference (2), “Average Current Mode Control of changes, while the outer voltage control loop deter-
Switching Power Supplies,” Eq. (2), the expression mines response to load current change. These
for the power circuit plus PWM gain is: loops do interact, especially if their respective
crossover frequencies are close to each other.
vRS RS VIN If both loops must be optimized for fast
= Ref. (2), Eq.(2)
vCA response, interaction is involved in the slope-
matching process. There is only one PWM in a
two-loop system. The triangular waveform vCA at
the output of the current error amplifier CA actual-
ly has two components – the inductor ripple current
seen across the current sense resistor and fed
through CA, and the inductor current seen across
the output capacitor ESR and fed through voltage
error amplifier VA and CA. These two triangular
waveforms are in-phase. VA and CA gains must be
adjusted so the combined slopes match the saw-
tooth waveform, but this can be accomplished in
different ways. For example, in a buck regulator
with a single loop optimized by slope matching, fS
equals fC/2π. But with two loops, if VA and CA
gains are adjusted so that each loop contributes 1/2
Figure 18. – Modulator Gain vs. Duty Cycle

Control Loop Cookbook 5-20

of the total slope-matched triangular waveform, CMC is that it can operate in the discontinuous
each will have fS equal to fC/4π. However, if the inductor current mode, which permits the use of a
current loop has more gain and the voltage smaller inductor value. This not only saves size,
loop less, the current loop contributes more weight and cost, it raises the RHP zero frequency
than 1/2 of the total triangular waveform so its to permit greater bandwidth for these topologies.
crossover frequency fCI will be greater than fCV of
Loop Design Procedure:
the voltage loop.
Normally, the power circuit topology is decided
The closed-loop gain of the current loop is part
upon and the power circuit values are determined,
of the open-loop gain of the voltage loop. The cur-
based on the application requirements, before con-
rent loop closed-loop gain rolls off at its crossover
trol loop design begins. Occasionally, problems
frequency, fCI, adding an additional –1 slope to the
encountered in the control loop design process
voltage loop above fCI. It is best to have fCV below
may force a rethinking of these power circuit deci-
fCI to minimize this interaction.
sions. The steps in the control loop design process
The Right Half-Plane Zero: will generally proceed as follows:
In the boost and flyback topologies, the output (1) Define the control loop strategy and plot the
is driven through a diode, as shown in Figure 7. tentative goal.
The inductor current flows to the output only when
(2) Plot the known part of the loop.
the power switch is off and the diode conducts. If
load current increases, the duty cycle must be (3) Define the crossover frequency, fS.
increased temporarily to make the inductor current (4) Try to meet the goal — Define and plot the
rise. But operating in the continuous inductor cur- error amplifier and overall loop characteristics.
rent mode, when D is increased the diode Examples given in Appendix C should help to
conduction time decreases, before the slowly rising clarify this process.
inductor current has time to change. The result is
Step 1. Define the Control Loop Goal and
that the average diode current decreases at first,
Strategy:
then as inductor current rises, the diode current
Based on application requirements for line and
ultimately reaches to the proper value. This action,
load regulation and transient response, output filter
where the average diode current must actually
capacitor type. Define and crudely plot a tentative
decrease before it can finally increase, results in
goal for the overall loop characteristic. The ideal
the small-signal phenomenon known as a right
goal is shown in Fig. 6a (two active poles below
half-plane zero.[4]
crossover, one above). Several strategies for prac-
tical situations are outlined below. Implementation
RLOAD (1-D)2
ωRHPZ = (13) is shown in Appendix C.
L D Strategy #1 – The Easiest but not the Best: For
a buck-derived topology with aluminum electrolytic
A “normal” zero occurs in the left half of the
capacitor. Line and load variations are small and/or
complex s-plane, and has a gain characteristic that
slow. Use single loop Voltage Mode Control. Cross
rises with frequency, with 90° phase lead (+1
over well below 1kHz, don’t worry about slope
slope). The right half-plane zero also has a rising
matching. The only problem to deal with is that the
gain characteristic, but with a 90° phase lag (-1
loop gain varies with VIN. The result of this short
slope). This combination is almost impossible to
cut stabilization method is poor dynamic response,
compensate within the control loop, especially as
but if this is acceptable, who can argue.
the RHP zero frequency varies with load current.
Strategy #2 — How to handle large step
So most designers give up and cross over the volt-
changes in load: Output regulation in the face of a
age control loop below the lowest RHP zero
large step load change depends heavily on the out-
frequency. One argument in favor of Average
put filter capacitor by itself, backed up by the

5-21 Control Loop Cookbook

voltage control loop. In a two-loop system, the cur- designed with slope matching to optimize band-
rent loop does not provide any help in responding width and input transient response. The voltage
to a load change. In this situation with a continuous loop should then be designed to cross over at a
mode buck-derived topology, it will take several lower frequency than the current loop. Then, the
switching periods for the inductor current to slew to voltage loop will not significantly affect slope
the new value (especially for a current rise at low matching, and the roll-off of the closed current loop
VIN). While the inductor current is slew-rate limited, will be above the range of concern for the voltage
the control circuit is non-functional because the loop. The voltage loop is definitely simplified, but
amplifiers have been driven into their limits. the ESR is still there. If the variable ESR zero is in
The salvation of this problem is an electrolytic the vicinity of the desired fC, it may be necessary
output filter capacitor, especially an aluminum elec- to reduce fC to below the ESR zero frequency. The
trolytic whose C is huge because of the ESR response of the voltage loop will not be excellent,
requirement. The aluminum electrolytic does such but the aluminum electrolytic’s huge C value will
a good job of “holding the fort”, that the voltage probably handle this problem better than the best
loop bandwidth does not need to be pressed to the control loop, if the control loop gets knocked out of
limit. Thus, the current loop can be designed with action by the inductor current slew rate.
slope matching for optimum fC, and the voltage The original single-loop VMC approach would
loop designed on a strictly linear basis to cross be much more workable with Tantalum electrolyt-
over at or below the capacitor ESR zero frequency. ics, which have much smaller ESR temperature
Ceramic or polymer capacitors make a very variation. If the frequency is high enough for eco-
poor showing with large rapid load changes — nomic viability, polymer capacitors might be worth
ESR is negligible but the C value used to achieve considering.
the desired output ripple is orders of magnitude As demonstrated above, many of the problems
less than an electrolytic. A really big help is to encountered while developing a control strategy
make the inductor smaller and the capacitor bigger lead back to the power circuit components or even
– lower the surge impedance -L/C . The smaller L to complete replacement of the original power cir-
can slew the current faster, the larger C will hold cuit topology. This is to be expected, but this is
the fort longer. The increased ripple current will clearly an area where experience can help to make
raise the minimum load where discontinuous oper- the right choices the first time (or maybe the sec-
ation begins, but Average CMC can cross the ond time!).
mode boundary nicely. Step 2. Plot the Known Part of the Loop:
Strategy #3 – Large ESR Variation: An auto- After the power circuit topology and the control
motive application must operate over a wide method have been at least tentatively defined, and
temperature range and must have rapid response the power circuit values established according to
to input surges and load changes. Optimizing fC by application requirements, Make a Bode plot of the
slope matching, along with the input voltage feed- entire loop but not including the error amplifier,
forward that slope matching provides, would KEA. This plot must include the control-to-output
provide a satisfactory solution. However, an ESR characteristic plus feedback KFB. The characteris-
variation of 6:1 including initial distribution and tem- tic of the PWM, power circuit and filter must be
perature coefficient causes a 6:1 variation in loop known – see examples in Appendix C. In a two
gain and crossover frequency. The triangular ripple loop system, do the complete design of the inner
waveform which is the basis for slope matching loop first, before starting outer loop design.
varies by the same amount.
Step 3. Define the Crossover Frequency:
In this difficult situation, it is best to use Current
If slope-matching to optimize fC, the slope
Mode Control. The current loop does not contain
matching process defines the E/A gain at fS. The
the ESR, so it will be very stable and can be
crossover frequency will be optimum, but the spe-

Control Loop Cookbook 5-22

cific frequency will not be know until the next step. voltage control loop of a two-loop CMC system, or
If slope matching in a two-loop system, remember as a single-loop Voltage Mode Controller.
that each loop will contribute its share of the total Note that both circuit models include the feed-
slope. The relative share contributed by each loop back loop gain element, KFB, in addition to KEA,
determines the relative crossover frequency of the E/A gain element. This is because with the volt-
each loop. It is best to have the current loop con- age divider input, it is difficult to separate KFB from
tribute most of the slope. This will result in current KEA. The divider resistors in series form KFB, but
loop crossover frequency greater than the voltage their parallel combination forms all or part of the
loop which is desirable because the closed current E/A input resistance, which determines KEA. The
loop is contained within the voltage loop. only problem this causes is mental – KFB is part of
If fC is put at a frequency less than optimum to the Step 2 Bode plot, KEA is defined in Step 4.
avoid problems, or just because there is no need Problems Preventing Optimization: There are
for high bandwidth and fast response time in this many problems that can get in the way of achiev-
application, then subharmonic instability will not ing optimum fC. Such things as excessive ESR
occur, and loop stability can be totally handled with variation or excessive gain variation with VIN, or
Bode plots. Steps 3 and 4 meld together. Again, in with RHP zero, or insufficient amplifier bandwidth
two-loop systems, there is loop interaction. The can all add tremendous uncertainty in both gain
closed current loop within the voltage loop adds a and phase in the region near crossover, especially
pole to the voltage loop at the current loop if several factors are at play. The effects of these
crossover frequency, so it is best to have the cur- variable elements must be examined at their
rent loop cross over at a higher frequency than the extremes. Either the uncertainties must be reduced
voltage loop. to manageable proportions, or fC must be shifted to
Step 4: Try to Meet the Goal — Define the E/A a much lower frequency. But some of these prob-
and Overall Loop: lems can be reduced or eliminating by making
Since fC has been determined, E/A gain at fC different choices, including rethinking some the
is by definition the complement of the gain from decisions made regarding the power circuit:
step 2. Starting at fC, work up and down in fre- If the RHP zero is a problem in a continuous
quency, combining E/A characteristic with gain mode boost or flyback circuit, making L smaller
from step 2, to obtain overall loop gain. Tailor E/A raises the RHP zero frequency. If the smaller
gain as needed to shape the overall loop gain char- inductor means crossing into the discontinuous
acteristic working toward the ideal defined in Step mode at light loads, where peak CMC or VMC falls
1. The examples in Appendix C should help apart because of the large drop in loop gain (which
explain this process. changes the crossover frequency!), consider using
Error Amplifier Compensation Circuits: Two cir- Average CMC which adds enough gain to make
cuit models given in Appendix A will handle most discontinuous operation feasible. And the smaller
E/A compensation requirements. In most applica- inductor cost less. The penalty is increase ripple
tions, fewer poles and zeros are required, and the and noise.
circuit models can be simplified accordingly by ESR variation over a wide temperature range
omitting components. One of the two models has a with aluminum electrolytics is a tough problem to
current sense resistor input and is intended for an get around. Tantalum capacitors have much less
Average Current Mode Control loop. The “refer- variation, but they cost a lot more. Polymer alu-
ence” voltage is actually the E/A output of the minum electrolytics have no ESR, but limited
voltage loop, which sets the current level for the capacitance and low voltage rating make them
inner loop. unsuitable for most applications.
The other circuit model has a voltage divider Gain variation due to wide swings in VIN can
input and is intended for use either as the outer be eliminated using peak or average CMC.

5-23 Control Loop Cookbook

 Insufficient Amplifier Bandwidth: As switching dc cross-regulation problems.
frequencies rise, error amplifier bandwidth may not Large signal problems involve changes that
be sufficient for slope matching or optimization of are so large or so rapid that the control loop cannot
fC. If the amplifier bandwidth is not enough for the keep up. Error amplifier outputs are driven to their
desired compensation scheme, there are some limits, and the loop(s) become temporarily open.
alternatives other than backing down on the Large signal events include: start-up, input voltage
crossover frequency: (1) use an IC with a better drop-outs, rapid input voltage changes, rapid load
amplifier. (2) In the current loop, use a larger cur- current changes.
rent sense resistor or a current transformer with a All energy storage elements within the loop are
larger turns ratio. Two cascaded amplifiers can pro- likely to either become the cause of large signal
vide a very large gain increase at frequencies well problems, or to behave badly as a result. This
below their crossover frequencies. includes not only the filter inductor and filter capac-
Control Problems your Mother Never itor, but even the small compensation capacitors
Told You About around the error amplifier.
A tremendous amount of effort has been put • The inductor is the main cause of large signal
into the development of small-signal techniques problems, because of its limited ability to slew the
and linear models of the various switching power current rapidly to accommodate a large, rapid
supply topologies. Hundreds, if not thousands of load change, or during start-up or after a line volt-
papers have been written over the years. Your aca- age drop-out. In a buck regulator with increasing
demic “mother”, whoever “he” may be (note the PC current demand, di/dt = (VIND - VO). If min VIN
sexual ambiguity), typically focuses on new topolo- times max D is only marginally greater than VO, it
gies and/or linear modeling. will take forever for the inductor current to rise.
While not disparaging any of these efforts – far Even if the loop bandwidth is 1MHz — The loop
from it, these contributions have been immense is open! Under normal operating conditions, it will
and totally necessary – there has been a lack of still take several switching periods. Once the
balance and a tendency to try to force behavior inductor slews to the proper current, the filter
that is uniquely related to switching phenomena capacitor, whose voltage has sagged, takes more
into linear equivalent models (with sometimes time to recharge, further delaying loop recovery
uncertain results). Many of the major significant Soft start is helpful only during start-up. A smaller
problems with switching power supplies do not inductor certainly helps at the expense of greater
show up in the frequency domain, or in the time noise and output filtering. If the inductor is small
domain using averaged models, unless these enough for discontinuous operation, the slew rate
problems are anticipated in advance and provided problem disappears.
for in the models. Simulation in the time domain
• A unique overshoot problem can occur at startup
using switched models, although slower, reveals
unless soft start is used. Without soft-start, L and
these problems that would have been hidden:
C will start to charge resonantly toward 2xVIN, but
• Modulator gain, d/vC, varies with duty cycle D as soon as the current limit is reached, inductor
when E/A gain is adjusted to optimize fC. This current stabilizes at this value. The capacitor volt-
makes buck regulator gain independent of VIN age now rises linearly toward the desired VOUT.
provides input voltage feed-forward (Fig. 16). But the inductor current is at the current limit, and
This is a geometry problem dealing with the ripple if the load current happens to be minimal, there is
waveform at the E/A output. way too much current. It takes time for the induc-
• Subharmonic instability and the slope tor current to slew back down to the load current
compensation / slope matching solution. demand. During this time the capacitor voltage
keeps rising, above the required VOUT value. The
• Leakage inductance leading edge delay causes

Control Loop Cookbook 5-24

 overshoot is probably only a few percent with the
huge C value of aluminum electrolytics, but with
the much smaller C values that would be used
with ceramic or polymer capacitors (if frequency
is high enough to make this viable) the overshoot
can be quite large – 30-50% — requiring soft-
start to prevent this from happening. A lower L/C
ratio helps here, as well.
• It may be tempting to add a zero to the error
amplifier to boost low frequency gain and
improve accuracy. Even though the resulting
small signal plot appears optimum, adding this
capacitor in the E/A feedback can hurt more than
it helps. If a situation arises where a rapid load
current increase causes inductor current to
become slew-rate limited, the power supply out-
put will sag, and the E/A output will be driven into
its positive limit. The feedback loop is temporari-
ly non-functional. The compensation capacitor
will charge to an abnormal voltage which later will
delay recovery of the loop to normal operation.
The lower the frequency of the pole or zero
involving the compensation capacitor, the longer Figure 19. – VOUT Tolerance
it will take to recover. of fC and the loop gain at high frequency. VSS, the
Many IC’s in wide use today have error ampli- steady-state voltage deviation or error from light to
fiers whose outputs can swing from 0 to +VCC. If heavy load, is a function of the loop gain at low fre-
the sawtooth voltage against which the E/A output quency. Fig. 19a demonstrates what happens with
will be compared ramps from 1 to 4 Volts, what is very high low frequency gain resulting in minimal
the virtue of allowing the E/A output to swing to steady state error, VOUT starts near the nominal
18 V whenever the E/A is temporarily driven into its value and returns there following each load
limits by a large signal event?. change. Thus, the total swing is twice the peak
IC designers should include clamps from the value, exceeding the permissible tolerance band.
E/A output to its input to prevent the output from Figure 19c shows what happens with the high fre-
being driven significantly beyond the useful range. quency loop gain unchanged, but with low
Not only might this hasten recovery of the amplifi- frequency gain reduced to the amount necessary
er itself, the amplifier input will always remain at its to result in VSS much larger but within the toler-
normal operational level, and external feedback ance band. The initial shape and amplitude is the
capacitors will not charge to abnormal voltages same in Fig 19a and 19b, but the voltage never
and thus will not delay recovery from large signal returns to nominal because of the deliberately
events. large dc error. The required gain is easy to calcu-
It may seem paradoxical, but the VOUT toler- late, especially with current mode control inner
ance band can be cut in half by reducing the loop. If the current sense resistor is .02 Ω, then 0.2
voltage loop gain. Figure 19 shows the output volt- V E/A output swing is required for a 10 A current
age waveforms that result when the load current
changes suddenly and then, at some later time,
changes back. The magnitude of VPK is a function

5-25 Control Loop Cookbook

 Some counter arguments are: Although there
are two decisions per switching period, they affect
only one power pulse per period. Also, the two
points of decision converge upon each other at
duty cycle extremes. However, the real limitation
on crossover frequency is not related to the num-
ber of samples taken. The real limitation on fC is
the subharmonic instability which start to occur
when the slopes of the inductor ripple current
waveform seen at the error amplifier output exceed
the slopes of the sawtooth (or triangular) waveform
at the other comparator input. This slope-matching
criteria limits the E/A gain, and thereby limits the
Figure 20. – Triangular PWM Waveform gain and the crossover frequency of the entire
loop. In this regard, the triangular waveform is no
change. If the desired VOUT swing is 0.1 V (within better and perhaps worse than the sawtooth.
a 0.15 V tolerance band), then the E/A gain must Certainly it is more difficult to implement. Slope
be set at 0.2V/0.1V = a gain of 2.0. In Strategy #2 matching is much more difficult to optimize when
above, this technique would be helpful. there are two slopes to consider. The PWM com-
Triangle vs. Sawtooth PWM Waveform: parator must latch in both states, and unlatch at
In a fixed frequency PWM using a sawtooth each subsequent peak of the triangular waveform,
waveform, a switching decision is made once per otherwise the comparator will false trigger on the
switching period based on the control signal level tiniest noise pulse and will not function at all if the
at that instant when the decision is made. A sec- control signal slope exceeds the triangular wave-
ond switching action is taken at the clock pulse at form at any point.
the beginning of the sawtooth ramp, but this is not
influenced by the control signal. Thus, the duty REFERENCES:
cycle is modulated according to a single control (1) R. D. Middlebrook, “Predicting Modulator
signal sample per switching cycle. In order for the Phase Lag in PWM Converter Feedback
duty cycle to be modulated effectively by a small ac Loops,” POWERCON 8, pp. H4.1-H4.6, April
signal, it is obvious that a minimum 2 samples 1981.
must be taken during the period of the signal in (2) L. H. Dixon, “Average Current Mode Control of
order to define its amplitude. From this point of Switching Power Supplies,” Unitrode Seminar
view, the highest signal frequency that can pass SEM700 1990, reprinted in the Unitrode
through the PWM is one-half of the switching (sam- Databook, Application Note U-140.
pling) frequency. (3) J. R. Wood, “Taking Account of Output Re-
With a triangular waveform, decisions to switch sistance and Crossover Frequency in Closed
ON and OFF are each made on the basis of sepa- Loop Design,” POWERCON 10, pp. D4.1-
rate intersections of the control signal vs. the D4.16, March 1983.
triangular waveform. The argument in favor of the
(4) “The Right Half-Plane Zero – A Simplified
triangular waveform is that since two control signal
Explanation,” Unitrode Seminar SEM300,
samples are taken per switching period, the PWM
1984, Reprinted in SEM400, SEM500,
should be able to handle twice small signal fre-
SEM600, and SEM700.
quency as the sawtooth PWM. Therefore a higher
crossover frequency, greater bandwidth and
improved performance should be attainable.

Control Loop Cookbook 5-26

 The error amplifier with its associated compen- margin, and a two-pole characteristic below fc to
sation network completes the closed loop system provide a rapidly rising gain characteristic below fc.
by comparing the output voltage to a voltage refer- If fC is not limited to lower frequencies by prob-
ence at the input of the error amplifier and feeding lems such as ESR variation or right half-plane
the amplified and inverted error signal to the con- zeros, fc is ultimately limited by subharmonic oscil-
trol input of the PWM or the control input of an lation and should be optimized using the
inner loop. The compensation networks provide slope-matching technique discussed in the main
phase leads and lags at appropriate frequencies to body of this paper.
cancel excessive phase lags and leads of the The error amplifier circuits shown in Figures
power circuit. The goal is to obtain an overall loop A-1 and A-2 each apply to a broad range of cir-
gain characteristic with a crossover frequency, fc cumstances and simplify considerably in most
(where loop gain equals 1, or OdB) as high as pos- applications, by eliminating some of the feedback
sible, with a single pole (-1 slope) characteristic for elements. Figure A-1 is for use in voltage loops,
1 decade above fc to provide adequate phase either single-loop Voltage Mode Control, or the

VREF -~
KFB= ~- R1+R2

RI
R1=-
KFB

RI
R2=~

1
(l)PI= Cp(RF+Rp)

roZ1 = ~ 1

1
(J)Z2 = Cz(RI +Rz )

O)P2 = - 1
fz1 fz2

Figure A-1 -Voltage Error Amplifier

[!::!)
- 5-A1 Error Amplifier Design
ol1er loop with a Current Mode Control inner loop. In both circuits, Ap limits the dc and low fre-
Fig. A-2 is for Average Current Mode Control loops. quency gain. Making Ap infinite (by omitting it),
The compensated error amplifier gain charac- pole fp1 is eliminated, and the gain continues to
teristic has been referred to as KEA, separate and rise at low frequency until finally reaching the
distinct from the feedback factor for the entire loop, amplifier gain limit.
KFB. However, it is difficult to separate KEA and With an Average CMC current loop, only the
KFB physically, and so both of these gain elements inductor pole is active at fs. A triangular ripple
appear in Figs. A.1 andA-2. Note how, in Fig. A-1, waveform is seen across As. There is no reason
resistors A 1 and A2 in series form the voltage not to optimize the crossover frequency by slope
divider gain element KFB, but these same resistors matching. E/A gain should be flat (ApAv down to
in parallel form AI, part of the network which deter- fC, resulting in -1 slope in overall loop gain above
mines gain KEA. It is important to keep these two fc. Put zero fZ1 at fc to boost overall loop gain with
elements separate conceptually, even though they -2 slope below fc. This current loop crossover fre-
are combined physically. In Fig. A-2, the loop feed- quency will be called fcl. The closed loop gain of
back element is the current sense resistor, As. the current loop equals 1/AS and rolls off with a
Although As is physically separate and plays no pole at fCI. This pole at fcl appears in the outer volt-
role in KEA, it is shown here for the sake of consis- age loop.
tency with Fig. A-1. There are several possible scenarios for the
In most voltage loop situations, fZ2 and fp2, tl:t~ outer voltage loop, depending on whether elec-
pole-zero pair in Fig. A-1 is not required, so Az is O trolytic capacitors or ceramic/polymer (with
and Cz is omitted. negligible ESAs) are used, and where it is desired

00 -- 1
Z1 -CpRF

fz1

Figure A-2 -Current Error Amplifier

(b!]
E"or Amplifier Design 5-A2 -
to put the voltage loop crossover frequency. These Amplifier Gain limits:
are best explored by looking at the examples in After the desired ElA compensation network
Appendix C. has been designed and plotted, make sure the
The rising gain characteristic of the zero-pole intended error amplifier gain characteristic
pair fZ2 and fp2 shown in Fig. A-1 is required in the exceeds the required gain over the entire range of
voltage loop to cancel one pole when two poles are frequencies. The high frequency end of the El A
active above the proposed voltage loop crossover gain characteristic is usually a -20 dB/decade
frequency, fcv. This will occur in these circum- (-1 )slope crossing 0 dB at the specified Unity
stances: (a) With CMC, when fcv is less than 1 Gain-Bandwidth frequency. This slope terminates
decade below fcl pole, and output filter capacitor at lower frequencies at the specified open loop
ESR is negligible (capacitor pole). (b) With single- voltage gain.
loop VMC, when the proposed fcv is less than 1
Slope Compensation:
decade below output filter resonance or between Strongly recommended for all continuous
filter resonance and the ESR zero frequency mode regulators using peak current mode control,
(L and C poles). even though it is not absolutely necessary for sta-
Amplifier Output loading: bility when duty cycle is less than 50%. Ideal slope
The starting point in the design of the E/A cir- compensation is achieved by introducing a ramp
cuit is to decide upon an appropriate value for RF. whose slope equals the downslope of the inductor
Too small a value of feedback resistance and/or current ramp, as seen across the current sense
other loading on the E/A output may exceed its resistor. The ramp could be negative going, super-
source/sink output current capability, so that the imposed on the current programming voltage (the
amplifier will not be able to swing its output voltage output of the error amplifier), but it is easier to
over the necessary range. Every amplifier (whether derive a positive ramp from the existing IC oscilla-
voltage or transconductance type) has a limited tor, and add it to the current ramp. For example, a
source and sink output current capability. This is 0.2 V ramp is easily added to the current ramp by
usually defined on the spec sheet, although some- a 10:1 voltage divider taken from a 2 Volt oscillator
times indirectly as the load currents in VOUT High ramp to the top of the current sense resistor. Be
and VOUT Low tests. Don't make RF too large or careful not to load the oscillator excessively.
noise sensitivity is increased. If the E/A input is at
2.5V (reference), 25K for RF requires :l:100mA to
drive O to 5V.
Transconductance Amplifiers have high imped-
ance (current source) outputs instead of the low
impedance output of the more common voltage
amplifiers. However, with either type of amplifier,
the E/A voltage gain is established by the feedback
impedance ratio, ZFfZI, and with feedback, the
amplifier type within is indistinguishable.
Transconductance amplifiers used in early power
control IC's developed a reputation for application
problems, but this was because their source/sink
output current capability was low, not because of
the amplifier type.

(1J]
- 5-A3 Error Amplifier Design
 The Bode plot is a method of displaying com- Low Pass -Single Pole: Figure 8-1
plex values of circuit gain (or impedance). The gain
magnitude in dB is plotted vs. log frequency. Phase I 1 L
F(s) = -S ; rop =RCor R
angle is plotted separately against the same log 1+-
frequency scale. rop
Bode plots are an excellent tool for designing Gain Slope: -20 dB/decade; Phase Lag: -90° total
switching power supply closed loop systems. They
Single Zero: Has the same gain and phase char-
provide good visibility into the gain/phase charac-
acteristic as the single pole shown in Figure 8-1,
teristics of the various loop elements. Calculation
except gain increases with frequency. Gain and
of the overall loop is made simply by adding the
phase slopes are both positive.
gain expressed in dB and adding the phase angle
in degrees.
s . 1 L
The process is further simplified by using F(s) = I+ 00;: , O>z= RCor R
straight line approximations of the actual curves,
called asymptotes. Calculations are then made
only at the frequencies where the asymptotes Gain Slope: +20 dB/decade; Phase Lead: +90° total
change direction.
Bode's theorem for simple systems, which
includes most switching power supplies: The
phase angle of the gain at any frequency is depen-
dent upon the rate of change of gain magnitude vs.
frequency. A single pole (simple RC low-pass filter)
has a gain slope of -20 dB/decade above its cor-
ner frequency and has a corresponding -90°
phase shift.
First Order Filters (A-C or L-A):
Single pole or zero first order filters both have
gain slopes of 20 dB/decade above the comer fre-
quency. The phase shift asymptotes slope
45°/decade, extending 1 decade each side of the
comer frequency for a total 90° phase shift (see
Rgure 8--1).
The maximum gain error is 3 dB between exact
values (curved lines) and the straight line approxi-
mations. The maximum phase error is 5.7°. These
small errors can be safely ignored in the control
loop design.
Figure 8-1- Single Pole

I1J]
- 5-81 Bode Plots
Right Half-Plane Zero: The effective series resistance RS determines
Refers to its location on the complex s-plane. a. Rs includes capacitor ESR: Rc, inductor: RL,
The RHP zero has the same positive gain slope as rectifier dynamic: Rc, leakage inductance effective
the conventional (left half-plane) zero, but the resistance: RI, and load resistance: ROo trans-
phase slope is negative, like a single pole. Above formed into its equivalent series R.
the RHP zero comer frequency, loop gain is held a seldom reaches a value greater than 4 or 5.
up, yet more phase lag is added. This makes it vir- At full load, low Ro transforms into high Rs. At light
tually impossible to achieve an open loop loads, diode Ro limits a.
crossover frequency above the RHP zero frequen- The phase characteristic slope is approximate-
cy. Fortunately, the right half-plane zero is ly -120°/decade at a a of 0.5. At higher a values,
encountered only in boost and flyback regulators Figure 8-4 shows that the phase slope becomes
and then only when operated in the continuous much steeper, making compensation more difficult.
inductor current mode.
Phase asymptote intercepts:
F(s) = ]- -!-
COz

K =52Q
Gain Slope: +20 dB/decade; Phase Lag: -90° total

Second Order Filters (Resonant LC):

The resonant LC filter of Figure 8-2 has a 2
pole --40 d8/decade gain slope above its comer
(resonant) frequency, and a total phase lag of 180°.
The gain characteristic has a resonant peak which
varies with a, as shown in Figure 8-3. The reso-
nant effect is suppressed in the closed-loop
characteristic, although it can reduce gain margin
and cause loop instability if the resonance is close
to the crossover frequency.

Fs = I
1 + (s/roo)/Q + (S/roo)2

where roo = ..[LC ,

L
Q=roo~

~
Rs=Rc+RL+RD+RR+ RO ;

Gain Slope: -40 dB/decade; Phase Lag: -180° total

Gain peak at ~ : 20 log Q

Fig. B-2- Two-Pole Resonant

0=:!)
Bode Plots 5-82 -
 Figure 8-3- Two-Pole Resonant GAIN
Figure B-4 -Two-Pole Resonant PHASE

0:::!]
- 5-83 Bode Plots
 t.

Buck-Derived Topologies --Continuous Inductor Current

Pulse Width Modulator Gain shown here applies to all Buck topologies
PWM Gain: KMOD = d = ~ E/A gain < 1/5 of optimum:

Vc Vs
d
PWM Gain (Opt.): KMODX = =J!.-=~ Optimized EtA gain (slope-matched)
Vc Vs VSV1

(1) Average Current Mode Control Loop

Feedback Gain: KFB = Rs ; VIA effective current sense R, incl. current xfmr turns ratio

Power Circuit Gain: KMODX X KpwR = ~

Filter Gain:

Closed-Loop Gain: G1 KFB (l+sI21rfcl) ; fCloptimal)yequalsfs/21r

{2) Voltage Loop with Current Mode Control Inner Loop

Feedback Gain: ~B = ~
Vo
p Co " G oo K
ower Ircult alno PWR = -=
Vo
G I Ro =- R 1
Ro
12 f )-;
"
KMQO IS not
.
In voltage loop
s ( +s n- CI
Vcv
l+sRESRC
Filter Gain: ~c = l+sRoC

(3) Voltage Mode Control -Single Loop

Feedback Gain: ~B =
VREF
~

Power Circuit Gain: -~ ; Kuooxx ~R -- Yo

~x~
-Vs -Ys

Filter Gain: I{
"'Lc -1+$RESRC
-
1 + $.[iC IQ + $2 LC

[1:!]
- 5-C1 Small Signal Characteristics and Control Loop Examples

~
Buck Regulator Application Examples
A 1DO Watt Forward converter is used to illustrate several different approaches to closing the
feedback loop. The input voltage values are referred to the transformer secondary, making the actual
primary voltage and the turns ratio irrelevant to this procedure.
Current sensing is actually performed on the primary side of the forward converter power trans-
former. Thus, with a turns ratio of 10:1, for example, an effective sense resistance of 50 m.Q is actually
5DO m.Q (10 x 50 m.Q) on the primary side, producing a sense voltage of 1 V on the primary side for
20 A secondary side current, and with much less loss .

Application Parameters: Calculations:

Switching freq., fs; 200kHz DMAX= {Vo+VF)N,min = 0.46; DMIN = {Vo+VF)Nimax = 0.23
Input Voltage, V,; 12 -24 V
Perio~ T = 5~ec. TOFFma.= T(I-DMIN) "" 4~ec
Output Voltage, V 0; 5 Volts
Output Ripple, ~Vp.p; 0.1 V L = (Vo+VF)to~L1IMAx = 5.5~
Output Current, 10; 2 -20 A
Output Rectifier V F; 0.5 V I A/ 12xT/2
CMIN = 6Q/6Vp.p = - = 25JlF
Output Ripple, ~Ip.p; 4 A 2 A.Vp-p

Reference, V REF; 2.5 V

ESRMAX = L1V p-p/L1Ip-p = 25mQ
Current Sense, Rs: 50 mil

Oscillator Ramp, V s: 2.5 V Output Resistance. Ro = 2.5 -0.25 .0,

Two different output filter capacitor types will be explored for this application --

1. Panasonic FA Series Aluminum Electrolytic:

10V, 3300~F, 25 m.Q.max ESR, (D-16mm, H-20mm): 3300~F, 25 m.Q. max, 12 m.Q. min
RoC Output pole frequency: fo = 19.3 -193 Hz; L-C resonant frequency: fR = 1200 Hz ;
ESR Zero Frequency: fESR= 1900 -4000 Hz

2. Panasonic SP/CB Series Polymer Aluminum Electrolytic:

BV, 15~F, zero ESR, (Bmmx5.3mmx3.3mmH), TWO in parallel: 30~F
RoC Output pole frequency: fo = 2.1 -21 kHz L-C resonant frequency: fR = 12.4 kHz

The triangular inductor ripple current waveform (at the switching frequency) will retain its triangular
shape across the 3300~F Aluminum Electrolytic because its impedance at fs is the ESR resistance. In
a single loop Voltage Mode Control, if the crossover frequency, fc, is to be optimized, the Error
Amplifier gain must be flat (0 slope) from fs down to fc, to retain the triangular shape used for slope
matching, and to provide a net -1 slope in the overall loop gain to preserve adequate phase margin.
Although the waveshape is triangular, its amplitude will vary with ESR, and if ESR variation is large,
optimizing fc may be impossible.
With the 30~F Polymer Electrolytic, there are two active poles at fs. The triangular inductor current
waveform is integrated by the output capacitor, resulting in a quasi-sinusoidal waveshape. If the VMC
loop is to be optimized, The E/A characteristic must differentiate this waveform (+ 1 slope) in order to
recover the triangular waveform as well as to obtain the -1 slope needed for overall loop phase margin.

[!='J
Small Signal Characteristics and Control Loop Examples 5-C2 -
\, Forward Converter -Avg. CMC Loop -Aluminum Electrolytic

Use the previously defined Average Current Mode Control Loop equations (1 ). and the parameters of
this application:

KKKK = KMODX X KpWR x KFB X ~C = Vo VI VoRs 0.1

-x-xRs XKLC= -XKLC = xKLC
VSVI Ro VsRo Ro

I 1
ZERO to= 2-POLE Resonant f R ="2;;"JLC
21rRoC
At 10 = 20A, Ro = 0.25; KKKK = 0.4 ~c (-8 dB) ; Zero fo = 193 Hz; fR = 1200 Hz

At 10 = 2A. Ro = 2.5; KKKK = .04 ~c (-28 dB) ; Zero fo = 19.3 Hz; fR = 1200 Hz

Slope Matching Criteria -fs = 200 kHz

dVs Vs dlL (VO+VF)

-=-= Vsfs =-RsKEA =RsKEA
dt Ts dt L

Put E/A zero at fc : 30 kHz

Put E/A pole at to: 193 Hz
E/A gain at 193 Hz = 10x30K/193 = 1550 (64dB)

Using Error Amplifier Circuit A-2:

Let RF = 10K

Gain above fc = R/R. = 10 ; ...R, = 1 K

1
Zero at fc: 30kHz= ; Cp = 560pF
21t"RFCp

Pole at 193Hz =

E/A Summary -Circuit A-2:

R, = 1K, RF = 10K, Rp = 1.5M, Cp = 560pF

Time Constant RFCp = 5.61.lSec

[!:JJ
- 5-C3 Small Signal Characteristics and Control Loop Examples
 Forward Converter -A vg. CMC Loop -Polymer Electrolytic

Use the previously defined Average Current Mode Control Loop equations (1 ). and the parameters of
this application:

KKKK = ~ODX X KpWR x ~B X ~C = ~x!.LXRs XKLC = -

VSV1 Ro VsRo

l+sRoC , --. I
~c= ~ 2 " ..2-POLE Resonant fR= ~
l+s"LCIQ+s LC .21C"LC

At 10 = 20A. Ro = 0.25; KKKK = 0.4 ~c (-8 dB) ; Zero fo = 21 kHz ; fR = 12.4 kHz

At 10 = 2A. Ro = 2.5 ; KKKK = .04 ~c (-28 dB) ; Zero fo = 2.1 kHz ; fR = 12.4 kHz

Slope Matching Criteria -fs = 200 kHz

dVs Vs
~="'T;= Vsfs dlL
= ~RsKEA = (VO+VF)
LRsKEA

Put E/A zero at fc : 30 kHz

Put E/A gain below 100 Hz = 2500 (68dB)

Using Error Amplifier Circuit A-2:

Let RF = 10K

Gain above fc = AIR, = 10; :.R, = 1K

1
Zero at fc: 30kHz= ; Cp = 560pF
2nRFCp
Gain below 100 Hz = 2500 + RIAl; Rp = 2.5M

E/A Summary -Circuit A-2:

R, = 1K, RF = 10K, Rp = 2.5M, Cp = 560pF
Time Constant RFCp = 5.6~sec

.-

w
(/) -90
<
:1:
Q.

.180

Small Signal Characteristics and Control Loop Examples 5-C4 0:!1

-

~
Forward Converter- Voltage Loop with CMC -Aluminum Electrolytic

Use the previously defined Voltage Loop with CMC equations (2), and the parameters of this applica-
tion. The PWM is within the current loop and does not appear in the outer voltage loop. The low
frequency power circuit gain equals the current loop closed loop gain times load resistance:

R o .R = .05.Q ;
= G,Ro =~(I+s/21rfc,) , s Pole at fc, = 30 kHz
~WR

KKK = KpWA x KFB X ~C = Ro

&x~x. xKLC = -x
.XKLC
Rs Vo (l+snnfcl) 0.1 (l+s/21t" f CI )

l+sRESRC .
KLC = l+sRoC . Pole at f o =2iiR;;C ; Zero at f ESR=
27rRESRC

At 10 = 20A, Ro = 0.25; KKK = 2.5 ~c (+8 dB) ; fo = 193 Hz ; fESR= 1900- 4000 Hz

At 10 = 2A, Ro = 2.5; KKK = 25 ~c (+28 dB) ; fo = 19.3 Hz ; tESR= 1900 -4000 Hz

Slope matching is not used, voltage loop crosses over at 4 kHz (max fesR)'to avoid problems with
current loop crossover frequency, fC,"

Put E/A pole at to: 193 Hz

R R .012
KKK at 4 kHz =-fl-x~=-=0.12 (-18dB)
0.1 Ro 0.1
:.E/A gain at 4 kHz = 8.33 (+18dB)

E/A gain at pole to = 8.33x4000/193 = 173 (45dB)

Using E"or Amplifier Circuit A-1 :

RF. Rz = O (omit) ; Omit Cz

LetR,=1K
R1 = R/~ = 2K; R2 = R/(1-K.B) = 2K

Gain below fc = R;R, = 173; :.Rp = 173K

I
Pole at fo: 193Hz = "'i"i"i;-c-; ; Cp = 4700pF

E/A Summary- Circuit A-1:

R1 = 2K, R2 = 2K, Rp = 173K, Cp = 4700pF

Rz, RF, Cz omitted

~ 5-C5 Small Signal Characteristics and Control Loop Examples

-
Forward Converter -Voltage Loop with CMC -Polymer Electrolytic

Use the previously defined Voltage Loop with CMC equations (2), and the parameters of this applica-
tion. The PWM is within the current loop and does not appear in the outer voltage loop. The low
frequency power circuit gain equals the current loop closed loop gain times load resistance:

Ro
~WR = GIRO =R;(I+s/21t"fcl ; As = .OSQ ; Pole at fcl = 30 kHz

xKLC = QI
Rox (l+s/21rfc/)
.XKLC
(l+s/21r f CI )

fo = 21 kHz ; fCt = 30 kHz

fo = 2.1 kHz ; fcl = 30 kHz

Slope matching is not used, voltage loop crosses over at 21 kHz (max to),

Put E/A pole at max to; 21 kHz

KKK at fcl = 21 kHz = 2.5 (+8dB)

Using Error Amplifier Circuit A-1:

:.EtA gain .R at 21 kHz = 0.4 (-8d8) = F

R1+Rz
60

40

m 20
Zero: fa: 29kHz = ; Cp =220pF ~
21t"(Rr+Rz}Cz Z
< 0
For noise reduction ~

Pole at 1010: 300kHz = 21rRJCZ ' 0',

..Rr=25K -20

R1 = R/~ = SK; R2 = R/(1-~) = SK

-40
Rz = (R, + RJ -R, + 22.SK.
10 100 1K 10K 100K 1M

FREQUENCY
E/A Summary -Circuit A-2:
R1= 5K, R2 = 5K, Rz = 22.5K, RF = 10K 0

Cp = 750pF , Cz = 220pF ;-

Rp. omitted w
(/) -90
<
:1:
Q.

180

l!=:!J
Small Signal Chamcteristics and Control Loop Examples 5-C6 -
t,
Forward Converter -Voltage Mode Control- Aluminum Electrolytic

Use the previously defined Voltage Mode Control -Single Loop equations (3), and the parameters of
this application:

v v
KKKK = KMODX X KpWR X KFB X KLC = ~
xKLC = lxKLC
~xVlx--B§LxKLC=
VSVl Vo Vo

K -l+sRESRC . I
LC- l+sJLC IQ+S2 LC , 2-POLE Resonant f R =~ ZERO f ESR=
21t'RESRC

Resonant frequency fA = 1200 Hz ; ESR Zero fESR

= 1.9 kHz (.0250) ; 4.0 kHz (.0120)

Slope Matching Criteria -fs = 200 kHz

dVs Vs dJL (VO+VF )

~=T;= Vsfs = &RESRKFBKEA = L RESRKFBKEA

KEA = VsfsL
(VO+VF)RESR K = 40 (32dB)
max FB

:.Crossover, fcl' occurs where KKKK = -32 dB

From the Bode plot: fCI= 30 kHz

Put EtA zero at fJ6: 200 Hz

Using Error Amplifier Circuit A-2: 60

Rp. Rz = 0 (omit); Omit Cz
Let RF = 40K; 40
EtA Gain above 200 Hz = 40 = R/R, ; R, = 1K
m 20
'C

Zeroatfc: 200HZ=~; Cp =.03.uF) Z

< 0
(!)
R1 = R/KFB = 2K; R2 = R/(1-~) = 2K
-20
E/A Summary -Circuit A-2:12
R1 = 2K, R2 = 2K, RF = 40K, Cp = .02~F
-40
Rp, Rz, Cz omitted
10 100 1K 10K 100K 1M
Time Constant RFCp = 800~sec
FREQUENCY

~
w -90
(/)
<
:1:
no

.180

~
- 5-C7 Small Signal Chatacteristics and Control Loop Examples
 Use the previously defined Voltage Mode Control -Single Loop equations (3), and the parameters of
this application:

KKKK = KMoox X KpWA x ~B X ~C =

, .
~c= 2-POLE Resonant f R ="2;;-JLC' . fR = 12.4 kHz
l+sJLCIQ+s2LC

Slope Matching Criteria -fs = 200 kHz

Optimum crossover frequency for a buck regulator with slope matching is f/2n, or 30 kHz in this
example. However, the ripple voltage across output capacitor C is not triangular, but a quasi-sinusoid
due to double integration (L and C, ESR is negligible). The E/A must differentiate the waveform across
C to recover the triangular waveshape at the PWM comparator input.

:.Crossover, fc" will occur at 30 kHz

KKKK at 30kHz = 1x(12.4kHzl30kHz)2 = 0.17

:.E/A gain at 30kHz = 1/0.17 = 5.8 (15dB)

Put E/A double-zero at fR: 12.4 kHz
E/A gain at fR = 2.4 (7.6dB); at fs = 38.6

60

40
~

m 20
"0
~
Z
< 0 - lKKKK
Zero at fR: 12.4 kHz= 21t"(R1 ;Rz )Cz f!J
KOA
Cz = 1200 pF
-20
R, = 500n -high freq. pole for noise reduction:
TO
Pole: f~(R,+RJ/R, = 260 kHz -40
R1 = R/KF8 = 1 K; R2 = R/(1-KF8) = 1K 10 100 1K 10K 100K 1M

FREQUENCY

E/A Summary -Circuit A-2:12

0
R 1 = 1 K, R2 = 1 K, Rz = 10K, RF = 25K
;-
Cp = 510 pF, Cz = 1200 pF
w -90

v
(/) ~
Rp omitted <
:1:
Q.

-180

[!:J]
Small Signal Chalacteristics and Control Loop Examples 5-C8 -
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