EE276 – Digital Electronic Circuits

Decoder, Encoder, Multiplexer

 Content

• Decoder
• Encoder
• Multiplexer
DECODER
 Decoder
• Decoding - the conversion of an n-bit input code to
an m-bit output code with
n  m  2n such that each valid code word
produces a unique output code
• Circuits that perform decoding are called decoders
• Here, functional blocks for decoding are
– called n-to-m line decoders, where m  2n, and
– generate 2n (or fewer) minterms for the n input variables
Decoder Examples
• 1-to-2-Line Decoder

• 2-to-4-Line Decoder
A0
A1 A0 D0 D1 D2 D3
A1
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

(a)

▪ Note that the 2-to-4-line

decoder made up of two
1-to-2- line decoders and
4 AND gates. (b)
5
Contd..
3-to-8-Line Decoder
4-to-10 line decoder with inverted outputs
BCD to Decimal Decoder

input to the decoder - BCD digit

one of the output lines will go low

– indicates which of the 10 decimal
digit is present
Contd…

4-to-10 line decoder.

n- to 2n line decoder with enable input (Demultiplexer)
• If En = 1, only one output is asserted at a time
• One-hot encoded output
– m-bit binary code where exactly one bit is set to 1

y0 = wn −1'...w1' w0' En
w0 y0 y1 = w n −1'...w1' w0En
n
2n y 2 = w n −1'...w1w0' En
inputs
wn – 1 outputs
...
y2n – 1
Enable En y 2n −1 = w n −1...w1w0En
Example: 2-to-4 Decoder with Enable input

En w1 w0 y0 y1 y2 y3
w0
1 0 0 1 0 0 0 y0
1 0 1 0 1 0 0 w1
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 x x 0 0 0 0 y1
(a) Truth table

y2

w0 y0
w1 y1 y3
y2
En y3 En

(c) Logic circuit

(b) Graphic symbol
Example:

Decoder enabled when E = 0 –

active-low enable.

Only one output = 0 at any given

time , other outputs = 1.
(c) Logic circuit
Output 0 represents the
minterm selected by the inputs
A and B.
Larger Decoder Circuit
• Decoder with enable inputs – connected together to form a larger
decoder circuit.
3 – to -8 line decoders with enable inputs connected forms a 4 – to -
16 line decoder.

W = 0, top decoder enabled, other is disabled

– bottom decoder outputs are all 0’s
– Top decoder outputs generate
minterms 0000 to 0111.

W = 1:reverses the enable condition

– bottom decoder outputs generate
minterms 1000 to 1111
– outputs of the top decoder are all 0’s.
Decoder-based Combinational Circuits
1-bit Binary Full Adder
S(X , Y, Z) =  m(1, 2, 4, 7)
C ( X , Y , Z ) =  m(3, 5, 6, 7)
 Contd..

Decoders with inverter outputs –

NAND gates can be used to realize
the given function.
ENCODER
Encoder
Opposite of decoders
Encode given information into a more compact form
Binary encoders
2n inputs into n-bit code
Exactly one of the input signals should have a value of 1,
and outputs present the binary number that identifies which
input is equal to 1
Use: reduce the number of bits
(transmitting and storing information)

w0
y0

2n n
inputs outputs
yn – 1
w2n – 1
 Octal to binary Encoder
Eight inputs – three outputs – only one input = 1 at any given time.

Two active inputs produce undefined combination as output.

Priority Encoder
➢ If more than one input value is 1, then the encoder just designed does not
owork.
➢ One encoder that can accept all possible combinations of input values and
produce a meaningful result is a priority encoder.
➢ Among the 1s that appear, it selects the most significant input position (or
the least significant input position) containing a 1 and responds with the
corresponding binary code for that position.

Priority encoder with 4 inputs

(D3, D2, D1, D0) - highest
priority to most significant 1
present - Code outputs A1, A0
and V where V indicates at
least one 1 present

Xs in input part of table represent 0 or 1; thus table entries correspond to product

terms instead of minterms. The column on the left shows that all 16 minterms are
present in the product terms in the table
Contd…
 Contd..
Eight inputs – three outputs – only one input = 1 at any given time.
Octal to binary encoder
More than one input = 1, output defined using a priority scheme.

Example: if inputs y1,y4 and y5 = 1, output abc = 101.

X’s – don’t cares.

Output d = 1, if any input is 1, otherwise d = 0. – required to distinguish the

case of all 0 inputs.
MULTIPLEXER
 Selecting
• Selecting of data or information is a critical function in digital
systems and computers

• Circuits that perform selecting have:

– A set of information inputs from which the selection is made
a single output
– A set of control lines for making the selection

• Logic circuits that perform selecting are called multiplexers

 Multiplexers
A multiplexer routes (or connects) the selected data input to the
output.

The value of the control inputs determines the data input that is
selected.

A multiplexer has
❑ 2n data inputs
❑ n control inputs
❑ 1 output
2-to-1 Multiplexer

Y Y

S S
Data S
inputs
Control
input
2-to-1 Multiplexer

Y = S′.I0 + S.I1
4-to-1 Multiplexer
Y = S1′.S0′.I0 + S1′. S0.I1 + S1. S0 ′.I2 + S1. S0.I3
Y

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I
3

m0 = S1'. S0'
m1 = S1'. S0
m2 = S1. S0'
m3 = S1. S0
 8-to-1 Multiplexer
Y = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

0
212
22

Y
MSB LSB

A B C Y
Y
0 0 0 I0 m0
0 0 1 I1 m1 Logical diagram
0 1 0 I2 m2
0 1 1 I3 m3
1 0 0 I4 m4
1 0 1 I5 m5
1 1 0 I6 m6
1 1 1 I7 m7
2n-to-1 Multiplexer

Y
Y
20
2n-1

mk: minterm of the n control variables.

Ik – corresponding data input.
Enable inputs
Many devices have an additional enable input, which activates or deactivates
the devices

2-to-1 multiplexer can be designed with an enable input:

➢ EN=0 disables the multiplexer, which forces the output to be zero.
➢ EN=1 enables the multiplexer

EN Enable
EN S Y
I0 0 X 0
2-to 1 Y 1 0 I0
I1
MUX 1 1 I1

Data inputs S

Control input
Contd..
EN
Active low enable input, Mux=1 when EN=0

EN S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 X X 1
Multiplexer Width Expansion
Quadruple 2-to-1 MUX – to select one of two 4 bit data words.

Four multiplexers – each capable of selecting one of two input lines.

A = 0; x0x1x2x3 – will appear at the z0z1z2z3 outputs.

A = 1; y0y1y2y3 – will appear at the z0z1z2z3 outputs.

Contd..
Multiplexer – a decoder that includes OR gate within the unit.
Contd…
Several logic signals that perform a common function – grouped together to form
a bus.

Bus – represented by a single heavy line instead of drawing individual wires.

Quad MUX with bus inputs X and Y, bus output Z.

X - x0x1x2x3 Y = y0y1y2y3 Z = z0z1z2z3

A = 0 , signals on X bus appear on Z bus.

A = 1, signals on Y bus appear on Z bus.

MUX with active high input and active low input, MUX with enable inputs.
Combinational Logic Implementation
- Multiplexer-Based approach
▪ Design:
• Find the truth table for the functions.
• In the order they appear in the truth table:
▪ Apply the function input variables to the multiplexer inputs Sn
- 1, … , S0
▪ Label the outputs of the multiplexer with the output variables
• Value-fix the information inputs to the multiplexer using the
values from the truth table (for don’t cares, apply either 0 or 1)
Examples
Implementing Boolean functions of n variables with a MUX
Example
Example of Binary Adder

S(X , Y, Z) =  m(1, 2, 4, 7)
C ( X , Y , Z ) =  m(3, 5, 6, 7)
Alternate Implementation of Binary Adder