I/O Systems

I/O system (Section) provides a means by

which a computer Communicates with the
outside world.

Data transmission to/from outside world

can be achieved through the use of Parallel
or Serial Communication ports.
 Parallel I/O Ports
- Data is transferred in parallel form i.e. All
data bits are transferred simultaneously
along separate lines.

-Much faster transmission speed.

-However limited to very short distances
i.e. impedance increases with many lines
bundled together carrying a.c. data
 Parallel I/O Ports Implementation

With Memory and Parallel I/O Ports in the

same system ways had to be developed for
distinguishing Memory from I/O ports.

-Three techniques are used.

 1. Isolated I/O Ports
In this scheme memory and I/O Ports are
decoded separately through the use of separate
address and data buses. The memory section
uses the entire memory range of the CPU. The
I/O section has its own address space.

Main Advantage: It provides a clear

distinction between I/O ports and Memory
sections of a computer system.
 1. Isolated I/O Ports…
Disadvantages:
-Extra decoding circuitry to distinguish
memory from I/O operations
-Special line required on the CPU to select
either the I/O Bus or Memory Bus i.e. the IO/M
line on Intel 8085 CPU.

-Special instructions required for I/O operations

1. Isolated I/O Ports…
 2. Memory Mapped I/O Ports
In this scheme memory and I/O ports share
the same computer memory map. I/O ports
occupy different memory addresses.
Memory and I/O ports are only
distinguished by memory addresses they
occupy.
 2. Memory Mapped I/O Ports…
Advantages:
-Same decoding circuitry for both memory and
I/O ports

-Same instructions used for both memory and

I/O operations. Example STA 3000H stores the
content of the accumulator to memory in case
memory address 3000H is occupied by a
memory chip OR sends the content to an output
port in case the address is occupied by an I/O
port
 2. Memory Mapped I/O Ports…
Disadvantages:
- An I/O port can occupy an entire memory
block of the computer memory space.
- Use of same instructions for both I/O and
memory operations does not distinguish
memory from I/O operations. Can be
confusing when going through a source
program.
 2. Memory Mapped I/O
Ports…(Address Decoder Outputs)
2. Memory Mapped I/O Ports…
 3. Attached I/O Ports
In this scheme I/O ports are attached to
memory chips:

Advantage:
Fewer chips required to develop a
system. Ideally suited for systems
where system small size is critical.
 3. Attached I/O Ports…
Disadvantages:
- Memory chips with attached ports are
more expensive
- Extra decoding circuitry to distinguish
memory and I/O operations
- Special line required on the CPU to select
either the I/O Bus or Memory Bus
- Special instructions required for I/O
operations
 3. Attached I/O Ports…
Examples :
- Intel 8155 is a 256 RAM chip with 3
I/O ports. Referred to as a
Programmable Peripheral Interface
(PPI).

- Intel 8355 is a 2 KB ROM chip with 2

I/O ports
 Programming I/O Ports
Writing programs that use I/O ports
might involve programming of the
parallel ports in use.

This is normally done through the use of

Control Registers provided on the chip
housing the I/O ports.
Intel 8155 PPI
Intel 8155 PPI…
 Intel 8155 PPI…
As can be seen the Chip has two sections i.e.
The RAM section and the I/O section. This
falls into the attached I/O ports category. Ports
A and B have 8 bits each. Port C only has 6
bits

The IO/M line is used to distinguish the access

section. When it is low the RAM section is
selected. When it is high the I/O section is
selected.
 Intel 8155 PPI…
The I/O ports can be programmed for
either input or output operations. For this
PPI all bits on the same port can be
programmed for the same direction. You
can not have bits of the same port
programmed for different data direction.

The PPI is equipped with a Command

Status Register (CSR)
Intel 8155 PPI CSR
 Intel 8155 PPI CSR…
Bits 0 to 3 of the CSR determine the Data
Direction of respective ports. Value 0
means Input and 1 implies Output.

For instance writing a 0 to PA (bit 0 of

CSR) implies all 8 bits of Port A are
programmed for input operations only i.e.
can only be used for input operations.
 Intel 8155 PPI CSR…
Note how port C is slightly different
from Port A and B. it has 2 bits in the
CSR.
To program all bits of Port C as Input
00 has to be written to PC1 and PC2.
whereas 11 to these bits means all the 6
bits are to be used as Output.
 Intel 8155 PPI Port Addresses
The relative addresses for the I/O ports
within the Chip are as follows:
Port Address
CSR 00H
Port A 01H
Port B 02H
Port C 03H
 Intel 8155 PPI Port Addresses…
However the Physical addresses in a system
depends on the memory block occupied by the
PPI. In case the PPI occupies a memory block that
starts at address 2000H the physical addresses for
the ports are as follows: :
Port Address
CSR 20H
Port A 21H
Port B 22H
Port C 23H
Intel 8155 PPI Port Addresses…
In case the PPI occupies a memory block
that starts at 2800H the physical addresses
are as follows: :
Port Address
CSR 28H
Port A 29H
Port B 2AH
Port C 2BH
 Programming Intel 8155 PPI Ports

Suppose Port A of the PPI occupying the

memory block that starts at 2000H is to be
used for Input operations and Port B as
output. CSR bit pattern should be as
follows:
TM2 TM1 IEB IEA PC2 PC1 PB PA
0 0 0 0 0 0 1 0

This corresponds to 02H

Programming Intel 8155 PPI Ports..

The CSR (at port 20H) can be written to by

sending data to its port address:

MVI A,02H ; Desired bit pattern to

OUT 20H ;Define Port A as input port
;and Port B as Output port
 Intel 8355 ROM I/O Ports

This chip is another example of attached

I/O ports scheme. It has 2KB of ROM and
2 parallel ports i.e. Port A and B

Unlike the 8155 PPI that has a single CSR

for all ports, the 8355 has a Data Direction
Register (DDR) for each port enabling the
programming of port bits individually.
Intel 8355 ROM I/O Ports..
Intel 8355 ROM I/O Ports..
 Intel 8355 ROM I/O Ports..
The Data Direction Register of each port has the
following bit definition with Dn meaning bit n
for the Port it controls:

7 6 5 4 3 2 1 0
D7 D6 D5 D4 D3 D2 D1 D0

A 0 on a DDR bit implies the corresponding port

bit is for input operation while a 1 means the
corresponding port bit is for output operation.
Intel 8355 ROM I/O Port Addresses

The relative addresses for the I/O ports

within the Chip are as follows:
Port Address
Port A 00H
Port B 01H
DDRA 02H
DDRB 03H
Intel 8355 ROM I/O Port Addresses
However the Physical addresses in a system depends
on the memory block occupied by the chip. In case the
chip occupies a memory block that starts at address
0000H the physical addresses for the ports are as
follows: :
Port Address
Port A 00H
Port B 01H
DDRA 02H
DDRB 03H
Intel 8355 ROM I/O Port Addresses
In case the chip occupies a memory block that starts at
say address 0800H the physical addresses for the ports
are as follows::
Port Address
Port A 08H
Port B 09H
DDRA 0AH
DDRB 0BH
Programming Intel 8355 ROM I/O Ports

Suppose bit 0,1,5, 7 of Port A are to be used as

input bits and bits 2,3,4, and 6 of the same port are
to be used as output bits. The Data Direction
Register for port A must be programmed with the
following values:
7 6 5 4 3 2 1 0
0 1 0 1 1 1 0 0

This corresponds to 5CH.

 Programming Intel 8355 ROM I/O
Ports..
This 5CH bit pattern has to be written to the Data
Direction Register for Port A. Assuming the chip
occupies the memory block that starts at address
0000H the required instruction sequence is:

MVI A,5CH ; Desired bit pattern to

OUT 02H ;Define bits 0,1,5 and 7 of
;Port A as input bits with
;the rest as output bits
 The Intel 8255 PPI

This is a Programmable Peripheral

Interface chip that holds 3 parallel I/O
ports i.e. Port A, Port B, and Port C, and a
Control Register that is used to program
the data direction for ports. Port C has two
parts that can be programmed separately.
Ir can be used in both memory mapped
I/O Scheme and Isolated I/O scheme.
The Intel 8255 PPI…
 The Intel 8255 PPI Port Addresses

The relative addresses for the I/O ports

within the Chip are as follows:
Port Address
Port A 00H
Port B 01H
Port C 02H
Control Reg. 03H
 The Intel 8255 PPI Port Addresses
However the Physical addresses in a system
depends on the memory block occupied by
the PPI. On the MPT 809 Trainer the PPI
ports actual physical addressee are:
Port Address
Port A 40H
Port B 41H
Port C 42H
Control Reg. 43H
The Intel 8255 PPI Control Word
 The Intel 8255 PPI Control Word

On the 809 MPT the Control word is

specified by the previous figure. For
example Writing a 0 to bit D4 defines
all the bits of Port A as output bits. On
the hand Writing a 0 and 1 to bits D3
and D0 respectively defines the Upper
4 bits of port C as Output and the
lower 4 bits of Port C as Input.
 Programming the Intel 8255 PPI ports

For example to define Port A as

Output, Port B as output, and the entire
port C as Input the Control Word bit
pattern is as follows:
D7 D6 D5 D4(PA) D3(PCU) D2 D1(PB) D0(PCL)
1 0 0 0 1 0 0 1

This corresponds to 89H

Programming the Intel 8255 PPI ports…

This bit pattern has to be written to the

Control Register at address 43H (MPT
809). The sequence of instructions is as
follows:

MVI A, 89H ;Desired bit pattern to

OUT 43H ;define Port A and B
;as Output and entire
;Port C as input
 Application of Parallel I/O ports

Parallel I/O ports are used in a lot of

applications in real life. For this course
we look at the following application:
- LEDs/lights Control
- Keypad Interfacing
- 7-segment LED display Unit control
MPT 809 16 LEDS Control
 MPT 809 16 LEDS Control…
From the circuit it is Clear that the
High Address 8 LEDS can only light
up if transistor Q2 is ON and
appropriate bit values are on Output
port B of the 8255 PPI. Transistor Q2
Can be turned on by sending Logic 0 to
bit 7 of Output port A of the PPI that is
connected to the base of transistor Q2.
 MPT 809 16 LEDS Control…
Similarly the Low Address 8 LEDS
can only light up if transistor Q3 is ON
and appropriate bit values are on
Output port B of the 8255 PPI.
Transistor Q3 Can be turned on by
sending Logic 0 to bit 6 of Output port
A of the PPI that is connected to the
base of transistor Q3.
 MPT 809 16 LEDS Control…
Note that both banks of LEDs rely on the output
of the same Port B. To display all the 16 LEDs
‘simultaneously’ one must first display High
address bank LEDs info for a short time, turn Off
the LEDS, then Display Low Address bank
LEDs info for a short time then turn OFF the
LEDs and Repeat the process all over again. If
this is done at a fast rate the human eye is fooled
into seeing continuous display of the 16 LEDs
info. The following flow chard illustrates this
process.
MPT 809 16 LEDS Control…
 MPT 809 16 LEDS Control…
Example:
Write a program that continuously lights up all
the 16 Address LEDS of the MPT 809.

The MPT has a DELAY routine at ROM address

00ABH that provides a 5 msec Delay without
affecting any CPU registers.
NOTE: A LED turns on when logic 0 is at its
Control Output bit of the PPI.
Example Flow Chart
 Homework
- Draw the Flow chart for the example
Question.

- Develop the Assembly Language for the

program.
- Assemble the program and test it on the
MPT
 LEDS Control..
The Program Header
Label Mnemonic Comment
NAME LEDS ;Program Name

PORTA EQU 40H ;8255 PPI Port A (Switch Port) Address

;on the MPT 809

PORTB EQU 41H ;8255 PPI Port B (LEDS Port) Address

CTREG EQU 43H ;8255 PPI Control Register Address

ORG 0C100H ;Program Starting Address

 LEDS Control..
Stack and Port Direction Definition
LXI SP,0C200H ;Initialise Stack Pointer

MVI A,89H ;The bit Pattern to

OUT CTREG ;Define Both Ports A and B as Output

 LEDS Control...
Initialise Pattern and Turn OFF LEDS
LXI H,0FFFFH ;LEDS display info bit pattern

MVI A,0C0H ;Bit pattern to

OUT PORTA ;Turn OFF both LEDS banks

 LEDS Control...
Display Upper Bank LEDS Info Section
SHOW: MOV A,H ;Get upper bank LEDs Info

CMA ;Put it in LEDS ON format

OUT PORTB ;Send Info to LEDS Port

MVI A,40H ;Bit pattern to

;
OUT PORTA ;Turn on Upper Bank LEDS info
CALL WAIT ;Wait for a while

MVI A,0C0H ; Bit pattern to

OUT PORTA ;Turn Off both LEDs Banks

 LEDS Control...
Display Lower Bank LEDS Info Section
MOV A,L ;Get Lower bank LEDs Info

CMA ;Put it in LEDS ON format

OUT PORTB ;Send Info to LEDS Port

MVI A,80H ;Bit pattern to

;
OUT PORTA ;Turn on Lower Bank LEDS info
CALL WAIT ;Wait for a while

MVI A,0C0H ; Bit pattern to

OUT PORTA ;Turn Off both LEDs Banks

JMP SHOW ;Continue Displaying Info

 LEDS Control...
Delay Implementation Section
WAIT: LXI D,0681H ;Reference Count for 20 msec Delay

LOOP: DCX D ;Count down

MOV A,D ;Get Upper Byte of Count

ORA E ;Is 20 msec over?

;
JNZ LOOP ;No – keep counting down

RET ;Return to calling program

END ;End of source program

 DELAY Reference Count
Number of States in the Standard DELAY
Loop:
10 + (6 + 4 + 4 + 10) N – 3 + 10
= 24N + 17
Given CPU frequency of f
1 State → 1/f i.e. time for 1 state
For desired Duration, D
24N + 17 → D
 DELAY Reference Count..
→ N = (D.f – 17) / 24
For desired delay of 20 msec and f = 2Mhz
N = (20 x 10-3 x 2 x 106 – 17) / 24 =
= 1665 Truncated
= 0681H
This is the Loop counter in Reg. pair D to
produce the desired delay
 Exercise

1.Develop a Program for the MPT 809 that lights all

the 16 LEDS in a flashing manner. i.e. Ligh up all
the LEDs for 1.2 seconds then turn off the LEDS for
0.5 second. Do this endlessly.

2. Develop a program for the MPT 809 that has 3

LEDS running from Right to Left at 0.3 second
interval. Produce wrap around effect i.e. The MSB
LED goes to tthe LSB position.