Unit II – Combinational Circuit

Analysis and Circuit Families

Syllabus
• Unit II – Combinational Circuit Analysis and Circuit Families
Combinational Circuit Analysis: NMOS Inverter and CMOS Inverter
Design & Analysis, Alternative Forms of Pull-up for Combinational
Circuits, Pull-up and Pull-down Ratios, Interconnect -Resistance,
Capacitance, Delay, Power Dissipation, Circuit Families: Pseudo
NMOS, Static CMOS, Dynamic Circuits, Domino Logic, Pass Transistor
Circuits, Transmission Gates, Complimentary Pass Transistor Logic
(CPL).
Contents
• NMOS Inverter
• Alternative Forms of Pull-up for Combinational Circuits,
• CMOS Inverter Design & Analysis,
• Power Dissipation,
• Other forms of CMOS: Pseudo NMOS,
• Static CMOS,
• Dynamic Circuits &Domino Logic,
• Pass Transistor Circuits,
• Transmission Gates,
• Complimentary Pass Transistor Logic (CPL).
• Pull-up and Pull-down Ratios,
 Inverter
• A basic requirement for producing
complete range of logic circuits
• It is required to convert NAND,NOR to
AND, OR gates vice versa.
• Basic inverter requires:
• A transistor with source connected to
ground
• A load is connected to positive supply (Vdd)
• Output is taken from the junction of above
two( load and transistor)
General Logic Circuits Realization
NMOS Inverter with Depletion Load
Nmos-Depletion transistor: Even channel exists
for zero gate voltage (Vgs = 0)
• Gate is connected to load and Always ON device
Pull-up • Here it is used as Pull-up tr. and connected to
Vdd.
Nmos-Enhancement transistor: no channel exists
for zero gate voltage.
Here it is Pull-down tr. and connected to ground
Pull-down
Operation:
if Vin = 0, then pd = OFF, and pu = ON, then Vo = Vdd = 1.
if Vin = 1, then pd = ON, and pu = ON, then Vo = Vss =
gnd = 0
 Nmos inverter-Characteristics
Superimposing of Nmos en.tr and Nmos dep.tr characteristics Transfer Characteristics of NMOS inverter
NMOS Inverter with Depletion Load features
• Whenever Vin = logic 1, both Pd and Pu transistors are ON
• Then Vdd is directly connected to VSS (Gnd).
• Large static current flows between power rails, hence static power
dissipation is produced.
• This inverter gives Non- zero output due to threshold voltage drop
Alternative forms of Pull-Up
1. Resistive pull-up
2. NMOS Depletion transistor as pull-up (already discussed)
3. NMOS Enhancement transistor as pull-up
4. PMOS transistor as pull up (CMOS)
 NMOS Inverter with Resistive pull-up
• Resistor as Pull-up
• NMOS- Enhancement as pull down
• Operation:
• If Vin = 0, Pd.tr =OFF,
then Vo = Vdd =1
• If Vin = 1, Pd.tr =ON,
then Vo = Gnd =0

Drawbacks:
Resistor occupies more silicon area
When Vin = Logic1, Vdd is connected to gnd, then static power is dissipated
NMOS Inverter with Resistive pull-up
Characteristics
 NMOS Inverter with Enhancement transistor pull-up
• Pull-up is Nmos Enhancement Transistor gate
terminal is connected to Vdd. So always ON.

• Pull-down also Nmos Enhancement

transistor.

• Operation:
If Vin = 0, then Pu Tr. = ON and Pd. Tr = OFF,
Then Vo = Vdd= Logic 1.

If Vin = 1, then Pu Tr. = ON and Pd. Tr = ON,

Then Vo = gnd or Vss = Logic 0.

When Vin = 1, both transistors are ON, Vdd is

connected to VSS 🡪 static Current🡪 Static
Power dissipation
CMOS Inverter
• Pull- Up is PMOS
• Pull-Down is NMOS
• Common input is applied
• At junction of NMOS and
PMOS, output is taken.
CMOS Inverter Operation
Operation:
• If Vin = 0, Pu tr. =ON,
Pd tr. = OFF,
then Vo = Vdd = Logic 1 .

• If Vin = 1, Pu tr. =OFF,

Pd tr. = ON,
then Vo = Vss = Logic 0
CMOS Inverter Characteristics
CMOS Inverter-Regions of Operation
• Region-1: In this region the input is in the range of (0- to - Vtn).
• Since the input voltage is less than Vtn, the NMOS is in cutoff region.
• No current flows from Vdd to Vss, The entire Vdd will appear at the Output terminal.
NMOS is in cutoff as Vgs < Vtn
PMOS is in linear as |Vgsp| > |Vtp| and |Vdsp| < |Vgsp –Vtp|.
• Zero current flows from supply voltage and the power dissipation is zero.

• Region-2: In this region the input is in the range of (Vtn – to - Vdd/2).

• Since the input voltage is greater than Vtn the NMOS is conducting and it jumps to
saturation as it has large Vds across it (Vout is high).
• PMOS still remains in the linear region
NMOS is in saturation as Vgs > Vtn and Vout > Vin - Vtn.
PMOS is in linear region as |Vdsp| < |Vgsp -Vtp.|
• since both the transistors are conducting some amount of current flows from supply in this
region.
• Region-3 : In this region the input voltage is (Vin = Vdd/2 )
• At this point the output voltage is also Vdd/2 as one can see in figure.
• At this voltage both the NMOS and PMOS are in saturation and the output drops drastically from Vdd to
Vdd/2.
• At this point a large amount of current flows from the supply. Most of the power consumed in CMOS inverter
is at this point.
• So care should be taken that the Input should not stay at Vdd/2 for more amount of time.
NMOS is in saturation as Vgs > Vtn and Vout > Vin - Vtn.
PMOS is in saturation as |Vgsp| > |Vtp| and |Vdsp| > |Vgsp –Vtp|.
• Large amount of current is drawn from supply and hence large power dissipation.
• Region-4 : In this region the input voltage is in the range of (Vdd/2 , Vdd-Vtp).
• Here the PMOS remains in saturation as Vout < Vin - Vtp and Vgsp < Vtp.
• But the NMOS moves from saturation to linear region since the drain to source voltage now is less than
Vgsn-Vtn.
NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.
PMOS is in saturation as |Vgsp| > |Vtp |and |Vdsp| > |Vgsp –Vtp|
• A medium amount of current is drawn as NMOS is in linear region and power dissipation is low.
• Region-5 : In this region the input voltage is in the range of (Vdd-Vtp, Vdd).
Here the PMOS moves from saturation to cutoff as the Vgsp is so high that
Vgsp > Vtp.
• The NMOS still remains in linear as the drain to source voltage now is less
than Vgsn-Vtn.
NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.
PMOS is in cutoff as |Vgsp| <| Vtp|
• Zero current flows from the supply and so the power dissipation is zero.
• Now that we have clearly understood the voltage transfer characteristics
and operation of an NMOS,
Power Dissipation
Advantages of CMOS
• It can pass both logic levels as Strong ‘0’ and Strong ‘1’
• Zero static power dissipation i.e extremely low power consumption
• Faster switching time i.e speed is more( smaller rise & fall times)
While CL discharging , the Vdd is trying to charge the CL
through pull-up,
then effective current of discharging = id-ic
Where, id= discharging current
ic-= charging current
Smaller currents 🡪 longer fall time

In case of CMOS:
No static current from Vdd.
while CL discharging
Discharges early 🡪 smaller fall time
Disadvantages of CMOS
1. BJT faster than CMOS, because of high trans-conductance.

2. CMOS cannot drive large interconnect capacitance (CL).

• The disadvantages of CMOS can be overcome by BJT

• Faster and able to drive large load capacitance
• High driving current capability
• But more power dissipation
• So entire VLSI circuit cannot be realized by BJT
• Remedy: Bi-CMOS= BJT +CMOS
Bi-CMOS Inverter
• BICMOS logic circuits are made by combining the CMOS and bipolar
IC technologies. These ICs combine the advantages of BJT and
CMOS transistors in them.
• We know that the speed of BJT is very high compared to CMOS.
However, power dissipation in CMOS is extremely low compared to
BJT.
• By combining such advantages, we construct the BICMOS circuits.
Bi-CMOS Inverter • Vin = 0, T3 = ON 🡪 T1 = ON,
T4 = OFF 🡪 T2 = OFF
Vo=VDD=1
• Vin = 1, T3 = OFF 🡪 T1 = OFF,
T4 = ON 🡪 T2 = ON
Vo = GND = 0

Draw backs
When Vin = logic 1,
Vdd is shorted to Gnd 🡪 Static power dissipation.

No discharge path for base currents of T1 and T2

speed reduces
Modified Bi-CMOS Inverter
• NMOS transistor T4 has its drain
connected to the output terminal rather
than to +VDD.
• As before, when T3 is turned ON, T1 is
also turned ON.
• Now, when T4 is turned ON, we
find T2 also to turn ON..
Modified BICMOS Inverters
CMOS Inverter Bi-CMOS Inverter

Charging

Discharging
Bi-CMOS Advantages
• Bi-CMOS has the advantages of both the BJTs and CMOS
gates.
• The power driver (BJT amplifier) in the output stage is
capable of driving large loads.
• The circuit, because of its CMOS input transistors, has high
input impedance.
• The output impedance of the circuit is low.
• The noise margin is high because of the CMOS input stage.
• The chip area is small.
Combinational Gates Realization
Combinational gates realization: basics
•
 NAND Gates

NMOS –resistive pullup NMOS –Depletion pullup NMOS –Enhancement pullup CMOS
 NMOS-NOR Gates

NMOS –resistive pullup NMOS –Depletion pullup NMOS –Enhancement pullup

CMOS NOR gate
•

A B N1 N2 P1 P2 Y
0 0 OFF OFF ON ON 1
0 1 OFF ON ON OFF 0
1 0 ON OFF OFF ON 0
1 1 ON ON OFF OFF 0
NMOS AND Gate
CMOS AND Gate
NMOS OR Gate
CMOS OR Gate
XOR Gate
XNOR Gate
General Boolean Expression
General Boolean Expression
General Boolean Expression
Realization of Y= AB+CD

•
Home Work
•
• Switch logic based on the ‘pass
transistor’ or ‘transmission
gates’.
• It is fast form small arrays
• No static current from supply
rails
• Power dissipation is small since
current only flows ON
switching.
AND Logic using NMOS switches

Vout =Vin when A.B.C.D.E.F.G.H = 1

CMOS 5-way Selector
NMOS 3-input OR gate
NMOS Switch
PMOS Switch
• Transistor switch on when

• Transistor switch OFF when

• Output for zero, it gives +Vt

Ex. Degradation in pass transistor logic

• NMOS gives Strong zero and Weak One

• PMOS gives Strong one and Weak zero
• Overcome by Transmission gate
Complementary signal are required to drive it
2:1 MUX using transmission gate
Other forms of CMOS Logic
 1.Pseudo NMOS Logic gates
• It is same as NMOS logic
• Pull down n/w is same as CMOS
• Pull up n/w is replace with a single
Inverter NAND gate PMOS- gate is connected to
gnd-permanently ON
• Small size of pull-up and less no of
transistors.
• No need to give inputs for pull up
• Whenever pull-down and pull-up are
ON, static current 🡪 static power
dissipation

NOR
gate
 2
2. Clocked CMOS (C MOS) Logic

Inverter

• Same as CMOS logic

• Logic is evaluated and connected to the output during the ON period of Clock only.
• Due to extra transistors slower rise and fall times
 3.Dynamic CMOS Logic
• Pull down n/w is same as NMOS design style
• Operation in two Phases 1. Pre-Charge mode, 2. Evaluation mode
Examples: Dynamic Logic
Dynamic CMOS gates Cascading problem
• If several dynamic gates are cascaded together
using same clock, a problem is occurred in
evaluation mode
• Consider two stage dynamic logic circuits
• During Pre-charge mode (Ø =0), Vout1 and Vout2
are pre-charged to Vdd.
• When Ø goes high (Ø =1) to begin Evaluate, all
inputs at stage 1 requires some finite time to
resolve, but during this time charge of Vout2 may
discharged to zero erroneously.
• Once it discharged and it will not get high output
• The result is an error in the output of second
stage (Vout2)
4.Domino CMOS logic
Domino CMOS logic

• Static Inverter between dynamic gates

 Summary on Inverters
Resistive pull-up Depletion pull-up Enhancement Pull-up CMOS Inverter Bi-CMOS Inverter
Basic CMOS gates
CMOS-EX-OR and EX-NOR Gates
 Other forms of CMOS
• Pseudo NMOS Clocked CMOS Dynamic CMOS Domino CMOS
Zpu/Zpd Ratios
Connection of series pass transistors degrades the Logic 1 level, which is input to inverter-2 and output will not
be a proper Logic 0.

If at point A is ‘0’, then at point B is Vdd, which passes through pass transistors and at point C, Vdd is degraded
by Vtp. i.e Vdd- Vtp

Where Vtp is threshold voltage of pass transistor

Consider inverter-1 with input at VDD, then
P.d tr. (T2) is in resistive region is denoted by R1,
P.u tr. (T1) is in saturation region is denoted by
constant current source.
 Unit-2 END

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