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EEG Note 400lv

The document discusses the measurement error caused by the loading effect of a voltmeter in a circuit with specified resistances. It explains the principles of digital voltmeters (DVMs), specifically ramp-type and dual-slope-integrator DVMs, detailing their operation and limitations. The document also includes a reference for further reading on electronic instrumentation and measurements.

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Reddish I
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8 views8 pages

EEG Note 400lv

The document discusses the measurement error caused by the loading effect of a voltmeter in a circuit with specified resistances. It explains the principles of digital voltmeters (DVMs), specifically ramp-type and dual-slope-integrator DVMs, detailing their operation and limitations. The document also includes a reference for further reading on electronic instrumentation and measurements.

Uploaded by

Reddish I
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Quiz

In the circuit above, R1 = 600 Ω, R2 = 1000 Ω, R3 = 400 Ω, R4 = 1000 Ω, and R5 = 500 Ω.


Determine the measurement error caused by the loading effect in the voltmeter when the
voltage across AB is measured. Take the voltmeter internal resistance as 9500 Ω.
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Digital Instruments

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Introduction Ramp-Type DVMs
While the analog instrument display the The ramp-type VDM measures unknown
quantity to be measured in terms of voltage using a ramp signal, based on the
deflection of a pointer, digital time it takes for the ramp to rise from a
instruments the measurement value in reference voltage to the input voltage.
form of a decimal number.
The input voltage Vi and the ramp signal
The digital meter works based on the Vr are compared in the comparator.
principle of quantization.
When Vi ≥ Vr , V1 = 1, the gate is in an
For illustration purpose, the operating open state and the decade counter counts
principles of digital voltmeter (DVM) the pulses generated from the clock
(Ramp-type and dual-slope-integrator circuit.
DVMs) will be considered.
When Vi < Vr , V1 = 0, the gate is closed.
A DVM essentially consists of The output of the decade counter
analog-to-digital converter (ADC) with a corresponds to the number of clock
set of seven-segment numerical displays to pulses, which is proportional to the
indicate the measured voltage. See Fig 1. duration of the ramp transition.
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Figure 1: A ramp-type DVM. (a) DVM system. (b) DVM waveforms

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Dual-slope-integrator VDM
The latch locks the counter’s output at The dual-slope-integrator (DSI) VDM,
the end of measurement, storing the count illustrated in Fig 2 eliminates the
representing the voltage for a stable and limitations of ramp-type VDM by using a
accurate display. special type of ramp generator circuit (or
A BCD to seven-segment driver converts a integrator)
BCD input into signals that control a The integrator capacitor is first charged
seven-segment display. Its function is to from the analog input voltage and then
translate the 4-bit BCD code discharged at a constant rate to give a
(representing decimal digits 0–9) into time period that is measured digitally.
appropriate outputs The control waveform for the integrator is
Limitation of ramp-type VDM derived from the clock generator by use of
a frequency divider
The ramp-type VDMs require precise ramp
voltages and precise time periods, both of During time t1 the integrator capacitor is
which can be difficult to maintain. charged to negatively from Vi , giving a
negative-going ramp.
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Figure 2: A dual-slope-integrator DVM. (a) System block diagram. (b) System waveforms

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The voltage V0 produced during this Pulses from the clock generator pass
phase is directly proportional to Vi through the AND gate to the counting
The constant current source is then circuits during this time.
switched into the circuit to discharge the The counting circuit is reset to zero by
capacitor, thus producing a positive going the positive-going edge of the control
ramp voltage. wave at the commencement of t2 , so the
The zero voltage comparator is a voltage output of the counting circuit is a digital
comparator that gives a high output when measurement of time t2
the integrator output waveform is Since t2 is directly proportional to V0 , and
negative, and low output at the end of the V0 is directly proportional to Vi , the
positive-going ramp. output is a digital measurement of the
The AND gate has high inputs from both analog input.
the zero-crossing detector and the control
waveform only during the positive-going
ramp time, i.e., during t2

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References I
[1] David A. Bell. Electronic Instrumentation and Measurements, Second Edition.
Prentice-Hall, 2003.

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