Dldlab Report 05
Dldlab Report 05
Safia Mahnoor
Name Eman Fatima
SP24-BAI-046
Registration No. SP24-BAI-015
BSAI-2
Class
Dr. Muhammad Rizwan Azam
Instructor’s Name
Lab Assessment
Post Lab Total
In-Lab
Data Presentation Data Analysis Writing Style
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Pre-Lab:
• Objectives:
The objective of this experiment is to introduce the Verilog
Hardware Description Language (HDL) and its simulation capabilities using Xilinx
ISE. This experiment will teach the process of creating and simulating Verilog code
and will also provide hands-on experience in using Xilinx ISE for creating
testbenches, simulating, and verifying the functionality of digital designs.
• Introduction:
Verilog:
Verilog is one of the most widely used hardware description languages
(HDLs) for designing digital systems such as microprocessors, memory systems,
and other integrated circuits.
➢ It allows designers to model, test, and simulate digital circuits at various levels
of abstraction such as from the behavioral level to the structural level.
➢ Verilog code defines how a circuit behaves, and with the aid of simulation tools
like Xilinx ISE, designers can verify the functionality of their design without
physically building the circuit.
Xilinx ISE:
Xilinx ISE (Integrated Software Environment) is a comprehensive
design suite used for synthesizing, implementing, and simulating digital circuits
targeting Xilinx FPGAs.
➢ The software provides an interface for designing, verifying, and optimizing
FPGA designs written in Verilog or VHDL.
In-Lab Task:
Verify all the Basic logic gates using Xilinx ISE simulation tool and verify your
waveform with logic gates truth table.
a) Write Verilog code ,stimulus/test bench for basic gates and show results.
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1) AND Gate:
Verilog code:
Stimulus:
Simulation:
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2) OR Gate:
Verilog code:
Stimulus:
Simulation:
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3) NOT Gate:
Verilog code:
Stimulus:
Simulation:
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4) NAND Gate:
Verilog code:
Stimulus:
Simulation:
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5) NOR Gate:
Verilog code:
Stimulus:
Simulation:
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6) XOR Gate:
Verilog code:
Stimulus:
Simulation:
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7) XNOR Gate:
Verilog code:
Stimulus:
Simulation:
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Post-Lab Task:
1. Write Verilog code for given Boolean Function:
F= x+x´y+yz´
a) Gate-Level Model:
Truth Table:
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b) Data Flow Model:
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Simulation:
Conclusion:
This experiment introduces Verilog HDL and Xilinx ISE for digital
circuit design and simulation. We gained practical experience in writing Verilog
code, creating testbench and verifying circuit functionally through simulation. It
highlights the importance of simulation in detecting flaws early, providing a solid
foundation for complex FPGA-based designs.
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