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Lab2 - YA - COEN230 - Spring 25

The document outlines Lab 2 for CSC 230 and COEN 230L, focusing on combinational logic design using Quartus II software. Students will design, simulate, and verify a logic circuit with specific inputs and a truth table, gaining practical experience in digital logic and FPGA programming. The lab includes steps to create a project, draw a schematic, and upload the design to an FPGA for testing.

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Yasmeen Al-Saleh
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15 views4 pages

Lab2 - YA - COEN230 - Spring 25

The document outlines Lab 2 for CSC 230 and COEN 230L, focusing on combinational logic design using Quartus II software. Students will design, simulate, and verify a logic circuit with specific inputs and a truth table, gaining practical experience in digital logic and FPGA programming. The lab includes steps to create a project, draw a schematic, and upload the design to an FPGA for testing.

Uploaded by

Yasmeen Al-Saleh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CSC 230 & COEN 230L – Lab 2

Introduction to Combinational Logic Design

Objectives:
1. Understand the principles of combinational logic circuit design.
2. Learn how to create and simulate logic circuits using Quartus II software.
3. Implement the given circuit schematic and verify its truth table.
4. Program and test the circuit on an FPGA using assigned input switches and output LEDs.

Introduction:
In this lab exercise, students will explore the implementation of combinational logic circuits using
Quartus II software. The exercise involves designing, simulating, and verifying a logic circuit with given
inputs and truth table. By constructing the circuit and testing its functionality, students will gain hands-
on experience in digital logic design, FPGA programming, and truth table validation.

Lab Exercise: Implement the following gate & Verify the truth table:

The following figure shows a combinational logic circuit with inputs a, b and c and output F.

c b a F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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Lab Exercise: Implement the following gate & Verify the truth table:
c b a F
The following figure shows a combinational logic circuit with inputs a, b and c
and output F. 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

1) Create a new project in Quartus II software named (Lab2)

2) Create a new Schematic/ Block Diagram File and draw the circuit

3) Upload your schematic into the FPGA. (Hint: assign SW[0] , SW[1], SW[2] as Inputs &

LEDR0 as Output)

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Note: Use the following table to find the location for some pins:

Input Output

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