MICROCONTROLLER

ANAND BHAT B
DEPARTMENT OF ECE | CANARA ENGINEERING COLLEGE
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MODULE 1 - 8051 Microcontroller: Microprocessor Vs Microcontroller, Embedded

Systems, Embedded Microcontrollers, 8051 Architecture- Registers, Pin diagram, I/O ports
functions, Internal Memory organization. External Memory (ROM & RAM) interfacing.

Microprocessors and Microcontrollers

Microprocessor or Computer on a Chip first became a commercial reality in 1971 with the
introduction of 4 bit 4004 by Intel Corporation. A byproduct of microprocessor development was
the microcontroller.
Microprocessors: A microprocessor is a general-purpose digital computer Central Processing
Unit (CPU). A block diagram of a microprocessor CPU is as shown

Arithmetic and Logic Unit

Accumulator

Working Registers

Program Counter Stack Pointer

Clock Circuit Interrupt Circuit

It consists of an arithmetic and logic unit (ALU), a program Counter (PC), a stack pointer (SP),
working Registers, clock timing circuit and interrupt circuits. The prime use of a microprocessor
is to read data, perform extensive calculations on those data and store calculations in a mass
storage device or display the results. The internal CPU architecture as well as the resultant
machine level code that operates the architecture is comprehensive but as flexible as possible.

Microcontrollers:
The block diagram of a microcontroller is as shown below It incorporates all of the features
found in a microprocessor CPU: ALU, PC, SP and Registers. It also has added the other features
needed to make a complete computer: ROM, RAM, and parallel I/O, Serial I/O, Counters and a
clock circuit. It is also a general-purpose device. It performs limited calculations on the data and
control its environment based on those calculations.

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The prime use of a microcontroller is to control the operation of a machine using a fixed program
that is stored in ROM of the system. The microcontroller design uses a much more limited set of
instructions that are used to move code and data from internal memory to the ALU. Many
instructions are coupled with pins on IC. The pins are programmable and capable of having
several different functions. They are concerned with getting data from and to its own pins; the
architecture and instruction set are optimized to handle data in bit, byte and word size

ALU Timer/counter I/O port

Accumulator I/O port

Registers
Interrupt
Internal ROM
Circuits
Internal RAM

Clock
Circuits
Stack Pointer

Program Counter

Microprocessor Vs Microcontroller

Microprocessor Microcontroller

• It is an IC which has only CPU inside. • It has a CPU, in addition with a fixed
They don’t have RAM, ROM and other amount of RAM, ROM and other
peripherals on chip peripherals embedded on a single chip.
• Finds applications where tasks are • It is designed to perform specific tasks
unspecific like developing software, where the relationship between the
games, websites etc. input and output is defined such as
keyboards, washing machine, remotes,
mobiles, digicam, pen drive etc.
• They need high number of resources • Small number of resources like RAM,
like RAM, ROM, I/O ports. ROM, I/O ports and hence they are
embedded on a chip. This in turn
reduces the size and the cost.
• The clock speed of the microprocessor • They operate at few MHz to 30-50
is quite high. They can operate at 1 MHZ.

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GHz and above

• Do not have inbuilt serial ports • They have inbuilt serial ports
• Program and data are stored in the same • Separate memory to store program and
memory data
• Less multifunction pins on IC • Many multifunction pins on IC
• Boolean operations are not possible • Boolean operations are possible
directly. directly
• It takes many instructions to read and • It takes few instructions to read and
write data from external memory. They write data.
have many operational codes for They have one or two operational codes
moving data from external memory to for moving data.
CPU.
• It fails to offer software protection • It provides software protection
• It finds usage in higher end industrial • It finds usage in lower end industrial
projects. projects.
• It has one- or two-bit handling • It has many bits handling instructions
instructions
• Rapid movement of data or code from • Rapid movement of bits within the chip
external address to chip

CISC versus RISC

CISC RISC

▪ Emphasis on hardware ▪ Emphasis on software

▪ Includes multi-clock complex instructions ▪ Single-clock, reduced instruction only

▪ Memory-to-memory: "LOAD" and ▪ Register to register: "LOAD" and

"STORE" "STORE"
incorporated in instructions are independent instructions
▪ Small code sizes, high cycles per second ▪ Low cycles per second, large code
sizes

▪ Transistors used for storing complex ▪ Spends more transistors on memory

instructions registers

Computer Architectures
There are basically two types of digital computer architecture. They are
1. Von Neumann Architecture:

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It is named after the mathematician and early computer scientist John Von Neumann. The block
diagram representation of this architecture is as shown below

The characteristics of this architecture is

• The computer has single storage system(memory) for storing data as well as program to
be executed.
• Processor needs two clock cycles to complete an instruction. Pipelining the instructions is
not possible with this architecture.

• In the first clock cycle the processor gets the instruction from memory and decodes it. In
the next clock cycle the required data is taken from memory. For each instruction this
cycle repeats and hence needs two cycles to complete an instruction.
• This is a relatively older architecture and was replaced by Harvard architecture.
• Allows instructions and data to be mixed and stored in the same memory module
• More flexible and easier to implement
• Suitable for most of the general-purpose processors

2. Harvard Architecture:

The name is originated from "Harvard Mark I" a relay based old computer. The block diagram
representation of this architecture is as shown below

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The characteristics of this architecture is

• The computer has two separate memories for storing data and program.
• Processor can complete an instruction in one cycle if appropriate pipelining strategies are
implemented.
• In the first stage of pipeline the instruction to be executed can be taken from program
memory. In the second stage of pipeline data is taken from the data memory using the
decoded instruction or address.
• Most of the modern computing architectures are based on Harvard architecture. But the
number of stages in the pipeline varies from system to system.
• Uses separate memory modules for instructions and for data
• It is easier to pipeline
• Higher memory throughput
• Suitable for DSP (Digital Signal Processors)

Embedded Systems

An embedded system uses a microprocessor (or microcontroller) to do one task and one task
only there is only one application software that is typically burned into ROM.
A PC, in contrast with the embedded system, can be used for any number of applications It
has RAM memory and an operating system that loads a variety of applications into RAM
and lets the CPU run them
A PC contains or is connected to various embedded products each one peripheral has a
microcontroller inside it that performs only one task.
Many manufactures of general-purpose microprocessors have targeted their microprocessor
for the high end of the embedded market there is times that a microcontroller is inadequate
for the task
One of the most critical needs of an embedded system is to decrease power consumption
and space in high-performance embedded processors, the trend is to integrate more
functions on the CPU chip and let designer decide which features he/she wants to use. In
many cases using x86 pcs for the high-end embedded applications Saves money and
shortens development time

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Embedded Microcontrollers

Although microcontrollers are the preferred choice for many embedded systems, there are
times where microcontrollers are limited for certain applications in order to solve this there
are wide range of microcontrollers were designed and manufactured modern high-end
microcontrollers are also termed as embedded processors.
8- bit microcontrollers
• Motorola’s 6811
• Intel’s 8051
• Zilog’s Z8
• Microchip’s PIC
There are also 16-bit and 32-bit microcontrollers made by various chip makers
Meeting the computing needs of the task at hand efficiently and cost effectively
• Speed
• Packaging
• Power consumption
• The amount of RAM and ROM on chip
• The number of I/O pins and the timer on chip
• How easy to upgrade to higher- performance or lower power-
consumption versions
• Cost per unit
• Availability of software development tools, such as compilers,
assemblers, and debuggers

8051 Microcontroller Architecture

The 8051 Microcontroller architecture block diagram is as shown
below.
The 8051 architecture consists of these specific features:
• Eight-bit CPU with registers A (the accumulator) and B Sixteen-bit program counter
(PC) and data pointer (DPTR) Eight-bit program status word (PSW)
• Eight-bit stack pointer (SP)
• Internal ROM or EPROM (8751) of 0 (8031) to 4K (8051) Internal RAM of 128 bytes:
• Four register banks, each containing eight registers Sixteen bytes, which may be
addressed at the bit level Eighty bytes of general-purpose data memory
• Thirty-two input/output pins arranged as four 8-bit ports: PO-P3
• Two 16-bit timer/counters: TO and TI
• Full duplex serial data receiver/transmitter: SBUF
• Control registers: TCON, TMOD, SCON, PCON, IP, and IE Two external and three
internal interrupt sources

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• Oscillator and clock circuits

The 8051-block diagram is as shown below

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Pinout Description

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Pins 1-8: Port 1 Each of these pins can be configured as an input or an output.

Pin 9: RST A logic one on this pin disables the microcontroller and clears the contents of most
registers. In other words, the positive voltage on this pin resets the microcontroller. By applying
logic zero to this pin, the program starts execution from the beginning.

Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions:

Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication
output.

Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication
clock output.

Pin 12: INT0 Interrupt 0 input.

Pin 13: INT1 Interrupt 1 input.

Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.

Pin 16: WR Write to external (additional) RAM.

Pin 17: RD Read from external RAM.

Pin 18, 19:X2, X1 Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins. Instead of it, miniature ceramics
resonators can also be used for frequency stability. Later versions of microcontrollers operate at
a frequency of 0 Hz up to over 50 Hz.

Pin 20: GND Ground.

Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher address byte,
i.e., addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is
not used, which means that not all eight port bits are used for its addressing, the rest of them are
not available as inputs/outputs.

Pin 29:PSENIf external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.

Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address
byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the

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external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and
uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous
logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by
means of only one additional (and cheap) integrated circuit. In other words, this port is used for
both data and address transmission.

Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address
transmission with no regard to whether there is internal memory or not. It means that even there
is a program written to the microcontroller, it will not be executed. Instead, the program written
to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will
use both memories, first internal then external (if exists).

Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin
is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0).

Pin 40: VCC +5V power supply.

The 8051 Oscillator and Clock

The heart of the 8051 is the circuitry that generates the clock pulses by which all internal
operations are synchronized. Pins XTAL1 and XTAL2 are provided for connecting a resonant
network to form an oscillator. Typically, a quartz crystal and capacitors are employed, as shown in
Figure.

The crystal frequency is the basic internal clock frequency of the microcontroller. The oscillator
formed by the crystal, capacitors, and an on-chip inverter generates a pulse train at the frequency of
the crystal, as shown in Figure.

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The clock frequency, f, establishes the smallest interval of time within the micro-controller,
called the pulse, P, time. The smallest interval of time to accomplish any simple instruction, or part
of a complex instruction, however, is the machine cycle. The machine cycle is itself made up of six
states. A state is the basic time interval for discrete operations of the microcontroller such as
fetching an opcode byte, decoding an opcode, executing an opcode, or writing a data byte. Two
oscillator pulses define each state.
Program instructions may require one, two, or four machine cycles to be executed, depending on
the type of instruction. Instructions are fetched and executed by the micro-controller automatically,
beginning with the instruction located at ROM memory address 0000h at the time the
microcontroller is first reset. Time required for completing the execution of an instruction is called
an instruction cycle. For example: MOV A,#25h is a 1 machine cycle instruction, MOV 60h,40h
is a 2-machine cycle instruction and MUL AB is a 4-machine cycle instruction.
To calculate the time any particular instruction will take to be executed, find the number of
cycles, C. The time to execute that instruction is then found by multiplying C by 1 2 and dividing
the product by the crystal frequency: Tinst = C x 12d / crystal frequency
For example, if the crystal frequency is 16 megahertz, then the time to execute an ADD A, R1
one-cycle instruction is .75 microseconds.

Registers:
In the CPU, registers are used to store information temporarily. This information could be a byte of
data to be processed or an address pointing to the data to be fetched.

A and B CPU Registers

The 8051 contains 34 general-purpose, or working, registers. Two of these, registers A and B,
comprise the mathematical core of the 8051 central processing unit (CPU). The A (accumulator)
register is the most versatile of the two CPU registers and is used for many operations,
including addition, subtraction, integer multiplication and division, and Boolean bit
manipulations. The A register is also used for all data transfers between the 8051 and any
external memory. The B register is used with the A register for multiplication and division
operations and has no other function other than as a location where data may be stored.
The other 32 are arranged as part of internal RAM in four banks, BO-B3, of eight registers each,
named R0 to R7.
Internal RAM :
The 128-byte internal RAM, is organized into three distinct areas:
1. Thirty-two bytes from address 00h to 1Fh that make up 32 working registers
organized as four banks of eight registers each. The four register banks are numbered
0 to 3 and are made up of eight registers named R0 to R7. Each register can be addressed

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by name (when its bank is selected) or by its RAM address. Thus, R0 of bank 3 is R0
(if bank 3 is currently selected) or address I8h (whether bank 3 is selected or not). Bits
RS0 and RS1 in the PSW determine which bank of registers is currently in use at any
time when the program is running. Register banks not selected can be used as general-
purpose RAM. Bank 0 is selected upon reset.
2. A bit-addressable area of 16 bytes occupies RAM byte addresses 20h to 2Fh, forming a
total of 128 addressable bits. An addressable bit may be specified by its bit address of
00h to 7Fh, or 8 bits may form any byte address from 20h to 2Fh. Thus, for example,
bit address 4Fh is also bit 7 of byte address 29h. Addressable bits are useful when the
program need only remember a binary event (switch on, light off, etc.).
3. A general-purpose RAM area above the bit area, from 30h to 7Fh, addressable as bytes.

7F

30 Scratch Pad RAM

2F
20 Bit-Addressable RAM
1F R7
Register Bank 3
18 R0
17 R7
Register Bank 2
10 R0
R7
0F Register Bank 1
08 R0
R7
07
Register Bank 0
00 R0

Program Counter and Data Pointer

The 8051 contains two 16-bit registers: the program counter (PC) and the data pointer (DPTR).
Each is used to hold the address of a byte in memory. The program counter points to the address of
the next instruction to be executed. As CPU fetches the opcode from the program ROM, the

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program counter is incremented to point to the next instruction. When 8051 is powered up, PC has
the value of 0000h. The first opcode must be burned into memory location 0000h
Program instruction bytes are fetched from locations in memory that are addressed by the PC.
Program ROM may be on the chip at addresses 0000h to 0FFFh, external to the chip for addresses
that exceed 0FFFh, or totally external for all addresses from 0000h to FFFFh. The PC is
automatically incremented after every instruction byte is fetched and may also be altered by certain
instructions. The PC is the only register that does not have an internal address.
The DPTR register is made up of two 8-bit registers, named DPH and DPL, that are used to furnish
memory addresses for internal and external code access and external data access. The DPTR is
under the control of program instructions and can be specified by its 16-bit name, DPTR, or by
each individual byte name, DPH and DPL. DPTR does not have a single internal address; DPH
and DPL are each assigned an address.

DPTR DPH DPL

PC PC(Program Counter

The Stack and the Stack Pointer

The stack is a section of RAM used by the CPU to store information temporarily. This
information could be data or an address. The Register used to access the stack is called Stack
Pointer (SP). The 8-bit stack pointer (SP) register is used by the 8051 to hold an internal RAM
address that is called the "top of the stack." The address held in the SP register is the location
in internal RAM where the last byte of data was stored by a stack operation. When 8051 is
powered up, the SP register contains value 07 which means 08 is the first location used for
stack by the 8051.When data is to be placed on the stack, the SP increments before storing
data on the stack so that the stack grows up as data is stored. As data is retrieved from the
stack, the byte is read from the stack, and then the SP decrements to point to the next available
byte of stored data. The stack operation is as shown below.

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Flags and the Program Status Word (PSW)

Flags are 1-bit registers provided to store the results of certain program instructions. Other
instructions can test the condition of the flags and make decisions based upon the flag states. In
order that the flags may be conveniently addressed, they are grouped inside the program status
word (PSW) and the power control (PCON) registers.
The 8051 has four math flags that respond automatically to the outcomes of math operations
and three general-purpose user flags that can be set to 1 or cleared to 0 by the programmer as
desired. The math flags include carry (C), auxiliary carry (AC), overflow (OV), and parity (P).
User flags are named F0, GFO, and GFI; they are general-purpose flags that may be used by
the programmer to record some event in the program. Note that all of the flags can be set and
cleared by the programmer at will. The math flags, however, are also affected by math
operations.
The PSW contains the math flags, user program flag F0, and the register select bits that
identify which of the four general-purpose register banks is currently in use by the program.

The program status word Register is shown in Figure.

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CY, carry flag:-This flag is set whenever there is a carry out from D7 bit. This flag is affected
after an 8-bit addition or subtraction. It can also be set to 1 or 0 directly by an instruction such
as “SETB C”(set bit carry) and “CLR C” (clear carry). This flag is used to detect errors in
unsigned arithmetic operations.

AC, the auxiliary carry flag:- If there is a carry from D3 to D4 during an ADD or SUB
operation, this bit is set otherwise cleared.

P, the parity flag:-The parity flag reflects the number of 1s in the A register only. If A register
contains an odd number of 1s, then P=1 otherwise P=0.

OV, the overflow flag:-This flag is set whenever the result of a signed number is too large,
causing the higher order bit to overflow into the sign bit. This flag is used to detect errors in
signed arithmetic operations.

The remaining two user flags, GFO and GFI, are stored in PCON Registers.

Special Function Registers:

The 8051 operations that do not use the internal 128-byte RAM addresses from 00h to 7Fh are
done by a group of specific internal registers, each called a special-function register (SFR),
which may be addressed much like internal RAM, using addresses from 80h to FFh.

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INTERNAL RAM
NAME FUNCTION ADDRESS (HEX)
A Accumulator 0E0
B Arithmetic 0F0
DPH Addressing external memory 83
DPL Addressing external memory 82
IE Interrupt enable control 0A8
IP Interrupt priority 0B8
PO Input/output port latch 80
P1 Input/output port latch 90
P2 Input/output port latch A0
P3 Input/output port latch 0B0
PCON Power control 87
PSW Program status word 0D0
SCON Serial port control 98
SBUF Serial port data buffer 99
SP Stack pointer 81
TMOD Timer/counter mode control 89
TCON Timer/counter control 88
TL0 Timer 0 low byte 8A
TH0 Timer 0 high byte 8C
TL 1 Timer 1 low byte 8B
TH1 Timer 1 high b y t e 8D

Some of the SFR is Bit addressable, as is the case for the bit area of RAM. This feature allows
the programmer to change only what needs to be altered, leaving the remaining bits in that SFR
unchanged. Not all of the addresses from 80h to FFh are used for SFRs, and attempting to use an
address that is not defined, or "empty," results in unpredictable results The SFR names and
equivalent internal RAM addresses are given in the following table:

Note that the PC is not part of the SFR and has no internal RAM address.
SFRs are named in certain opcodes by their functional names, such as A or TH0, and are
referenced by other opcodes by their addresses, such as 0E0h or 8Ch. Note that any address
used in the program must start with a number; thus, address E0h for the A SFR begins with 0.
Failure to use this number convention will result in an assembler error when the program is
assembled.

Internal ROM
The 8051 is organized so that data memory and program code memory can be in two entirely
different physical memory entities. Each has the same address ranges.

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A corresponding block of internal program code, contained in an internal ROM, occupies code
address space 0000h to 0FFFh. The PC is ordinarily used to address program code bytes from
addresses 0000h to FFFFh. Program addresses higher than 0FFFh, which exceed the internal
ROM capacity, will cause the 8051 to automatically fetch code bytes from external program
memory. Code bytes can also be fetched exclusively from an external memory, addresses
0000h to FFFFh, by connecting the external access pin (EA pin 31 on the DIP) to ground. The
PC does not care where the code is; the circuit designer decides whether the code is found
totally in internal ROM, totally in external ROM, or in a combination of internal and external
ROM.

External Memory
The system designer is not limited by the amount of internal RAM and ROM available on chip.
Two separate external memory spaces are made available by the 16-bit PC and DPTR and by
different control pins for enabling external ROM and RAM chips. Internal control circuitry
accesses the correct physical memory, depending upon the machine cycle state and the opcode being
executed.
There are several reasons for adding external memory, particularly program memory, when applying
the 8051 in a system. The manufacturers make available an EPROM version, the 8751, which has
4K of on-chip EPROM that may be programmed and erased as needed as the program is developed.
The resulting circuit board layout will be identical to one that uses a factory-programmed 8051. The
only drawbacks to the 8751are the specialized EPROM programmers that must be used to program
the non-standard 40-pin part, and the limit of "only" 4096 bytes of program code.
The 8751 solution works well if the program will fit into 4K bytes. Unfortunately, many times,
particularly if the program is written in a high-level language, the program size exceeds 4K bytes,
and an external program memory is needed. Again, the manufacturers provide a version for the job,
the ROMless 8031. The EA pin is grounded when using the 8031, and all program code is
contained in an external EPROM that may be as large as 64K bytes and that can be programmed
using standard EPROM programmers.
External RAM, which is accessed by the DPTR, may also be needed when 128 bytes of internal data
storage is not sufficient. External RAM, up to 64K bytes, may also be added to any chip in the
8051 family.

Connecting External Memory

Figure shows the connections between an 8031 and an external memory configuration consisting of
16K bytes of EPROM and 8K bytes of static RAM. The 8051 accesses external RAM whenever
certain program instructions are executed. External ROM is accessed whenever the EA (external
access) pin is connected to ground or when the PC contains an address higher than the last address in
the internal 4K bytes ROM (0FFFh). 8051 designs can thus use internal and external ROM
automatically; the 8031, having no internal ROM, must have EA grounded.

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Figure shows the timing associated with an external memory access cycle. During any memory

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access cycle, port 0 is time multiplexed. That is, it first provides the lower byte of the 16-bit
memory address, and then acts as a bidirectional data bus to write or read a byte of memory data.
Port 2 provides the high byte of the memory address during the entire memory read/write cycle.

The lower address byte from port 0 must be latched into an external register to save the byte.
Address byte save is accomplished by the ALE clock pulse that provides the correct timing for the
'373 type data latch. The port 0 pins then become free to serve as a data bus.
If the memory access is for a byte of program code in the ROM, the PSEN (program store enable)
pin will go low to enable the ROM to place a byte of program code on the data bus. If the access is
for a RAM byte, the WR (write) or RD (read) pins will go low, enabling data to flow between the
RAM and the data bus.
The ROM may be expanded to 64K by using a 27512 type EPROM and connecting the remaining
port 2 upper address lines A14-A15 to the chip.
At this time the largest static RAMs available are 32K in size; RAM can be expanded to 64K by
using two 32K RAMs that are connected through address A14 of port 2.
External Memory (ROM & RAM) interfacing
̅𝐸̅𝐴̅(External access)

• Connect the EA pin to Vcc to indicate that the program code is stored in the
microcontroller’s on-chip ROM
• Connect the EA pin to GND To indicate that the program code is stored in external
ROM
ALE(address latch enable)
ALE (address latch enable) pin is an output pin for 8031/51
ALE = 0, P0 is used for data path
ALE = 1, P0 is used for address path

To extract the address from the P0 pins we connect P0 to a 74LS373 and use the ALE pin
to latch the address

• Normally ALE = 0, and P0 is used as a data bus, sending data out or bringing
data in
• Whenever ALE=1 P0is used as an address bus, it puts the addresses A0 – A7 on
the P0 pins
PSEN (program store enable)

PSEN signal is an output signal for the 8051 microcontroller and must be connected to
the OE pin of a ROM containing the program code

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• It is important to emphasize the role of EA and PSEN when connecting the

8031/51 to external ROM

• When the EA pin is connected to GND, the 8031/51 fetches opcode from
external ROM

RD, WR

We use RD to connect the 8051 to external ROM containing data

• For the ROM containing the program code, PSEN is used to fetch the code
To connect the 8051 to an external SRAM, we must use both RD (P3.7) and WR (P3.6)

Figure : address and data bus separation using ALE

Interfacing 8051 to (8KB) External Data ROM

Interfacing 8051 to (8KB) External Data ROM

• The number of bits that a semiconductor memory chip can store is called chip

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capacity
• It can be in units of Kbits (kilobits), Mbits (megabits), and so on
• ROM is a type of memory that does not lose its contents when the power is turned off
• ROM is also called nonvolatile memory
• RAM memory is called volatile memory since cutting off the power to the IC
willresult in the loss of data
• Sometimes RAM is also referred to as RAWM (read and write memory), in
contrast to ROM, which cannot be written to
• Memory chips have one or more pins called CS (chip select), which must be
activated for the memory’s contents to be accessed
• Sometimes the chip select is also referred to as chip enable (CE)

• In connecting a memory chip to the CPU, note the following points

• The data bus of the CPU is connected directly to the data pins of the memory
chip
• Control signals RD (read) and WR (memory write) from the CPU are connected
to the OE (output enable) and WE (write enable) pins of the memory chip
• In the case of the address buses, while the lower bits of the address from the CPU go
directly to the memory chip address pins, the upper ones are used to activate the CS pin
of the memory chip
• To extract the address from the P0 pins we connect P0 to a 74LS373 and use the ALE pin
to latch the address
• P0 provides the lower 8-bit address A0 – A7,
• P2 provides the upper 8-bit address A8 – A15
• P0 is also used to provide the 8-bit data bus D0 – D7
• P0.0 – P0.7 are used for both the address and data paths.

Interfacing 8051 to (8KB) External program ROM

• It is important to emphasize the role of EA and PSEN when connecting the 8031/51

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to external ROM

• PSEN of 8051 microcontroller must be connected to the OE pin of a ROM

containing the program code

• Enable the memory chip by connecting PSEN to CE

• When the EA = GND, the 8051 fetches opcode from external ROM
• EA = Vcc,
▪ Upon reset 8051 executes the on-chip program first, then
▪ When it reaches the end of the on-chip ROM, it switches to external
ROM for rest of program

Interfacing 8051 to (8KB) External program ROM and data ROM

Interfacing 8051 to (8KB) External data RAM

• To connect the 8051 to an external data RAM, we must use both RD (P3.7) and
WR (P3.6)
• Rest of the connection remain unchanged as that of data ROM

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Interfacing 8051 to A Single ROM as Program memory and Data memory

• Note that an AND gate is used in order to switch between program and data memory
• CE is connected to ground indicating that only one chip to be interfaced

Note: memory of any size can be interfaced to 8051 using proper number of address lines

12 pins for address (212 = 4K)

13 pins for address (213 = 8K)
14 pins for address (214 = 16K)
Interfacing 8051 to (16KB) External program ROM and data ROM and data RAM

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Question Bank
1. Explain with a block diagram the Architectural features of 8051 and list out salient
features of 8051Micro microcontroller.
2. Discuss the need for stack memory in microcontroller. Explain with examples Push and
POP instructions.
3. What are assembler directives? explain them
4. Interface 8051 to external ROM and RAM. Explain how 8051 Access them
5. Wait neat diagram explain internal architecture of 8051 with neat diagram
6. Compare microcontroller and microprocessor
7. Explain 128 bytes of internal RAM organization in 8051
8. Interface 8051 to 8K external RAM and 32K external ROM. Explain how 8051
accessthem.
9. .In 8051 based system what is the difference in connection to the program ROM and Data
ROM.
10. Interface 8051 to 16K Data RAM, 16K Data ROM and 16K program ROM. Explain how
8051 access them.
11. Explain briefly the Functions of 8051 ports.

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