Digital Design and Computer Organization Semester 3
Course Code BCS302 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 20 Hours of Practicals Total Marks 100
Credits 04 Exam Hours 3
Examination nature (SEE) Theory
Course objectives:
● To demonstrate the functionalities of binary logic system
● To explain the working of combinational and sequential logic system
● To realize the basic structure of computer system
● To illustrate the working of I/O operations and processing unit
Teaching-Learning Process (General Instructions)
These are sample Strategies; that teachers can use to accelerate the attainment of the various course outcomes.
1. Chalk and Talk
2. Live Demo with experiments
3. Power point presentation
MODULE-1 8 Hr
Introduction to Digital Design: Binary Logic, Basic Theorems And Properties Of Boolean Algebra, Boolean
Functions, Digital Logic Gates, Introduction, The Map Method, Four-Variable Map, Don’t-Care Conditions,
NAND and NOR Implementation, Other Hardware Description Language – Verilog Model of a simple circuit.
Text book 1: 1.9, 2.4, 2.5, 2.8, 3.1, 3.2, 3.3, 3.5, 3.6, 3.9
MODULE-2 8 Hr
Combinational Logic: Introduction, Combinational Circuits, Design Procedure, Binary Adder- Subtractor,
Decoders, Encoders, Multiplexers. HDL Models of Combinational Circuits – Adder, Multiplexer, Encoder.
Sequential Logic: Introduction, Sequential Circuits, Storage Elements: Latches, Flip-Flops.
Text book 1: 4.1, 4.2, 4.4, 4.5, 4.9, 4.10, 4.11, 4.12, 5.1, 5.2, 5.3, 5.4.
MODULE-3 8 Hr
Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus structure, Performance –
Processor Clock, Basic Performance Equation, Clock Rate, Performance Measurement.Machine Instructions
and Programs: Memory Location and Addresses, Memory Operations, Instruction and Instruction
sequencing, Addressing Modes.
Text book 2: 1.2, 1.3, 1.4, 1.6, 2.2, 2.3, 2.4, 2.5
MODULE-4 8 Hr
Input/output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and Disabling
Interrupts, Handling Multiple Devices, Direct Memory Access: Bus Arbitration, Speed, size and Cost of memory
systems. Cache Memories – Mapping Functions.
Text book 2: 4.1, 4.2.1, 4.2.2, 4.2.3, 4.4, 5.4, 5.5.1
MODULE-5 8 Hr
1
Basic Processing Unit: Some Fundamental Concepts: Register Transfers, Performing ALU operations, fetching
a word from Memory, Storing a word in memory. Execution of a Complete Instruction. Pipelining: Basic
concepts, Role of Cache memory, Pipeline Performance.
Text book 2: 7.1, 7.2, 8.1
PRACTICAL COMPONENT OF IPCC
Sl.N Experiments
O Simulation packages preferred: Multisim, Modalism, PSpice or any other relevant
1 Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same
using basic gates.
2 Design a 4 bit full adder and subtractor and simulate the same using basic gates.
3 Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioural model.
4 Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and Full
Subtractor.
5 Design Verilog HDL to implement Decimal adder.
6 Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.
7 Design Verilog program to implement types of De-Multiplexer.
8 Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
Course outcomes (Course Skill Set):
At the end of the course, the student will be able to:
CO1: Apply the K–Map techniques to simplify various Boolean expressions.
CO2: Design different types of combinational and sequential circuits along with Verilog programs.
CO3: Describe the fundamentals of machine instructions, addressing modes and Processor performance.
CO4: Explain the approaches involved in achieving communication between processor and I/O devices.
CO5:Analyze internal Organization of Memory and Impact of cache/Pipelining on Processor Performance.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the
SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be
deemed to have satisfied the academic requirements and earned the credits allotted to each subject/
course if the student secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
CIE for the theory component of the IPCC (maximum marks 50)
● IPCC means practical portion integrated with the theory of the course.
● CIE marks for the theory component are 25 marks and that for the practical component is 25
marks.
● 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests (Two
Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
2
assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the
syllabus and the second test after covering 85-90% of the syllabus.
● Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for the
theory component of IPCC (that is for 25 marks).
● The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.
CIE for the practical component of the IPCC
● 15 marks for the conduction of the experiment and preparation of laboratory record, and 10 marks
for the test to be conducted after the completion of all the laboratory sessions.
● On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
● The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of
all experiments’ write-ups are added and scaled down to 15 marks.
● The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
● Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
● The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the IPCC.
SEE for IPCC
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will
have a CIE component only. Questions mentioned in the SEE paper may include questions from the
practical component.
Suggested Learning Resources:
Books
1. M. Morris Mano & Michael D. Ciletti, Digital Design With an Introduction to Verilog Design, 5e,
Pearson Education.
2. Carl Hamacher, ZvonkoVranesic, SafwatZaky, Computer Organization, 5th Edition, Tata McGraw
Hill.
Web links and Video Lectures (e-Resources):
https://cse11-iiith.vlabs.ac.in/
3
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
Assign the group task to Design the various types of counters and display the output accordingly
Assessment Methods
● Lab Assessment (25 Marks)
● GATE Based Aptitude Test
