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HW05

This document outlines Homework #5 for ECE 122A VLSI Principles, focusing on device parasitics, CMOS inverter characteristics, and logic gate sizing. It includes problems related to CMOS inverter VTC, inverter delay calculations, optimal sizing of inverter chains, and logical effort analysis for various gate configurations. The homework is due on November 8, 2021, and consists of multiple problems requiring analytical and design skills in VLSI circuits.

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5 views4 pages

HW05

This document outlines Homework #5 for ECE 122A VLSI Principles, focusing on device parasitics, CMOS inverter characteristics, and logic gate sizing. It includes problems related to CMOS inverter VTC, inverter delay calculations, optimal sizing of inverter chains, and logical effort analysis for various gate configurations. The homework is due on November 8, 2021, and consists of multiple problems requiring analytical and design skills in VLSI circuits.

Uploaded by

andybao291
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE 122A, Fall 2021, Homework 05 Prof.

Kaustav Banerjee

UNIVERSITY OF CALIFORNIA, SANTA BARBARA


Department of Electrical and Computer Engineering
ECE 122A VLSI Principles

Homework #5 Device Parasitics, CMOS Inverter and Logic


Gate Sizing
Due Date: 11/08/2021, Monday, 11:59 PM

Problem 1 CMOS Inverter VTC (20)


You fabricated some transistors and found that IDS do not saturate at high VDS, rather they follow
a linear relationship. If you still went ahead with fabricating a CMOS inverter with these
transistors, show by drawing the inverter load characteristics how would the VTC look.
Problem 2 Inverter Delay (20)
As shown in the schematic below, a unit-size inverter (0.72 um/0.36 um) is driving a Pseudo-NMOS
inverting stage. The external load capacitance, CL=50fF. Assume the unit-size inverter has an equivalent
capacitance of Cunit, and equivalent output resistance of Runit. Also assume the equivalent output resistance
of the Pseudo-NMOS (2nd inverter stage) stage Req=Runit/S

(a) Keep the Wp/Wn ratio of the Pseudo-NMOS stage 2:1, find the delay for a low-to-high transition at the
output, tpLH, in terms of Cunit and Runit.

(b) Use Cunit = 2 fF, find the optimal S that minimize the low-to-high delay by taking derivative of your
result in part (a).

(c) Use tp0=0.69*Runit*Cunit=20ps, calculate the minimum delay for low-to-high transition at the output, tpLH,
for a given Runit=2kΩ.

1
ECE 122A, Fall 2021, Homework 05 Prof. Kaustav Banerjee

(d) Suppose that the probability for input being 0V, α0=50%; the probability for input being 2.5V, α1=50%.
Ignore short circuit current, what is the average power dissipated by this circuit? Use VDD=2.5V,
fclk=3GHz. Use Cunit=2fF, Runit=2kΩ.

Problem 3 Optimal Sizing of Inverter Chain (4 X 5 = 20)


For an inverter chain, implemented with N ‘2:1’ (PMOS:NMOS width) inverters, derive the
expressions for the following assuming the output capacitance is COUT and the input capacitance
(to the gate of the first inverter) is CIN:
a. Optimal fanout (f) of each stage.
b. Number of inverters (N) needed for least delay
c. Input capacitance to ith inverter
d. Total propagation delay

Problem 4 CMOS Sizing (20)


(A) Implement the following function in a single stage CMOS logic (avoid the use of inverter at output).
Appropriately size the transistors to mimic the rise and fall times of a 3:2 inverter (PMOS width: NMOS
width = 3:2). (20 pts)

F(a,b,c,d) = ∑(0,2,4,9,15) + d(7,13)

Problem 5 Logical Effort I (20)


Sketch 3-input XNOR gate using each of the following circuit techniques:
(1) Static CMOS (2) Pseudo-NMOS
Label the transistors with their widths (a unit size inverter is assumed to have the ratio Wp:Wn = 3:1). What
is the logical effort of each gate?

Problem 6 Logical Effort II (20)


The figure below shows a logic path from node 1 to node 2. Find the input capacitances necessary for each
of the gates {W, X, Y, Z} in the path to minimize path delay.
A unit size inverter is assumed to have the ratio Wp:Wn = 3:1.

2
ECE 122A, Fall 2021, Homework 05 Prof. Kaustav Banerjee

1
W
3fF X
Y 2
Z

25fF

Problem 7 Logical Effort III (20)


(A) (5 PTS) The figure below shows a logic path from node 1 to node 2. Find the input capacitances
necessary for each of the gates {W, X, Y, Z} in the path to minimize path delay.
For part A, B and C, a unit size inverter is assumed to have the ratio Wp:Wn = 3:1.

1
W
3fF X
Y 2
Z

25fF

(B) (5 PTS) As discussed in the course, the carrier mobility decreases when temperature increases. Assume
temperature only affects carrier mobility. Intuitively, higher temperature makes it more difficult for a circuit
stage to drive the next stage, because the driving current decreases. Hence, we may define a temperature
effort (T for path temperature effort, and t for single stage temperature effort) to describe the effects of
temperature-induced current decrease in a combinational logic block.
The following figure shows the relation between fan-out (f) and delay of a logic gate. The logical effort and
intrinsic delay of this gate are g0 and p0. What is the fan-out to delay curve of a gate of logical effort g1
and intrinsic delay p1 (g1 > g0, p1 > p0)? If temperature increases, how will the fan-out to delay relation
change? Show your answers in the same figure. (You need to draw the three curves in the same figure)
From the above analysis, derive the temperature effort t of a logical gate, with respect to the change of
mobility.

3
ECE 122A, Fall 2021, Homework 05 Prof. Kaustav Banerjee

Delay

g0, p0

Fanout
(C) (10 PTS) Again, a unit size inverter has the ratio Wp:Wn = 3:1, and operates at temperature T0, when
the mobility of electrons and holes is μn0 and μp0. Assume temperature T1 causes the mobility to decrease
by 10% (μn/μn0 = μp/μp0 = 0.9), and temperature T2 causes the mobility to decrease by 20% (μn/μn0 = μp/μp0
= 0.8). Assume temperature only affects the mobility of a device.
Now each stage is set to be at temperature either T1 or T2, as shown in the figure below. Find the input
capacitances necessary for each of the gates {W, X, Y, Z} in the path in order to minimize path delay.
Assume the path delay is minimized when each stage bears the same effort.

T1 T1 T2
T2
1
W
3fF X
Y 2
Z

25fF

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