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Document 113

This document outlines an examination for the Department of Electronic and Computer Engineering at Lagos State University, focusing on topics related to logic gates, Boolean expressions, and circuit simplifications. It includes various questions requiring students to demonstrate their understanding of logic symbols, truth tables, and the application of De Morgan's theorems. The exam consists of five questions, with specific instructions regarding the use of mobile phones during the examination.

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0% found this document useful (0 votes)
9 views2 pages

Document 113

This document outlines an examination for the Department of Electronic and Computer Engineering at Lagos State University, focusing on topics related to logic gates, Boolean expressions, and circuit simplifications. It includes various questions requiring students to demonstrate their understanding of logic symbols, truth tables, and the application of De Morgan's theorems. The exam consists of five questions, with specific instructions regarding the use of mobile phones during the examination.

Uploaded by

georgeife33
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAGOS STATE UNIVE! FACULTY OF ENGINEERING. DEPARTMENT OF ELECTRONIC AND COMPUTER ENGINEERING IRST SEMESTER EXAMINATION course cone: 7 course tinue: RAL ELECTRONICS tie: 2iovRs XSTRUCTION: ANSWER QUESTION ONE AND ANV OTHER-TWO. NB: STUDENTS ARE NOT ALLOWED TO COME INTO TU EXAMINATION HALL WITH MOBILE PHONE(S). QUESTIONS ONE - (50 MARKS) (®) (i) With the aid of suitable diagram, describe Logic Gate. Briefly explain the following in terms of logic symbol, switching circuit, logical operation and truth table: (ji) Exclusive OR Gate (iii) AND Gate (ii) NOT Gate. 13,5,5,5 mavias] (©) (i) Find the Boolean expression for the output ¥ of Fig. Qla. Evaluate ¥ when (ii) A = 1,€ = 1,D = 0(iii) A=B (2,2,2 marks} Input | Output = 4 AT BIC iv, 7 ofoTo 0 c ofott 1 § y [folitol—o i» ofitt 0 ih ito fol o noo [1 1 a [| og)enaro EE 0 Table Qla (© Prove the following Boolean identities: (JAC + ABC = AC(ii)(A + B)(A + C) = A + BC (iii) A+ AB = A+B (iv) ABC + ABC + ABC + AB 4 (4,4.4,4 marks] (4) Determine the logic expression forthe output Y, from the truth table shown inTable Qla. Simpli'y and sketch the logic circuit for the simplified expression. [10 marks} QUESTION TWO ~ (25 MARKS) (@ Anelectrical signal is expressed as 101011. Explain its meaning gate, what would be the output signal? (6 marks] (b) Two electrical signals represented by A= 101101 and B= 110101 are applied to a 2-input AND gate. Sketch the output signal and the binary number it represents, (6 marks) (©) Simplify the folowing Boolean expression and -raw the logic circuits forthe simplified expressions. (i) ¥ = ABC + ABC + ABC + BC (ii) ¥ = B+ (A4+C)+C(A+B)+AC (5,5 marks} [3 marks} ig. If this signal is applied to a NOT (d) Prove the following Boolean identity: A+ AB = A+B QUESTION THREE ~ (25 MARKS) (a) Simplify cach of the following expressions De Morgan’s theorems (a) A(B + ap (b) (M+N)(M +N) (c) ABCD [3,3,3 marks} (b) Find switching circuits for lo ‘B+ C) (i) AB + CD Ww 8 for t me ; * the following logic expressions: (i) A. ( ) Gi) AB+AC)T (3,3,3 marks} (©) Map the followin ‘ollowing SOP expression on the Kamaugh map: AB C + A BC + ABC + ABC {7 marks} @@ i QUESTION FOUR (25 MARKS) Demorganize the expression: (A+ B)(C+D) i) Simplify the following Boolean expressior musing the Kamaugh mapping technique: X = AB + ABC +ABC+ ABC ©) simpli ‘ 3, 7 marks) ) Sa ne eee aR expression using Karnaugh mapping technique. ! ) x + + ABCD a B (7 mais} © Af Prove tit 3-input NAND gate of the diagram (a) below is equivalent to the bubbled AND y gate of diagram (b). [8 marks] sy A A+B+T — B c— c @ ® Fig. Q4e QUESTION FIVE~ (25 MARKS) (@) Determine the output X of a logic circuit shown in Fig. Q5a. Simplify the output expression using Boolean laws and theorems. Redraw the logic circuit with the simplified expressions. [10 marks} x wD tp cp cB ‘ apie fe t AB at Fig. Q5a F ig. Q5b (b) Consider the Karaugh map of a sum-of-products function (SOP). Determine the simplified SOP function. [10 marks} JmA when its output is HIGH and 3.5mA when its output is LOW. sted on 50% duty cycle. (©) A TTL logic gate draws 21 tage and the logic gate is operat hey cite Calculate the average power if the supply vol

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