UNIVERSITY OF YAOUNDÉ I

FACULTY OF SCIENCES
DEPARTMENT OF COMPUTER SCIENCES
ICT4D L3

Top-Level View of Computer

Function and Interconnection

Author:
CHE SWANSEN S.

November 26, 2024

Contents
1 Introduction 2

2 Computer Components 2
2.1 Processor (CPU) . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Main Memory . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Input/Output Modules . . . . . . . . . . . . . . . . . . . . 3
2.4 System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.5 Secondary Storage . . . . . . . . . . . . . . . . . . . . . . 3

3 Computer Function 3
3.1 Example: Executing a Simple Addition . . . . . . . . . . . 4

4 Instruction Fetch and Execute 4

4.1 Example: Fetching an Addition Instruction . . . . . . . . . 6

5 Interrupts 6
5.1 Types of Interrupts . . . . . . . . . . . . . . . . . . . . . . 6
5.2 Example: Keyboard Interrupt . . . . . . . . . . . . . . . . 6

6 I/O Function 7
6.1 Example: Data Transfer Using DMA . . . . . . . . . . . . 7

7 Interconnection Structures 7
7.1 Types of Interconnections . . . . . . . . . . . . . . . . . . 7

8 Bus Interconnection 8
8.1 Example: Bus Data Transfer . . . . . . . . . . . . . . . . . 8
8.2 Point-to-Point Interconnect . . . . . . . . . . . . . . . . . 8
8.2.1 Characteristics of Point-to-Point Interconnect . . . 8
8.2.2 Examples of Point-to-Point Interconnect . . . . . . 9
8.2.3 Advantages of Point-to-Point Interconnect . . . . . 9
8.3 QuickPath Interconnect (QPI) . . . . . . . . . . . . . . . . 9
8.3.1 QPI Architecture . . . . . . . . . . . . . . . . . . . 9
8.3.2 Detailed Layers of QPI . . . . . . . . . . . . . . . . 10
8.3.3 Benefits of QPI . . . . . . . . . . . . . . . . . . . . 11
8.3.4 Example Use Case of QPI . . . . . . . . . . . . . . 11
8.4 Comparison: Point-to-Point vs. Bus Interconnects . . . . . 11
8.4.1 Future Trends in Point-to-Point Interconnects . . . 12

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1 Introduction
Modern computer systems depend on efficient organization and commu-
nication between components to ensure performance, scalability, and re-
liability. This chapter provides a comprehensive overview of computer
components, their roles, and the mechanisms that enable seamless inter-
connection. Additionally, we explore interconnection structures, protocols,
and architectures that form the backbone of contemporary computer sys-
tems.
—

2 Computer Components
A computer system is composed of five fundamental components, each
serving a specific function. Together, they allow the computer to execute
instructions and perform useful tasks.

Figure 1: Computer Components

2.1 Processor (CPU)

The processor, often referred to as the brain of the computer, is responsible
for executing instructions, performing computations, and coordinating the
activities of other components. It consists of:

• Control Unit (CU): Directs the flow of data between components.

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 • Arithmetic Logic Unit (ALU): Performs mathematical calcula-
tions and logical operations.

• Registers: Provide temporary storage for instructions, data, and

addresses.

2.2 Main Memory

The main memory (RAM) temporarily holds data and instructions that
the CPU actively uses. It is volatile, meaning its contents are lost when
power is turned off.

2.3 Input/Output Modules

I/O modules enable communication between the computer and external
devices such as keyboards, monitors, and storage drives. Examples include:

• Disk controllers for hard drives.

• USB controllers for peripheral devices.

2.4 System Bus

The system bus interconnects the processor, memory, and I/O modules.
It serves as a communication highway for data, addresses, and control
signals.

2.5 Secondary Storage

Secondary storage, such as hard drives and SSDs, provides long-term data
storage. Unlike main memory, it is non-volatile.
—

3 Computer Function
A computer performs four primary functions:

1. Data Movement: Transfers data between devices, such as from

memory to the CPU.

2. Data Storage: Maintains data temporarily in registers or RAM

and permanently in secondary storage.

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 3. Data Processing: Executes arithmetic and logical operations on
data.

4. Control: Directs and coordinates the operation of all components.

3.1 Example: Executing a Simple Addition

Consider an instruction to add two numbers stored in memory. The com-
puter performs the following steps:

1. Fetch the instruction from memory.

2. Decode the instruction to identify it as an addition operation.

3. Fetch the operands from memory.

4. Perform the addition in the ALU.

5. Store the result back in memory or a register.

4 Instruction Fetch and Execute

The fetch-and-execute cycle describes the steps a CPU takes to execute
an instruction:

1. Fetch: Retrieve the next instruction from memory, based on the

Program Counter (PC).

2. Decode: Interpret the instruction to determine the operation and

operands.

3. Execute: Perform the specified operation, such as a calculation or

data transfer.

4. Store: Write the result back to memory or a register.

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Figure 2: Fetch Decode Execute Cycle

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4.1 Example: Fetching an Addition Instruction
Suppose the CPU encounters the instruction ‘ADD R1, R2, R3‘, which
adds the contents of registers R2 and R3 and stores the result in R1. The
cycle works as follows:

• Fetch: Retrieve the instruction ‘ADD R1, R2, R3‘ from memory.

• Decode: Interpret it as an addition operation.

• Execute: Add the contents of R2 and R3.

• Store: Save the result in R1.

5 Interrupts
Interrupts are mechanisms that allow the CPU to pause its current task,
handle an event, and then resume. This ensures efficient handling of asyn-
chronous tasks.

5.1 Types of Interrupts

• Hardware Interrupts: Generated by devices like keyboards or
network cards.

• Software Interrupts: Triggered by programs to request services

from the operating system.

• Timer Interrupts: Enable periodic tasks like system clock updates.

5.2 Example: Keyboard Interrupt

When a key is pressed, the keyboard sends an interrupt signal to the
CPU. The CPU temporarily pauses its current task, reads the keystroke,
and resumes its previous task.
—

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6 I/O Function
Input/output operations allow the computer to interact with external de-
vices. There are three main techniques:

1. Programmed I/O: The CPU manages the data transfer between

memory and I/O devices.

2. Interrupt-Driven I/O: Devices notify the CPU when they are

ready, reducing CPU idle time.

3. Direct Memory Access (DMA): Transfers data between memory

and devices without CPU intervention, improving efficiency.

6.1 Example: Data Transfer Using DMA

In a DMA transfer, the DMA controller directly moves data from an ex-
ternal storage device to memory, bypassing the CPU. This allows the CPU
to focus on other tasks.
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7 Interconnection Structures
The interconnection structure connects the CPU, memory, and I/O mod-
ules. It determines the efficiency of communication within the system.

7.1 Types of Interconnections

• Bus: A shared communication pathway for data, addresses, and
control signals.

• Point-to-Point: Dedicated connections between components for

high-speed communication.

• Crossbar Switch: Provides direct links between multiple compo-

nents, enhancing parallelism.

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8 Bus Interconnection
The bus is a shared medium for data transfer. It consists of:

• Data Bus: Transfers actual data.

• Address Bus: Specifies the memory location for data transfer.

• Control Bus: Manages communication and synchronization.

8.1 Example: Bus Data Transfer

When transferring data from memory to the CPU:

• The address bus specifies the memory location.

• The data bus transfers the data.

• The control bus coordinates the operation.

8.2 Point-to-Point Interconnect

Point-to-point interconnect refers to a direct communication pathway be-
tween two components in a computer system, bypassing the need for shared
bus architecture. This method improves communication speed and reduces
latency compared to traditional bus-based systems.

8.2.1 Characteristics of Point-to-Point Interconnect

• Direct Connection: Unlike a bus, which connects multiple devices,
point-to-point links provide a dedicated channel between two specific
components, such as a CPU and a memory controller.

• Scalability: Adding more components to the system does not intro-

duce contention or bottlenecks, as each connection is independent.

• High Bandwidth: By avoiding shared communication pathways,

point-to-point interconnects offer significantly higher bandwidth and
lower latency.

• Reliability: Errors are less likely because each connection is tailored

to two devices, reducing noise and interference.

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8.2.2 Examples of Point-to-Point Interconnect
• Intel QuickPath Interconnect (QPI): Used in Intel processors
for high-speed communication between CPUs and between CPUs
and memory.

• HyperTransport (HT): Developed by AMD, this technology pro-

vides a low-latency, high-speed interconnect for AMD processors.

8.2.3 Advantages of Point-to-Point Interconnect

Point-to-point interconnect is particularly beneficial in systems with high
performance requirements. For example, in server-grade CPUs, multiple
processors can communicate directly using point-to-point links without
sharing bandwidth.
—

8.3 QuickPath Interconnect (QPI)

The QuickPath Interconnect (QPI) is a high-speed point-to-point intercon-
nect developed by Intel. It is designed to replace the traditional front-side
bus (FSB) architecture, allowing for faster communication between pro-
cessors and other system components.

8.3.1 QPI Architecture

The QPI architecture consists of multiple layers that ensure efficient data
transfer and management:

• Physical Layer: Responsible for the electrical and mechanical con-

nection between devices.

• Link Layer: Ensures reliable data transfer by handling flow control

and error correction.

• Routing Layer: Determines the path that data packets take be-
tween the source and destination.

• Protocol Layer: Manages high-level data transfer tasks, such as

ensuring data integrity and coherence.

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8.3.2 Detailed Layers of QPI
1. QPI Physical Layer

• Transmits raw data signals over high-speed serial links.

• Typically uses differential signaling to reduce noise and improve sig-

nal integrity.

• Example: A QPI link might connect two processors at a rate of up

to 25.6 GB/s.

2. QPI Link Layer

• Provides error detection and correction using cyclic redundancy checks

(CRC).

• Ensures proper sequencing of packets to maintain data order.

• Example: If a packet is lost or corrupted during transmission, the

link layer requests a retransmission.

3. QPI Routing Layer

• Handles the routing of packets through the interconnect fabric.

• Ensures that packets reach the correct destination based on their

address headers.

• Example: A multi-socket system with multiple processors will use

the routing layer to direct packets to the appropriate processor or
memory module.

4. QPI Protocol Layer

• Ensures coherence between processors in multi-processor systems.

• Manages high-level communication protocols for data transfer.

• Example: In a dual-processor system, the protocol layer ensures that

both processors have consistent views of shared memory.

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8.3.3 Benefits of QPI
• High Performance: QPI provides high bandwidth, enabling pro-
cessors to exchange data at speeds of up to several gigabytes per
second.

• Low Latency: By eliminating the bottlenecks of traditional bus

systems, QPI significantly reduces communication delays.

• Scalability: QPI is designed for multi-socket systems, making it

ideal for high-performance servers.

8.3.4 Example Use Case of QPI

Consider a server system with two Intel Xeon processors and shared mem-
ory. Using QPI, the processors can directly communicate with each other
at high speed, ensuring efficient execution of parallel tasks. For instance,
if Processor A performs a database query while Processor B performs data
compression, QPI ensures seamless coordination and memory access be-
tween them.
—

8.4 Comparison: Point-to-Point vs. Bus Intercon-

nects
• Bus Interconnects:

– Shared by multiple devices.

– Prone to congestion and bottlenecks.
– Example: In older architectures, the front-side bus connected
the CPU to memory and I/O devices.

• Point-to-Point Interconnects:

– Dedicated pathways for each connection.

– Eliminates bottlenecks and improves scalability.
– Example: QPI in Intel systems and HyperTransport in AMD
systems.

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8.4.1 Future Trends in Point-to-Point Interconnects
With increasing demands for high-speed data transfer and parallel process-
ing, point-to-point interconnects are evolving. Emerging technologies such
as Compute Express Link (CXL) are designed to provide even faster and
more efficient communication between CPUs, memory, and accelerators
like GPUs.

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