SCHOOL OF ELECTRONICS ENGINEERING

Fall Semester 2024-2025

BECE312L – Robotics and Automation

PROJECT REPORT

Kamisetty Sai Sravan (22BEC0273)

Vallam Yaswanth (22BEC0899)
Koilada Bharath Surya (22BEC0135)

Slot: A2+TA2
 VLSI based Alarm Clock top
Kamisetty Sai Sravan Vallam Yaswanth Koilada Bharath Surya
22BEC0273 22BEC0899 22BEC0135

Abstract: includes error handling mechanisms to manage invalid inputs

This report presents the design and implementation of a and ensure robust operation.
digital alarm clock using Verilog Hardware Description
Language (HDL). The primary goal of the project is to In summary, this project provides a comprehensive design
develop a functional and reliable alarm clock system that and implementation of a digital alarm clock using Verilog
accurately keeps track of the current time, allows users to set HDL. The modular approach ensures that each component
an alarm, and triggers an alarm sound when the current time can be tested and verified independently, contributing to the
matches the set alarm time. The system is composed of overall reliability of the system. The simulation results
several interconnected modules, each designed to handle confirm the functionality and accuracy of the alarm clock,
specific tasks essential for the overall functionality of the making it a practical and useful device for everyday use. The
alarm clock. project demonstrates the application of digital design
principles and Verilog HDL in creating a functional and
The time generator module is responsible for producing reliable digital system.
one-second and one-minute pulses, which are crucial for
updating the current time. The counter module keeps track of Keywords: Digital Alarm Clock, Verilog HDL, Time Generator,
the current time in hours and minutes, updating the time Counter Module, Alarm Register, Key Register, Finite State
based on the pulses generated by the time generator. The Machine (FSM), LCD Driver, Modular Design, Simulation,
Testbenches, Digital Circuits, Timekeeping, Alarm Setting, User
alarm register module stores the alarm time set by the user,
Interface, Reliability, Practical Applicability
ensuring that the alarm can be triggered at the desired time.
The key register module handles key inputs, allowing users I. INTRODUCTION
to set the current time and alarm time through a user-friendly
interface. The advent of digital electronics has revolutionized the
way we interact with everyday devices, including alarm
The finite state machine (FSM) module controls the clocks. Traditional analog alarm clocks have given way to
overall state of the system, managing the display of the digital counterparts that offer enhanced functionality and
current time, alarm time, and key inputs, as well as the setting precision. This project focuses on the design and
implementation of a digital alarm clock using Verilog HDL, a
of the current time and alarm time. The FSM ensures that the
widely used language for describing digital circuits. The
system transitions smoothly between different states, such as primary objective is to create a system that accurately keeps
displaying the current time, setting the alarm time, and track of the current time, allows users to set an alarm, and
triggering the alarm sound. The LCD driver module drives triggers an alarm sound when the current time matches the set
the LCD display to show the current time, alarm time, and alarm time. [1]
key inputs, providing a clear and intuitive user interface.
The alarm clock system is composed of several key
The modular design of the alarm clock system ensures that modules, each responsible for specific functions. The time
each component can be tested and verified independently. generator module produces one-second and one-minute
This approach not only simplifies the debugging process but pulses, which are essential for updating the current time. The
also enhances the reliability of the overall system. The system counter module keeps track of the current time in hours and
was simulated using a Verilog simulator to verify the minutes, updating the time based on the pulses from the time
functionality of each module and the overall system. generator. The alarm register module stores the alarm time set
by the user, ensuring that the alarm can be triggered at the
Testbenches were created to test various scenarios, including
desired time. The key register module handles key inputs,
setting the current time, setting the alarm time, and triggering allowing users to set the current time and alarm time. The
the alarm sound. The simulation results confirmed the finite state machine (FSM) module controls the overall state
accuracy and functionality of the alarm clock, demonstrating of the system, managing the display of current time, alarm
its practical applicability. time, and key inputs, as well as the setting of the current time
and alarm time. Finally, the LCD driver module drives the
In addition to the core functionalities, the system includes LCD display to show the current time, alarm time, and key
features such as fast time adjustment and key input buffering inputs, providing a user-friendly interface.
to improve user experience. The fast time adjustment feature
allows users to quickly set the current time and alarm time, The modular design of the alarm clock system ensures that
while the key input buffering ensures that key inputs are each component can be tested and verified independently.
processed accurately and efficiently. The system also This approach not only simplifies the debugging process but
also enhances the reliability of the overall system. The system input reset,
was simulated using a Verilog simulator to verify the
functionality of each module and the overall system. input one_minute,
Testbenches were created to test various scenarios, including input load_new_c,
setting the current time, setting the alarm time, and triggering
the alarm sound. The simulation results confirmed the input [3:0] new_current_time_ms_hr,
accuracy and functionality of the alarm clock, demonstrating input [3:0] new_current_time_ms_min,
its practical applicability.[2]
input [3:0] new_current_time_ls_hr,
In summary, this project provides a comprehensive design
and implementation of a digital alarm clock using Verilog input [3:0] new_current_time_ls_min,
HDL[3]. The modular approach ensures that each component output reg [3:0] current_time_ms_hr,
can be tested and verified independently, contributing to the
overall reliability of the system. The simulation results output reg [3:0] current_time_ms_min,
confirm the functionality and accuracy of the alarm clock, output reg [3:0] current_time_ls_hr,
making it a practical and useful device for everyday use.[4]
output reg [3:0] current_time_ls_min
II. SYSTEM ARCHITECTURE
);
The system architecture is composed of the following
modules: // Module implementation
1. Time Generator (timegen): Generates one-second endmodule
and one-minute pulses.
2. Counter (counter): Keeps track of the current time C. Alarm Register Module
in hours and minutes. The alarm_reg module stores the alarm time set by the
3. Alarm Register (alarm_reg): Stores the alarm user. It updates the alarm time based on key inputs and the
time. alarm button.
4. Key Register (keyreg): Handles key inputs for
module alarm_reg(
setting the time and alarm.
5. FSM (fsm): Controls the state of the system based input [3:0] new_alarm_ms_hr,
on user inputs.
input [3:0] new_alarm_ls_hr,
6. LCD Driver (lcd_driver and lcd_driver_4): Drives
the LCD display to show the current time, alarm input [3:0] new_alarm_ms_min,
time, and key inputs. input [3:0] new_alarm_ls_min,
A. Time Generator Module input load_new_alarm,
The timegen module generates one-second and one- input clock,
minute pulses based on the system clock. It includes a counter input reset,
that increments with each clock pulse and resets after reaching
specific values to generate the required pulses. output reg [3:0] alarm_time_ms_hr,
module timegen( output reg [3:0] alarm_time_ls_hr,
input clock, output reg [3:0] alarm_time_ms_min,
input reset, output reg [3:0] alarm_time_ls_min
input reset_count, );
input fastwatch, // Module implementation
output reg one_second, endmodule
output reg one_minute D. Key Register Module
); The keyreg module handles key inputs for setting the time
and alarm. It shifts the key inputs into buffers for processing.
// Module implementation
module keyreg(
endmodule
reset, clock, shift, key, key_buffer_ls_min,
B. Counter Module
key_buffer_ms_min,
The counter module keeps track of the current time in
hours and minutes. It updates the time based on the one- key_buffer_ls_hr, key_buffer_ms_hr
minute pulse from the time generator and handles time setting
through key inputs. );

module counter( // Module implementation

input clk, endmodule

 E. FSM Module display_ms_hr,
The fsm module controls the state of the system based on display_ls_hr,
user inputs. It manages the display of current time, alarm time,
and key inputs, as well as the setting of the current time and display_ms_min,
alarm time.[5] display_ls_min,
module fsm ( sound_a
clock, reset, one_second, time_button, alarm_button, );
key, reset_count,
endmodule
load_new_a, show_a, show_new_time, load_new_c,
shift III. SIMULATION AND TESTING

); The system was simulated using a Verilog simulator to

verify the functionality of each module and the overall
// Module implementation system. Testbenches were created to test various
endmodule scenarios, including setting the current time, setting the
alarm time, and triggering the alarm sound. The
F. LCD Driver Module simulation results confirmed the accuracy and
The lcd_driver modules drive the LCD display to show the functionality of the alarm clock, demonstrating its
current time, alarm time, and key inputs. The lcd_driver_4 practical applicability.
module combines four instances of lcd_driver to display the
A. Simulation Results
complete time and alarm information.
module lcd_driver(
input [3:0] key,
input [3:0] alarm_time,
input [3:0] current_time,
input show_alarm,
input show_new_time,
output reg [7:0] display_time,
output reg sound_alarm
);
// Module implementation
endmodule

module lcd_driver_4(
alarm_time_ms_hr,
alarm_time_ls_hr,
alarm_time_ms_min,
alarm_time_ls_min, Figure 1: Block Diagram and Schematic of the Alarm Clock
System
current_time_ms_hr,
current_time_ls_hr,
current_time_ms_min,
current_time_ls_min,
key_ms_hr,
key_ls_hr,
key_ms_min,
key_ls_min,
show_a,
show_current_time, Figure 2: Circuit Diagram of the Time Generator Module
 Figure 3: Circuit Diagram of the Counter Module

Figure 7: Circuit Diagram of the LCD Driver Module

IV. Finite State Machine (FSM)

The Finite State Machine (FSM) is a crucial component of
the alarm clock system, responsible for managing the
overall state and flow of the system based on user inputs.
The FSM ensures that the system transitions smoothly
between different operational states, such as displaying the
current time, setting the alarm time, and triggering the alarm
sound. This section provides an in-depth explanation of the
FSM's design, states, transitions, and functionality.[6]
Figure 4: Circuit Diagram of the Alarm Register Module
A. FSM Design
The FSM is designed to handle various user interactions and
system events, ensuring that the alarm clock operates
correctly and efficiently. The FSM consists of several states,
each representing a specific mode of operation. The states
are defined as follows:
1. SHOW_TIME: The default state where the current
time is displayed.
2. KEY_ENTRY: The state where key inputs are
being processed to set the time or alarm.
3. KEY_STORED: The state where the key input has
been stored and is waiting for further action.
4. KEY_WAITED: The state where the system waits
Figure 5: Circuit Diagram of the Key Register Module
for a key input within a specified time.
5. SHOW_ALARM: The state where the alarm time
is displayed.
6. SET_ALARM_TIME: The state where the alarm
time is being set.
7. SET_CURRENT_TIME: The state where the
current time is being set.

B. State Transitions
The FSM transitions between states based on specific
conditions and user inputs. The transitions are governed by
the following rules:
1. SHOW_TIME to SHOW_ALARM: The system
Figure 6: Circuit Diagram of the FSM Module transitions to the SHOW_ALARM state when
the alarm_button is pressed.
 2. SHOW_TIME to KEY_STORED: The system system responds correctly to user inputs and transitions
transitions to the KEY_STORED state when a key smoothly between different operational states. The FSM's
input (other than NOKEY) is detected. functionality includes:
3. KEY_STORED to KEY_WAITED: The system  Displaying the Current Time: In the SHOW_TIME
transitions to the KEY_WAITED state after storing state, the FSM ensures that the current time is
the key input. displayed on the LCD.
4. KEY_WAITED to KEY_ENTRY: The system  Setting the Time: In the SET_CURRENT_TIME
transitions to the KEY_ENTRY state if no key state, the FSM processes key inputs to set the
input is detected within a specified time. current time.
5. KEY_WAITED to SHOW_TIME: The system  Setting the Alarm: In the SET_ALARM_TIME
transitions back to the SHOW_TIME state if the state, the FSM processes key inputs to set the alarm
timeout occurs without a key input. time.
6. KEY_ENTRY to SET_ALARM_TIME: The  Triggering the Alarm: When the current time
system transitions to the SET_ALARM_TIME matches the set alarm time, the FSM triggers the
state when the alarm_button is pressed. alarm sound.
7. KEY_ENTRY to SET_CURRENT_TIME: The  Handling Timeouts: The FSM manages timeouts to
system transitions to the SET_CURRENT_TIME ensure that the system returns to the default state if
state when the time_button is pressed. no further action is taken within a specified time.
8. KEY_ENTRY to SHOW_TIME: The system In summary, the FSM is a vital component of the alarm
transitions back to the SHOW_TIME state if the clock system, ensuring that the system operates correctly
timeout occurs without further action. and efficiently based on user inputs and system events. The
9. SHOW_ALARM to SHOW_TIME: The system Moore state diagram provides a visual representation of the
transitions back to the SHOW_TIME state when FSM's states and transitions, aiding in the understanding and
the alarm_button is released. verification of the system's functionality.[7]
10. SET_ALARM_TIME to SHOW_TIME: The
system transitions back to the SHOW_TIME state
after setting the alarm time. V. TESTBENCH AND OUTPUTS
11. SET_CURRENT_TIME to SHOW_TIME: The The system was simulated using a Verilog simulator to verify
system transitions back to the SHOW_TIME state the functionality of each module and the overall system.
after setting the current time. Testbenches were created to test various scenarios, including
setting the current time, setting the alarm time, and triggering
C. FSM Implementation the alarm sound. The simulation results confirmed the
The FSM is implemented using Verilog HDL, with the state accuracy and functionality of the alarm clock, demonstrating
transitions and outputs controlled by the fsm module. The its practical applicability.[8]
module takes various inputs, including clock, reset,
one_second, time_button, alarm_button, key, and
reset_count, and produces outputs such as load_new_a, Simulation Results
show_a, show_new_time, load_new_c, and shift.
1.

Figure 9: Testbench Waveform for Alarm Clock System

Input Conditions:
Figure 8: Moore State Diagram of the FSM
 reset is set to 1 to initialize the system.
The Moore state diagram illustrates the different states of  clock is toggled every 5 ns.
the FSM and the transitions between them based on the
 time_button, alarm_button
input conditions. Each state represents a specific mode of
and fastwatch are initially set to 0.
operation, and the transitions between states are governed
by the user inputs and system events.  key is initially set to 4'b0011.
 After 100 ns, reset is released (set to 0).
D. FSM Functionality
The FSM plays a critical role in managing the overall  time_button is pulsed twice to enter the time-setting
operation of the alarm clock system. It ensures that the mode.
 key is set to 4'b1010 and time_button is pulsed to set Input Conditions:
the hours.
 reset is set to 1 to initialize the system.
 key is set to 4'b0101 to set the minutes.
 clock is toggled every 5 ns.
 fastwatch is toggled to enable/disable fast time
adjustment.  time_button, alarm_button and fastwatch are
initially set to 0.
 alarm_button is pulsed to enter the alarm-setting
mode.  key is initially set to 4'b0011.

 key is set to 4'b0001, 4'b0010, 4'b0100, and 4'b1000  After 100 ns, reset is released (set to 0).
to set the alarm time.  time_button is pulsed twice to enter the time-setting
 The system operates normally, toggling time_button, mode.
alarm_button, fastwatch and key to simulate user  key is set to 4'b1010 and time_button is pulsed to set
interactions. the hours.
Output Comments:  key is set to 4'b0101 to set the minutes.
 The provided waveform image shows the behaviour  fastwatch is toggled to enable/disable fast time
of the alarm clock system under the specified input adjustment.
conditions.
 alarm_button is pulsed to enter the alarm-setting
 The system initializes correctly when reset is high. mode.
Alloutputs(ms_hour, ls_hour, ms_minute, ls_minute
, alarm_sound) are set to their default values.  key is set to 4'b0001, 4'b0010, 4'b0100, and 4'b1000
to set the alarm time.
 The clock signal toggles every 5 ns, providing the
necessary clock pulses for the system.  The system operates normally, toggling time_button,
alarm_button, fastwatch and key to simulate user
 When time_button is pulsed, the system enters the interactions.
time-setting mode. The values
of ms_hour, ls_hour, ms_minute,
and ls_minute update according to the key inputs. Output Comments:
 Toggling fastwatch affects the speed of time  The provided waveform image shows the behavior
increment. When fastwatch is high, the time of the alarm clock system under the specified input
increments faster, as observed in the waveform. conditions.
 When alarm_button is pulsed, the system enters the  The system initializes correctly when reset is high.
alarm-setting mode. The values of the alarm time All outputs (ms_hour, ls_hour, ms_minute,
update according to the key inputs. ls_minute, alarm_sound) are set to their default
 When the current time matches the set alarm values.
time, alarm_sound is triggered. The waveform  The clock signal toggles every 5 ns, providing the
shows alarm_sound going high at the correct time, necessary clock pulses for the system.
confirming the functionality of the alarm triggering
mechanism.  When time_button is pulsed, the system enters the
time-setting mode. The values
 The system operates correctly, updating the time and of ms_hour, ls_hour, ms_minute,
alarm values as per the user inputs. The waveform and ls_minute update according to the key inputs.
shows the expected behaviour of the system under
normal operation.  Toggling fastwatch affects the speed of time
increment. When fastwatch is high, the time
2. increments faster, as observed in the waveform.
 When alarm_button is pulsed, the system enters the
alarm-setting mode. The values of the alarm time
update according to the key inputs.
 When the current time matches the set alarm
time, alarm_sound is triggered. The waveform
shows alarm_sound going high at the correct time,
confirming the functionality of the alarm triggering
mechanism.

Figure 10: Testbench Waveform for Alarm Clock System  The system operates correctly, updating the time and
without toggling fast watch. alarm values as per the user inputs. The waveform
shows the expected behavior of the system under
normal operation.
3.  Toggling fastwatch affects the speed of time
increment. When fastwatch is high, the time
increments faster, as observed in the waveform.
 When alarm_button is pulsed, the system enters the
alarm-setting mode. The values of the alarm time
update according to the key inputs.
 When the current time matches the set alarm
time, alarm_sound is triggered. The waveform
shows alarm_sound going high at the correct time,
confirming the functionality of the alarm triggering
Figure 11: Testbench Waveform for Alarm Clock mechanism.
System with Extended Testing  The system operates correctly, updating the time and
Input Conditions: alarm values as per the user inputs. The waveform
shows the expected behavior of the system under
 reset is set to 1 to initialize the system. normal operation.
 clock is toggled every 5 ns.  In the previous waveform, the system was tested with
 time_button, alarm_button and fastwatch are a shorter sequence of operations and fewer
initially set to 0. repetitions.

 key is initially set to 4'b0011.  The current waveform includes more extensive
testing with multiple cycles of time and alarm
 After 100 ns, reset is released (set to 0). setting, demonstrating the system's robustness and
stability over extended periods.
 time_button is pulsed twice to enter the time-setting
mode.  The repeat loop in the testbench allows for
automated testing of multiple scenarios, ensuring
 key is set to 4'b1010 and time_button is pulsed to set comprehensive verification of the system's
the hours. functionality.
 key is set to 4'b0101 to set the minutes.  The waveform shows consistent behavior across
 fastwatch is toggled to enable/disable fast time multiple cycles, confirming the reliability of the
adjustment. alarm clock system under various conditions.

 alarm_button is pulsed to enter the alarm-setting

mode.
VI. CONCLUSION
The design and implementation of a digital alarm clock
 key is set to 4'b0001, 4'b0010, 4'b0100 and 4'b1000 using Verilog HDL have been successfully demonstrated in
to set the alarm time. this project. The alarm clock system comprises several
interconnected modules, each responsible for specific
 The system operates normally, toggling time_button, functions such as time generation, timekeeping, alarm
alarm_button, fastwatch, and key to simulate user setting, key input handling, state management, and LCD
interactions display driving. The modular approach ensures that each
 The repeat loop is used to simulate multiple cycles component can be tested and verified independently,
of time and alarm setting. contributing to the overall reliability of the system.[9]
Output Comments: The time generator module accurately produces one-second
 The provided waveform image shows the behavior and one-minute pulses, which are essential for updating the
of the alarm clock system under the specified input current time. The counter module keeps track of the current
conditions. time in hours and minutes, updating the time based on the
pulses from the time generator. The alarm register module
 The system initializes correctly when reset is high.
stores the alarm time set by the user, ensuring that the alarm
All outputs (ms_hour, ls_hour, ms_minute,
ls_minute, alarm_sound) are set to their default can be triggered at the desired time. The key register module
values. handles key inputs, allowing users to set the current time
and alarm time through a user-friendly interface.
 The clock signal toggles every 5 ns, providing the
necessary clock pulses for the system. The finite state machine (FSM) module plays a critical role
 When time_button is pulsed, the system enters the in managing the overall state of the system. It ensures
time-setting mode. The values of ms_hour, ls_hour, smooth transitions between different operational states, such
ms_minute, and ls_minute update according to the as displaying the current time, setting the alarm time, and
key inputs. triggering the alarm sound. The LCD driver module drives
the LCD display to show the current time, alarm time, and
key inputs, providing a clear and intuitive user interface.
The system was simulated using a Verilog simulator to We also thank our peers and colleagues for their
verify the functionality of each module and the overall collaboration and support. Their contributions and
discussions have enriched our learning experience and
system. Testbenches were created to test various scenarios, helped us overcome various challenges.
including setting the current time, setting the alarm time,
and triggering the alarm sound. The simulation results Finally, we extend our thanks to the institution for
confirmed the accuracy and functionality of the alarm clock, providing the necessary resources and facilities that
demonstrating its practical applicability. enabled us to carry out this project successfully.

In summary, this project provides a comprehensive design References

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