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COMP204 Tutorial 2

The document outlines key concepts related to processor operations, instruction execution, and data transfer mechanisms, including processor-memory interactions and interrupt handling. It discusses the architecture of microprocessors, detailing address and data bus configurations, as well as instruction formats. Additionally, it covers the significance of various components such as the Program Counter and Instruction Register in executing instructions and managing data flow.

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Calvin Pillay
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8 views

COMP204 Tutorial 2

The document outlines key concepts related to processor operations, instruction execution, and data transfer mechanisms, including processor-memory interactions and interrupt handling. It discusses the architecture of microprocessors, detailing address and data bus configurations, as well as instruction formats. Additionally, it covers the significance of various components such as the Program Counter and Instruction Register in executing instructions and managing data flow.

Uploaded by

Calvin Pillay
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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COMP204 Tutorial 2:

Calvin John Asogaran Pillay

223003485

1. Processor-memory: Data may be transferred from processor to


memory or from memory to processor.
Processor-I/O: Data may be transferred to or from a peripheral
device by transferring between the processor and an I/O module.
Data processing: The processor may perform some arithmetic or
logic operation on data.
Control: An instruction may specify that the sequence of execution
be altered.

2. Instruction address calculation (iac): Determine the address of the


next instruction to be executed.
Instruction fetch (if): Read instruction from its memory location into
the processor.
Instruction operation decoding (iod): Analyse instruction to
determine type of operation to be performed and operand(s) to be
used.
Operand address calculation (oac): If the operation involves
reference to an operand in memory or available via I/O, then
determine the address of the operand.
Operand fetch (of): Fetch the operand from memory or read it in
from I/O.
Data operation (do): Perform the operation indicated in the
instruction.
Operand store (os): Write the result into memory or out to I/O.

3. - Disable all interrupts while an interrupt is being processed.


- Define priorities for interrupts and to allow an interrupt of higher
priority to cause a lower-priority interrupt handler to be interrupted.

4. Memory to processor: The processor reads an instruction or a unit of


data from memory.
Processor to memory: The processor writes a unit of data to
memory.
I/O to processor: The processor reads data from an I/O device via an
I/O module. Processor to I/O: The processor sends data to the I/O
device.
I/O to or from memory: For these two cases, an I/O module is
allowed to exchange data directly with memory, without going
through the processor, using direct memory access (DMA).
5. Physical - Consists of the actual wires carrying the signals, as well as
circuitry and logic to support ancillary features required in the
transmission and receipt of the 1s and 0s.
Link - Responsible for reliable transmission and flow control.
Routing - Provides the framework for directing packets through the
fabric.
Protocol - The high-level set of rules for exchanging packets of data
between devices.

6. Physical - Consists of the actual wires carrying the signals, as well as


circuitry and logic to support ancillary features required in the
transmission and receipt of the 1s and 0s.
Data link - Is responsible for reliable transmission and flow control.
Transaction - Generates and consumes data packets used to
implement load/store data transfer mechanisms and manages the
flow control of those packets between the two components on a link.

7. a. A 32-bit microprocessor typically means that the address bus is


32 bits wide, which allows for 232 unique addresses. Each address

∴ Maximum memory capacity = 232 bytes = 4,294,967,296 bytes =


typically points to a byte (8 bits) of memory.

4 GB

b.
1. 32-bit local address bus and 16-bit local data bus:

- The address bus being 32 bits allows the processor to


address 232 bytes of
memory directly.

- A 16-bit data bus means that only 2 bytes of data can be


transferred at a

∴ Impact: The system would need two cycles to transfer a 32-bit


time.

instruction, potentially reducing speed compared to a system with a


32-bit data bus.

2. 16-bit local address bus and 16-bit local data bus:


- A 16-bit address bus can only address 216 bytes of memory,
which is 64 KB.

∴ Impact: The system can address much less memory (only 64 KB),
- A 16-bit data bus means 2 bytes can be transferred at a time.

and it would still require two cycles to transfer a 32-bit instruction.


This setup would be significantly slower and more limited in memory
addressing capability compared to a system with a 32-bit address
bus.

c. - Program Counter (PC): The PC holds the address of the


next instruction
to be executed. With a 32-bit address bus, the PC would
need 32 bits to
address any location in the 4 GB memory space.
- Instruction Register (IR):The IR holds the instruction
currently being executed. Since instructions are 32 bits wide,
the IR would also need 32 bits.

8. a. - Opcode: Bits 0 to 3 (4 bits)


- Address: Bits 4 to 15 (12 bits)
This means the instruction format is 16 bits long, where the first 4
bits represent the opcode, and the remaining 12 bits represent an
address in memory.

b. - Magnitude: Bits 0 to 15 (16 bits)


This suggests that the number format used by the hypothetical
machine is a 16-bit value representing the magnitude of a number.

c. The CPU registers and operations mentioned are:


- 0001: Load the Accumulator (AC) from memory. Fetch a
value from
memory and load it into the Accumulator.
- 0010: Store the AC to memory. Take the value in the
Accumulator and store it in memory.
- 0101: Add to AC from memory. Fetch a value from memory,
add it to the current value in the Accumulator, and store the
result back in the Accumulator.

These binary codes represent different instructions, and given the 4-


bit opcode, they would fit into the instruction format described
above.

d.

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