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FACULTY OF ENGINEERING
(AlCTE) (Main) (Now) Examination,
BE (CSET) I - Semester
March / April 2022
Subject: Digital Electronics
Max. Marks: 70
Time: 3 Hours
questions fron the
compulsory and answer any four
Note: (0) First question isquestions. Each Questions carries 14 Marks.
remaining six placeanly and in
question must be written at one
() Answer to each they occur in the question paper.
the same order as assumed.
suitably
(ii) Missing data, if any, may be
6
1. (a) State and prove DeMorgan's theorem.
k-map b'+ac'+a'cd.
(b) Represent the Boolean expression in adders.
(c) Draw a circuit of full adder using n and PRGA.
(d) Write the comparision between
(e) Design 4X16 decoder using 2X4 decodete
() Write the excitation table of RS andAKPE
(g) What is state assignment?
2 (a) Simplify the Boolean functigNg a minimum no. of literals
ABC+A'BABO
i) xy+x'z+yz i)
(bSimplityythe functionO24.6.9,11,13,15,17,21,25,27;29,31)
usitN-nap
EVW.X.Y,Z)= 2m ushg
Realize the circujt NANDgates.
circuit diagram.
a)Design a BCD -to-Decimal code converter withdiagram
Draw the block and truth table of a one
6jpefine magnitde comparator.
Show the implementation using logic gates,
bit magiude comparator.
) Wite hedt diagram explain FPGA architecture.
6)Realiz the given logic functions using PAL
1xx'+x'x
F2=x1'x+X1X2X3
with parallelload facility.
5 (a) Construct a 4-bit shift register
be converted to JK FF.
(b) Show that a aSR FF can
sequential circuits.
6 aiExolain the steps required to desgn 2411.12.13,14,15) using
F(A,B,C, D)=
(b) Implement the functionMUX.
i) 8:1 MUX and i)16:1
yusing Quine Mc Ciuskey tabular method
JaSaCD-~m(02or'3
(b) Write the Verilog
,9)+Ed(10,11)
for 3X8 decoders.
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Gode Ho F43636/HIAC
EACULTY OF ENGINEEain & Backiog) (Nw)
BE (ECE/CSEICMEIAISDS/AIRLIT
ERamination, Fatbruaryf March 202
Subject oigital Electronics
Max. Marks: 70
Times in eonouteory and arswer four guestions from the
ne los Each ouestion carrles 14 Marks.
() Answer to each question must be writton at one place onty and in the sarne
order as they occur in the question paper.
(i) Missing data, if any, may be sultably assumed.
1 a) Differentiate between variables and function
b) Diagrammatically show the mplernentation 1X8 dernuliple Msieg 1A demultiplexer
c) Give the block diagram of a comparator and state the inpóts outputs.
d) llustrate and explain the timing diagram of a 4-bit ring counter
e)Explain the Mealy FSM using a
9 llustrate the serial-in-parallel-outdiagram
shift register withh OFF
9) Explain the race-around condition
2. a) Simplify the function using Quine McClusky melhod
F(A,B,CD)=Em(0,24,6,7,9) +Em(10,11) and realize the function with basic gates
b) Simplify the expressions using Boolean
0(A+B) (A+B) (A4C) () xyztxxyz
algebra
3 a)Design and implementa 462 binary Priority Encoder
b) Design and implement a Blary to Gray codet converter.
Aa) Draw the 3-input LUT and explain.
Program the LUT to jmplement the logic function F = XXa'X3 where X1 is the MSB.
b) Draw and explain the structure of the CPLD.
5, a) Conveg the TKEoJKFF.
by Design and implement a 3-bit Synchronous counter using TFF.
6. a) Explain in detail the design and operation of a universal bi-directional shift register.
b) Give the state table &ASM chart for the following
a) Give the complete steps involved in simplifying Boolean expressions using
Ilustrate using 4-variable K-map. Karnaugh's M
5) Design and implement a 4-bit parity checker circuit.
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Code No E-5038IOIBUAICTE
BE. (ECE/CSEIT)
FACULTY OF ENGINEERING
-Semester (AICTE) (Back)(Old) Examination, September / October 2023
Subject: Digital Electronics
Time: 3 Hours
(Missing data, if any. may be suitably assumed) Max, Marks: 70
PART- A
Note: Answer all the questions.
(10 x 2 20 Marks)
1 Implement the function F (ABC. D) ABC+ (C+A)D using switches
2 List different menory types in a
computer
3. Define variables in logic circuits.
4. Represent (-7) in signed magnitude and 2 complement form1 6 0 4
5. Give the truth table and logic expression for a 2X1 multiplexer.
6. Draw the general structure of a Programmable Array Logic (PAL).
7. Depict the structure of a 2-input LUT with a diagram.
8. Explain the race-around condition.
9. Differentiate between Moore and Mealy FSM.
10.Draw and explain the parallel-in-paralel out registes
PARTB
(5x 10 50 Marks)
Note: Answer any five questions.
11. Minimlze using K-Map and implement using NOR gates
F(a, b, c, d) =(0.1,4,6,8,9, 10, 12))+ d(57)
a BCD to 7-segment code converter
12. Glve the truth table, minimize and iiplement
&explain it.
13. a) Draw the structure of an FPGA
b) Reallze a half adder using a look-up table
asynchronous counter and give its waveforms
14. a) Realize a 4-bil
Jahnson's counter and realize a mod-6
Johnson's counter
b) Explain the
overlapping
a sequence detector to
detect the sequence 1010 in
15. Design and implement
mode with T-Flip-Flop.
explain the steps in detail.
T-Flip-Flop to a JK-Flip-Flop and priority encoder.
16. a) Convert a diagram of a four (04)
input
b) Give the logic method
the function using Quine McClusky
simplified expression for (10,11).
17. a) Obtain the D) =Em
(0,2,4,6.7.9) +Ld
F (A B, C, unsigned numbers.
notes on signed and
b) Writea short
O
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Code No.D-2370 INIAICTE
FACULTY OF ENGINEERING
BE (CSENT) II- Semester (AlCTE) (Main) (New) Examination,
March / April 2022
Subject: Digital Electronics
Time: 3 Hours Max. Marks: 70
Note: (9) First question is compulsory and answer any four questions from the
remaining six questions. Each Questions2
carries4
14 Marks.
5 3
(i) the
Answer to each question must be written at one place only and in
same order as they occur in the question paper.
(iii) Missing data, if any, may be suitably assumed.
1. (a) State and prove DeMorgan's theorem.
(b) Represent the Booleaadeson in k-map b'+ac'+a'
(c)) Draw a circuit of hl
(d) Write the comparision behwoon cRL addet
(e) Design 4X16 decoder using 2X4 daend
() Write the excitation table of RS andAK PE
(9) What is state assignment?
2 (a) Simplify the Boolean functipno a minimum no. of literals
)xy+x'z+yz i) ABC+ABABO
(b) Simplify the function usfogRhap
F(V,WX,Y,Z)= Zm(04.6911,13,15,17,21,25,27,29,31)
Realize the circuituslpeNAND gates.
3 (a) Design a BCD -to-Decimal code converter with circuit diagram.
(b) bitDefine magnityde comparator. Draw the block diagram and truth table of aone
magnitude comparator. Show the implementation using logic gates.
4 (a) Witheheaf diagram explain FPGA architecture.
(b) Realize the given logic functions using PAL
Pix2s+xx3
F2-x1'x'+xxX3
5 (a) Construct a 4-bit shift register with parallel load facility.
(b) Show that a SR FF can be converted to JK FF.
6 (a) Explain the steps required to design synchronous sequential circuits.
(b) Implement the function F(A,B,C,D)= Sm(1,3,4,11,12,13,14,15) using
i) 8:1 MUX and i)16:1 MUX.
7 (a) Simplify using Quine Mc Cluskey tabular method
F(A,B,C.D)-~m(0.2.4,6,7,9)+Ed(10,11)
(b) Write the Verilog code for 3X8 decoders.
11:35 .00
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1
FACULTY OF ENGINEERING
B.E. (AICTE) (ECE/CSE/I) II-Semester (Suppl) Examination, Decermber 2020
Time: 2 Hours Max. Marks: 70
Note: (Missing data i, any can be assumed suitable).
PART -A
Answer any five questions.
(5x2= 10 Marko)
1. State and prove De Morgan's laws and show their implenentation using
fuctaretet
2. Prove that the dual of xOR is XNOR.
NAND
5. Write the comparison between a PLA and PAL?
B been Conbinational and Sequential circuits
8. Conpare and contrast between synchronous and asynchronous counters?
C ealy PsMs
10. Explain notationot
PART-B
Answer any four questions. (4x 15 6 0 Marks)
b) Reduce the following functions using a K-Map method
f(a, b, c, d) = n(4,5,7,12,14,15) + dc(3,8,10)
12.o) Inplerment full adder using 3x8 decoder and suitable gates
b) What is Priority Encoder? Design 4x2 Priority Encoder with appropriate gates?
13.a) Draw the block diagram and explain architecture of a PLA
b) Explain architecture of FPGA with a neat circuit diagra.
14.a) Design Mod-6
timing synchronous
diagrarn counter using JK Flip-Flops and explain its operation
b) Convert D- Flip Flop to JK Filp Flop
15.a) Draw and explain Circuit of master slave JK Flip - Flop
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1. State and prove De Morgan's laws and show their implementation using
fundamental gates
2. Prove that the dual of XOR is XNOR.
3. Design half subtractor using only NAND gates.
4. What are the applications of muitiplexer?
5. Write the comparison between a PLA and PAL?
6. What is acronyn tor
vDEionol and Seguential circuits
8. Compare and contrastbetweensynchronous and asynchronous counters?
9. Distinguish between Moore and Mealy FSMs
10. Explain notation of an ASM chart?
PART-B
Answer any four questions. (4x 15 60 Marks)
)Epanx
b) Reduce the followin function Map method
f(a. b. c. d) =m(4.5.712.14.15) + dc(3.8.1o)
12. a) Implement full adder using 3x8 decoder and suitable gates
b) What is Priority Encoder? Design 4x2 Priority Encoder with appropriate gates?
13. a) Draw the block diagram and explain architecture of a PLA.
b) Explain architecture of FPGA with a neat circuit diagram.
14. a) Design Mod-6 synchronous counter using JK Flip-Flops and explain its opera
with a timing diagran.
b) Convert D-Flip Flop to J-K Filp Flop
15. a) Draw and explain Circuit of master slave J-K Flip- Flop
b) Explain the operation of positive edge triggered T Flip-Flop with active low
preset and clear inputs through its truth table.
16. Simplify the following function using Tabulation method,
f(a, b, c, d) = m (1,3,5,8,9,11,15).
17. a) Write Verilog code for a JK Flip-Flop using case statemnent.
b) Draw ASM chart for a 1010 sequence.
