LECTURE 5: HAZARDS IN PIPELINING

Course Website

https://iit-plt.github.io/cs528/
Practice Problem - 1
◦Consider a pipeline having 5 phases with duration 30, 40,
60, 70 and 50 ns. Given latch delay is 10 ns. Calculate-
◦ Pipeline cycle time
◦ Non-pipeline execution time
◦ Speed up ratio
◦ Pipeline time for 100 tasks
◦ Sequential time for 100 tasks
 Solution
◦ Given:
◦ Delay of stages = 30, 40, 60, 70, and 50 ns
◦ Latch Delay = 10 ns
◦ Pipeline Cycle Time = Max (Delay of stages) + Latch Delay
= (70 + 10) ns = 80 ns
◦ Non-pipeline execution time for one instruction
◦ = 30 ns + 40 ns + 60 ns + 70 + 50 ns = 250 ns
◦ Speedup ratio = Non-pipeline / Pipeline = 250/80 = 3.125
◦ Pipeline time for 100 tasks = Time taken for 1st task + Time taken for remaining 999
tasks
= 1 x 5 clock cycles + 99 x 1 clock cycle = 5 x 80 ns + 99 x 80 ns = 8320 ns
◦ Sequential Time For 100 Tasks = 100 x Time taken for one task = 100 x 250 ns
= 25000 ns
 Practice Problem - 2
◦ A four stage pipeline has the stage delays as 50, 60, 80 and 70 ns respectively.
Registers are used between the stages and have a delay of 5 ns each. Assuming
constant clocking rate, the total time taken to process 10000 data items on the
pipeline will be-
◦ Pipeline cycle time = Max (Delay due to any stages) + 5 = 85 ns
◦ Pipeline to process 10000 = Time taken for 1st data item + Time taken for
remaining 9999 data items
= 1 x 4 clock cycles + 9999 x 1 clock cycle = (4 * 85) + (9999 * 85)
= 850255 ns
Pipelining Hazards
◦ Hazards: situations that prevent the next instruction from
executing in the designated clock cycle.
◦ Structure hazards
• A required resource is busy
• Data hazard
• Need to wait for previous instruction to complete its data
read/write
• Control hazard
• Deciding on control action depends on previous instruction
• Program Counter (PC) changes (e.g., branches)
Structural Hazards

◦ Conflict for use of a resource

• In MIPS pipeline with a single memory
• Load/store requires data access
• Instruction fetch would have to stall
for that cycle
• Would cause a pipeline “bubble”
• Hence, pipelined data paths require separate
instruction/data memories
• Or separate instruction/data caches
Structural Hazard

◦Root Cause: resource conflicts

e.g., a processor with 1 reg write port
but intend two writes in a CC
◦Solution
stall one of the instructions
until required unit is available
Structural Hazard
MEM ◦Example
1 mem port
Load mem conflict

Instr i+1 data access

vs
Instr i+2 instr fetch
IF
Instr i+3
Structural Hazard

Stall Instr i+3

till CC 5
Structural Hazard

◦Example
ideal CPI is 1;
40% data references;
structural hazard with 1.05 times higher clock rate than ideal;
Question:
is pipeline w/wo hazard faster?
by how much?
Structural Hazard
Stall for
one clock cycle
◦ Answer
avg instr time without hazard
=CPI x clock cycle timeideal
=1 x clock cycle timeideal

avg instr time with hazard

=(1 + 0.4x1) x clock cycle timeideal
1.05
=1.3 x clock cycle timeideal

So, without hazard is 1.3 times faster.

Data Hazard
◦Data hazards: an instruction cannot continue because it
needs a value that has not yet been generated by an earlier
instruction
◦Root Cause: data dependency
when the pipeline changes the order of read/write accesses to
operands;

so that the order differs from the order seen by sequentially

executing instructions on an unpipelined processor.
Data Hazards
◦read-after-write (RAW) hazard
add r1, r2, r3
add r4, r1, r5
◦write-after-read (WAR) hazard
add r1, r2, r3
add r2, r4, r5
◦write-after-write (WAW) hazard
add r1, r2, r3
add r1, r4, r5
RAW Hazard

value available value needed value written

add r1,r2,r3 IF ID EX MEM WB

add r4,r1,r5 IF ID ID ID ID EX MEM WB

IF IF IF IF ID EX MEM
Data forwarding (bypasses)

IF/ID ID/EX EX/MEM MEM/WB

NPC

MUX
A

ALU
RF D$

MUX
B

MUX
IMM
Data forwarding (bypasses)

IF/ID ID/EX EX/MEM MEM/WB

NPC

MUX
A

ALU
RF D$

MUX
B

MUX
IMM

preliminary:
moved this
mux to prior
stage
Data forwarding (bypasses)

bypass 3

IF/ID ID/EX EX/MEM MEM/WB

bypass 2
bypass 1
MUX
NPC

MUX
A

ALU
RF D$

MUX
B

MUX
MUX

IMM
Data forwarding (cont.)

byp 1 byp 2 byp 3

add r1,r2,r3 IF ID EX MEM WB

add r4,r1,r5 IF ID EX MEM WB

add r6,r1,r5 IF ID EX MEM WB

add r7,r1,r5 IF ID EX MEM WB

add r8,r1,r5 IF ID EX MEM WB

Stalls due to RAW hazards
◦ With bypasses
◦ No stall if producer is ALU type instruction
◦ Unavoidable 1-cycle stall if producer is a load instruction (cache hit) AND its dependent instruction is
right behind it. This is because the dependent instruction must wait for BYPASS 2 for the load value.
◦ Note: If an instruction takes multiple cycles in EX (e.g., complex ALU operation) or multiple cycles in MEM
(load/store cache miss), all instructions behind the long-latency instruction stall whether or not they
depend on the data. The stall is attributable to a structural hazard caused by the current pipeline design
(EX and MEM stages are “blocking” for multi-cycle instructions).

value needed value available

byp 2
lw r1,#0(r2) IF ID EX MEM WB

add r4,r1,r5 IF ID ID EX MEM WB

IF IF ID EX MEM
WAR and WAW Hazards
◦ WAR hazard
◦ A: ADD R1, R2, R3
◦ B: ADD R2, R4, R5
◦ Problem if B writes R2 before A reads R2
◦ A will get the wrong value of R2 (that of B)
◦ Doesn’t happen in most in-order pipelines (like ours)
◦ Happens in out-of-order pipelines
◦ A may be stalled and B may be ready to execute out-of-order and write R2
◦ WAW hazard
◦ A: ADD R1, R2, R3
◦ B: ADD R1, R4, R5
◦ Problem if B writes R1 before A writes R1
◦ Later instructions will get the wrong value of R1 (that of A)
◦ Doesn’t happen in most in-order pipelines (like ours)
◦ Happens in out-of-order pipelines
◦ A may be stalled and B may be ready to execute out-of-order and write R1 first
WAR and WAW Hazards (cont.)
◦Options for handling WAR and WAW hazards
◦ Stall the later instruction to defer its register write, OR
◦ Register renaming (see next major topic: ILP)

◦Either way, compiler can limit the occurrence of WAR and

WAW hazards by limiting the reuse of destination register
specifiers among nearby instructions
Types of program dependencies
◦ True dependence (pure dependence, flow dependence)
◦ ADD R1, R2, R3
◦ ADD R4, R1, R5
◦ Causes RAW hazard if the two instructions are in the pipeline concurrently
◦ Anti-dependence
◦ ADD R1, R2, R3
◦ ADD R2, R4, R5
◦ Causes WAR hazard if the two instructions are in the pipeline concurrently
◦ Output dependence
◦ ADD R1, R2, R3
◦ ADD R1, R4, R5
◦ Causes WAW hazard if the two instructions are in the pipeline concurrently
Program dependencies (cont.)

◦ A true dependence is called that, because there is truly a data

dependency between the two instructions
◦ Producer-consumer relationship
◦ Second instruction needs the data produced by the first
◦ Anti-dependence and output dependence are sometimes clubbed
together as false dependence because there isn’t actually a data
dependency between the two instructions, just a register conflict
Thank You