Paper ID #36964

A Novel Project-Oriented System on Chip (SoC) Design

Course for Computer and Electrical Engineers
Bill D Carroll (Professor)
Bill Carroll is Professor of Computer Science and Engineering at The University of Texas at Arlington (UTA). He has
been a UTA faculty member since 1981 and also has held faculty positions at Auburn University and visiting
appointments at the University of California-Berkeley and the University of Washington. He has held engineering
positions at Texas Instruments and General Dynamics. Carroll received B.S., M.S., and Ph.D. degrees in electrical
engineering from the University of Texas at Austin. He is a Life Fellow of the Institute for Electrical and Electronics
Engineers (IEEE) and a licensed professional engineer in Texas and Alabama. Carroll has co-authored three textbooks, a
tutorial book, and numerous papers and technical reports. He has received an American Society for Engineering
Education Outstanding Young Faculty Award, two National Aeronautics and Space Administration Technology
Innovation Awards, and three IEEE Computer Society Service Awards. He is an IEEE Computer Society Golden Core
Member and a recipient of the IEEE Third Millennium Medal. Carroll served as chair of the UTA Faculty Senate from
September 1, 2019 to August 31, 2021. He served as Dean of the College of Engineering at UTA from January 1, 2000 to
August 31, 2011 and chair of CSE from June 1981 to August 1999.

Jason Losh (Professor of Practice)

© American Society for Engineering Education, 2022

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A Novel Project-Oriented System on Chip (SoC) Design Course for Computer
and Electrical Engineers

Bill D. Carroll, Ph.D., P.E. and Jason H. Losh, Ph.D.

Computer Science and Engineering Department
The University of Texas at Arlington

Abstract
This paper describes a novel project-oriented system on chip (SoC) design course. The course is
taught in the Computer Science and Engineering (CSE) Department at the University of Texas at
Arlington and is offered as CSE 4356 System on Chip Design for computer engineering
undergraduates, as CSE 5356 for computer engineering graduate students, and as EE 5315 for
electrical engineering graduate students. It is taught as one course combining all numbers. All
students are given the same lectures, course materials, assignments, and projects. Grading
standards and expectations are the same for all students as well. The course in its current form
was first offered in fall 2020 and was taught online due to COVID-19 restrictions. The course
was offered again in fall 2021 in a traditional on-campus, in-person mode of delivery. Two
seasoned educators, with more than eighty years of total teaching experience, combined to team
teach the course. One also brought more than thirty years of industrial design experience to the
course.
SoC FPGA devices have been available for use by designers for more than 10 years and are
widely used in applications that require both an embedded microcomputer and FPGA-based
logic for real-time computationally-intense solutions. Such solutions require skills in C
programming, HDL programming, bus topologies forming the bridge between FPGA fabric and
the microprocessor space, Linux operating systems and virtualization, and kernel device driver
development.
The breadth of the skills that were conveyed to students necessitated a team teaching approach to
leverage the diverse background of the instructors.
With such a wide range of topics, one of the biggest challenges was developing a course that was
approachable for a greatly varied population of students – a mix of Computer Engineering (CpE)
and Electrical Engineering (EE) students at both the graduate and undergraduate level.
Another, perhaps less obvious, challenge was the inherently application focus of the course,
which presents challenges to many graduate students whose undergraduate degree lacked a
robust hands-on design experience.
Selection of an appropriate project was key to making the course effective and providing a fun
learning experience for students. The projects were aligned to relevant industry applications,
stressing complex modern intellectual property (IP) work flows, while still being approachable to
students. The design of a universal asynchronous receiver transmitter (UART) IP module in
2020 and a serial peripheral interface (SPI) IP module in 2021 were chosen as the projects for the
first two offerings of the course.
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The Terasic/Intel DE1-SoC development board and Intel Quartus Prime 18.1 design software
were the technologies chosen for the course. The development board and basic test instruments
were provided to each student in a take-home lab kit.
The system on chip design course has proven to be a popular but challenging course for our
undergraduate and graduate students in computer engineering and electrical engineering. The
course has demonstrated that it is possible to successfully teach an advanced design-oriented
course to students of varying majors, levels, educational backgrounds, and cultures.

Introduction

System-on-Chip (SoC) Field-Programmable-Gate-Array (FPGA) devices have been available for

for more than 10 years and are widely used in applications that require both an embedded
microcomputer and real-time computationally-intense solutions. Hence, it is important to
provide students studying computer engineering and electrical engineering an opportunity to
learn how to develop industry-relevant intellectual property (IP) modules before they graduate.

The complexity of SoC devices makes it difficult to incorporate them in other courses such as
digital logic, embedded systems, or computer architecture. Also, many current graduate students
did not have an opportunity to learn SoC technology as undergraduates. So we chose to develop
a standalone course that can be taken as an elective by seniors or graduate students.

The course is taught in the Computer Science and Engineering (CSE) Department at the
University of Texas at Arlington and is offered as CSE 4356 System on Chip Design for
computer engineering undergraduates, as CSE 5356 for computer engineering graduate students,
and as EE 5315 for electrical engineering graduate students. It is taught as one course combining
all numbers. All students are given the same lectures, course materials, assignments, and
projects. Grading standards and expectations are the same for all students as well.

The subject matter difficulty coupled with diverse student backgrounds made this course difficult
to design and teach. However, we are satisfied with the results of the first two offerings and
wish to share our results so that others can benefit. The remainder of the paper is organized in to
four sections – background and motivation, course description and structure, observations and
student survey results, and conclusions and future plans.

Background and Motivation

The development of SoC solutions require skills in C programming, HDL programming, bus
topologies forming the bridge from FPGA fabric to/from microprocessor space, Linux operating
systems and virtualization, and kernel device driver development.
The breadth of the skills that were conveyed to students necessitated a team teaching approach to
effectively cover the course topics and leverage the diverse background of the two faculty
members. One instructor has more than fifty years of teaching in computer engineering and
electrical engineering programs and the other more than thirty years of industry experience plus
thirty years teaching as an adjunct.
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With such a wide range of topics, one of the biggest challenges was developing a course that was
approachable for a greatly varied population of students – a mix of Computer Engineering (CpE)
and Electrical Engineering (EE) students at both the graduate and senior level.
Students were required to have knowledge of basic circuits, digital logic, embedded systems, and
to have had experience with hardware description languages (Verilog or VHDL).

Table 1 shows the enrollments by major and level in both offerings of the course.

Table 1 – Course Enrollments

Fall 2020 Fall 2021

UG Grad UG Grad
CpE 6 0 6 6
EE 0 15 1 1
Subtotals 6 15 7 7
Total 21 14

Portions of this course have been offered as a special topics course to EE students over the past
10 years with greatly varied outcomes. The lack of robust C programming skills, knowledge of
VHDL vs Verilog HDL, and no background in operating systems by some students required
careful consideration of how to properly provide the necessary leveling.
Another, perhaps less obvious, challenge was the inherently application focus of the course,
which presents challenges to many graduate students whose undergraduate degree lacked a
robust hands-on design experience. To help address this concern, the embedded system course,
which has a significant hardware construction component, was required as a prerequisite.
Selection of an appropriate project was key to making the course effective and providing a fun
learning experience for students. The projects were aligned to relevant industry applications,
stressing complex modern intellectual property (IP) work flows, while still being approachable to
students. The design of a universal asynchronous receiver transmitter (UART) IP module in
2020 and a serial peripheral interface (SPI) IP module in 2021 were chosen as the projects for the
first two offerings of the course.

Course Description and Structure

The catalog description of the courses reads “Programming and implementation of FPGA-based
system on chip solutions, including processor subsystems, FPGA fabric, processor to FPGA
bridges, and device drivers.” It is structured as a semester-length, three credit hour course. The
course is heavily lab- and project-oriented. Students are given the flexibility to work at home
and attend staffed open lab as best suiting their needs. To allow this, two take home lab kits
were checked out to each student to use on assignments and projects (more details to follow)
while open labs allowed students to access more capable test equipment or seek attention from
the faculty or teaching assistants as needed.

The first offering of the course in fall 2020 was taught online due to the COVID-19 restrictions.
The take home kits accommodated this arrangement well. All lectures were recorded and made
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available to the students for review. The second offering of the course in fall 2021 was planned
for in person, on campus. However, an increase in COVID-19 cases caused a pivot to online for
the first two weeks of the semester. The take home lab kits and the experience from fall 2020
made this pivot to online seamless.

One lab kit contained the hardware and components needed to implement the assignments and
projects. See Fig. 1 for a picture of the kit and its contents. The second kit contained basic
instruments needed to analyze, test, and debug designs. See Fig. 2 for the contents of this kit.

The Terasic/Intel DE1-SoC development board [1] and Intel Quartus Prime 18.1 design software
[2] were the technologies chosen for the course. The DE1-SoC is based on the Intel Cyclone V
FPGA. The Cyclone V consists of an FPGA fabric and a hard processor subsystem as shown in
Fig. 3 [3]. Verilog was chosen as the hardware description language to be used since that’s the
language used in the computer engineering program which offers the course.

Fig. 1 – DE1-SoC Lab Kit.

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Fig. 2 – SoC Test Instrumentation Kit.

Fig. 3 – Intel Cyclone V Block Diagram [3].

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To level the students, the first 40% of the course reviewed digital logic fundamentals and Verilog
programming. Five simple design assignments and an on-campus, in-person exam constituted
this portion of the course. The assignments consisted of a digital lock controller, register file,
synchronous FIFO buffer, digital timer, and a fractional-rate baud rate generator.

To address the aforementioned deficiencies in operation systems, a compact review of the Linux
operation system was also provided.

During the remainder of the course, a series of IP design examples were developed in class,
including GPIO, quadrature encoder, and PID controller modules. Each example developed the
complete solution including the Verilog code, hard processor subsystem (HPS) to FPGA bridge,
user- and kernel-space code to control the IP module, and character device drivers. The goal is
these complete designs was to provide a framework upon which to write the IP module required
in the project, without the tedious steps and deeply knowledge-based information needed to
develop these solutions.

Two in-person exams were used to assess their knowledge. The final course project required that
students develop an entire IP solution from Verilog to Linux device drivers. In the project
defense, the students were given their choice of a variety of hardware devices to interface with to
show that their solution worked.

Table 2 Lists the topics covered in the course. Table 3 shows the course assignments.

Table 2 – List of Topics Covered in the Course

Course overview (1 hr) Project-specific lectures (4.5 hrs)

Intro to DE1-SoC kit and check out. (0.5 hr) AMBA, AXI, and Avalon MM interface (1 hr)
Review of combinational logic, Verilog, and Using the Quartus Platform Design (was Qsys)
Quartus Prime. (1.5 hrs) (1.5 hr)
Review of sequential logic, Verilog, and Quartus Designing a memory-mapped register interface
Prime (3 hrs) (1.5 hrs)
Designing a GPIO peripheral with interrupts (2
Designing registers and register stacks (1.5 hrs)
hrs)
Designing a quadrature peripheral handling
Designing FIFO buffers (1.5 hrs)
asynchronous inputs (1.5 hrs)
Designing counters and clock dividers (1.5 hrs) Case study: Designing a PWM peripheral (2 hrs)
Designing clocks and timers (1.5 hrs) Virtual memory interface (/dev/mem) (1 hr)
Virtual file system (/sys/class/*) kernel module
Using Signal Tap Logic Analyzer (1.5 hrs)
design (1.5 hrs)
Designing fractional rate dividers (1.5 hrs) Higher-level kernel modules (1 hr)
Project introduction, selection of teams (0.5 hrs) Interrupts in Linux (1 hr)
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Table 3 – List of Laboratory and Project Exercises

Exercise Topic Comments

Lab 1 Design of a Digital Lock Controller A warm up exercise.
Lab 2 Design of a Register File Easy step toward a FIFO.
Lab 3 Design of a Synchronous FIFO Buffer A key component for the projects.
Lab 4 Design of a Digital Timer Gain familiarity with clock dividers.
Lab 5 Design of a Baud Rate Generator Programmable using fractional dividers.
Data register interfaces for
Project step 1
communications FIFO
Project step 2 FIFO status register interface
Fractional rate was used even for the
Programmable fractional rate clock source synchronous interface to allow spur
Project step 3
with register interface reduction in a SPI DAC-based DDS
application
Supporting different word sizes, for-
Project step 4 Design of transmit serializer
mats, and multiple chip selects (SPI)
Project step 5 Design of receiver deserializer
User-space command-line utility to
Project step 6
control IP block
Loadable kernel module (LKM) to
Project step 7
provide a character device driver

Observations and Student Feedback

As mentioned earlier, attempts to teach aspects of this material in a special topics course resulted
in greatly varied results. Those afforded invaluable input on some of the problems that needed to
be addressed in this new course.

The first (fall 2020) offering of the course was viewed as a success with a few caveats and areas
needing improvement. One Covid-19 related action by the university administration had an
interesting impact. Late in the semester, a decision was made to allow students to choose a
pass/fail grade option in certain courses. A few students in the SoC course took that option and
it seemed to influence their performance on the term project.

Other observations from the first offering were that student’s background in digital logic
fundamentals were more uniformly solid than expected and that Verilog programming skills
were weaker than expected. These led to reducing the time spent on review of digital logic in the
second offering (fall 2021). It also led to an increase in the coverage of Verilog in the
introductory digital logic course taught in the department.

Observations in the second offering suggest that further reduction in the review of digital logic
may be appropriate to provide more time for review of Linux and C programming. A final
decision on this has not yet been made.

When surveyed, 31% of the students replied that their HDL prerequisite knowledge was in
VHDL instead of Verilog. Despite this fact, the actual statistics surprisingly show a 3.5% better
result for students completed labs with the VHDL background instead of Verilog as used in the
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course, indicating that despite the small sample size and non-intuitive result, this difference has
likely been adequately addressed.

Another notable observation was seen in the Linux device driver aspects of the exams were
answered successfully by 86% of the EE students and 90% of the CpE students, which is near
equity. This represents a substantial improvement over the previous outcomes in the range of 60
to 65% mastery in past SoC special project courses in the EE Department.

Despite efforts to address the deficiency of some EE students, the embedded microprocessor side
of the project is where notable shortcomings still existed. In some cases, the use of pointers,
macros, and structures in C were just not understood well. On the project, the kernel driver work
was only completed by 37% of these students which is at odds with the test results. Also
obvious in about 50% of the EE students was a lack of architectural aspects of the computer,
such as bus cycles and their timing, although the degree of success on the FPGA-HPS interface
of the system was successful in all but 2 of the teams.

Also encouraging was the fact that all but one team that completed the overall design of the
project were able to interface an external device without difficult and develop the higher-level
device driver.

Conclusions and Future Plans

The system on chip design course has proven to be a popular but challenging course for our
undergraduate and graduate students in computer engineering and electrical engineering. The
course has demonstrated that it is possible to successfully teach an advanced design-oriented
course to students of varying majors, levels, educational backgrounds, and cultures.

The approaches taken to leveling students’ knowledge and skills needs further work since the
current approach has proven to be challenging for some students and boring for others.

In future versions of the course, the goal is to develop:

- flipped classroom modules for reviewing digital logic fundamentals and Verilog programming,
- a more exhaustive primer on C programming for students without this prerequisite knowledge,
- a self-study package or lab on the AMBA and Avalon buses and their timing.

An unexpected outcome of the course was the identification of weaknesses in prerequisite

subjects, such as, C programming, Verilog programming, and operating systems. These are
being addressed as mentioned above and through changes in prerequisite courses.

References

1. DE1-SoC User’s Manual, www.terasic.com, January 28, 2019.

2. Quartus Prime Introduction: Using Verilog Designs (For Quartus Prime 18.1), Intel
Corporation – FPGA University Program, March 2019.
3. Cyclone V Device Handbook, Altera Corporation, June 2012.