Seamless SoC Verification Using Virtual Platforms:

An Industrial Case Study

Kyungsu Kang1, Sangho Park, Byeongwook Bae, Jungyun Choi, SungGil Lee, Byunghoon Lee and Jong-Bae Lee
Design Technology Team, Memory Business, Samsung Electronics, Korea
1
[email protected]
Abstract— As SoC (System-on-Chip) complexity continues to
increase, function/performance verification is required in the II. PROPOSED VERIFICATION METHODOLOGY
middle of design process (before tape-out) to reduce the possible Fig. 1 shows the proposed SSD development process. In the
risks ranging from over-design to non-compliance with the
design specifications. In this paper, we propose a seamless SoC early design stage, VP-1, which consists of only SystemC
verification. The proposed methodology exploits a modern models, is used to determine product architectures as well as IP
virtual platform (VP) technology which can combine high-level design parameters e.g., SRAM buffer size, data-flow control
C++ firmware, timing-accurate SystemC models, and RTL policy, operating clock frequency. Because VP-1 is much
(register-transfer level) designs. Thus, the full-chip level faster and flexible than RTL simulation, many full-chip level
verification can be done at any design stages in the whole test scenarios can be simulated. However, the development of
development process. With experimental results, this paper VP-1 is not just assembling existing library components (e.g.,
shows the benefits and lessons of using VPs. processor model, bus model, memory model, etc.) available in
Keywords— Virtual platform, Verification, Design space commercial tool libraries, but it demands significant amount of
exploration, SystemC/TLM, Solid-state drive (SSD) manual works, e.g., developing SystemC models for legacy IPs
with a tight development schedule. For that, we should not
I. INTRODUCTION model all the components of SSD with full cycle accuracy, but
In this paper, we propose a seamless SoC verification classify them with respect to the accuracy requirements, i.e., 1)
methodology which is a continuous verification process from full cycle accuracy, e.g., asynchronous buffers, 2) latency-
design specifications to silicon available with full-chip level throughput accuracy, e.g., DMA controllers, 3) untimed
test scenarios and simulations. It helps engineers determine the accuracy, e.g., HOST computers.
design parameters at the early design stage and verify the As time goes, IPs are implemented in order and they need to
gradually implemented HW/SW designs with a consistent be fully verified with respect to the specifications. Usually, in
verification environment until a hardware prototype is ready. development, interconnects and memory controllers (i.e.,
This seamless verification is feasible thank to the support of SRAM/DRAM controller) are implemented earlier than the
co-simulation between SystemC models and RTL designs in other IPs, because IP designers get help from third-party design
VP technology. The contributions of this paper are as follows. tools [1]. Verifications of them are crucial because the behavior
x This paper presents an industry case study of applying VP of generated RTL designs from the design tools might not be
technology for the seamless SoC verification. As far as the what the designers expect and the performance bottleneck of
authors know, this is the first work that uses VPs in the them seriously degrades the whole SoC performance. By
whole design and verification processes, not just in a part of replacing some SystemC models in VP-1 with the target RTL
design stages. DUTs (Design Under Test), VP-2 makes it possible to validate
them with the same full-chip level scenarios used in VP-1
x This paper reports practical issues, strategies, and benefits before the other master/slave designs are available. In VP-2, in
of using VP technology for a real product, i.e., SSD (Solid order to make a communication between SystemC model and
State Drive), development in industries. RTL DUTs, there must be a transaction-signal converter which
Section II presents the proposed verification methodology. The connects a TLM interface of SystemC model to the
lessons learned in the case study are summarized in Section III. corresponding signal inputs and outputs of RTL design. For the
protocol converters, there are commercial tools that supports
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them as libraries [2]. Through VP-2, we basically validate the usually determined only for HW and SW engineers, not for VP
connectivity, latency, and throughput of interconnects as well modeling engineers. Also design specifications were frequently
as the efficiency, latency, and throughput of SRAM/DRAM. In changed even during the design progress. To tackle the issues,
addition, we evaluate various candidate designs that have it was required to contact each HW and SW engineer on a
different parameter configurations. In our experience, with person-to-person basis, not just relying on the documents.
various interconnects evaluations, we got the final interconnect Second, we used ARM Fast Models that are loosely-timed
design with the gate-counts and power consumption reduced (LT) models. Because they are not cycle-accurate virtual
by 41% and 42%, respectively. For the power estimation, there models, it is hard to use them for SW optimization in the view
are commercial tools [3] that estimate the power consumption of performance. Thus, we consider to use ARM cycle model
from simulation waveform dump. [6] for the next project. At last, in this work, the VP was
developed to endure only for the functional verifications of
VP-3 is used to verify implemented RTL designs that main data paths. If you want to use it for HW/SW regression
communicate with a CPU running firmware. In the test, you need to develop a different type of VPs, either a VP
conventional design process, since a set-up of hardware that consists of only fast virtual models or a hybrid emulation
prototype (e.g., FPGA or HW emulator) happens much later, that makes it possible to communicate between virtual models
both HW and SW designers have no choice but to lean on only and real designs synthesized in a hardware prototype.
RTL simulation for the HW/SW verifications. Because of the
limitations of RTL simulation, i.e., lower simulation speed, no
support of SW debugger, difficulties to make full-chip level TABLE I. DESIGN FAULT LIST DETECTED THROUGH VPS
verification environment, it is hard to fully verify their Verification Category VP Type Count
implementations. In VP-3, a commercial virtual model, i.e., Interconnect & Buffer performance
ARM fast model[4], is used in conjunction with SW debuggers VP-2 3
degradation
(e.g., Trace-32 [5]). Thus, VP-3 helps not only reduce the IP HW performance degradation VP-1, VP-2, VP-3 7
verification efforts but also develop and verify early SW HW/SW functional fault VP-2, VP-3 16
functions (e.g., boot code, basic operations, etc.) before the
hardware prototype available. In our experience, VP-3 was TABLE II. SIMULATION PERFORMANCE COMPARISONS
available 6 weeks ahead of FPGA. It was used for early SW
VP Type Simulation Time RTL IP
bringing up as well as design flaw detections. Thus, the set-up VP-1 0.0015 None
time of FPGA has been reduced by 2 months. VP-2 0.0410 Interconnects
VP-3 0.0761 Host I/F only
III. EXPERIMENTAL RESULTS (LESSONS LEARNED) RTL 1.0000 Host I/F Sub-System w/o CPUs

Creating a VP for early design stage demanded modeling IV. CONCLUSION

SystemC components within a given tight development
schedule with the limited man-power. Thus, a practical strategy In this paper, we presented an industry case study of
was required, and we did only the least of what we had to do. applying VP technology to real product development. The use
As development goes, we replaced SystemC models with the of proper VPs makes the seamless SoC verification possible. In
corresponding RTL designs. This approach, i.e., first creating a the early design stage, VP was used to determine the
VP with fast and flexible models only, then replace them with performance-related design parameters. As development goes,
slow-but-accurate ones later, makes it possible to do seamless SystemC models were gradually replaced by real RTL designs
SoC verification while meeting the time-to-market constraint and the VP was used to verify them with full-chip SoC test
for the real product development. Table I summaries the design scenarios. Product SW was brought up early on ARM fast
faults being found from a SSD development project. In order to model so that HW/SW functional verifications were done. In
find the design faults, a long-term full-chip level simulation our experience, the VP for HW/SW co-verification was
was required, where either spreadsheet program or RTL available 6 weeks ahead of FPGA and the use of VP reduced
simulation is not possible. We could fix them before the the set-up time of FPGA by 2 months. Through VPs, many
hardware prototype available. design faults were detected, which usually might be detected a
hardware prototype. The interconnect power consumption was
In SystemC-RTL co-simulation, the simulation speed was reduced by 42%. Overall, the proposed methodology helped
shackled by RTL simulator. However, in our case, it is decrease the HW resources as well as the development time,
endurable for verification (e.g., ~2.2 IOPS for normal SAS thus it raises SSD’s competitiveness in the world market.
commands, ~0.3 IOPS for normal NVMe commands in the
view of wall clock time). Table II shows the simulation time of REFERENCES
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