PSIT, Kanpur

Computer Organization and Architecture (BCS302)

Input-Output Organization
Unit - 5 (Part - II)
 Modes of Data Transfer with Direct Memory Access (DMA)
 Input Output Processor (IOP)
 Serial Communication with its modes
 Asynchronous data transfer (Strobe control & Handshaking)
 I/O Channel, Standard communication interfaces

Modes of Data Transfer

Data transfer between the central computer and I/O devices may be handled in one of three possible of modes:
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)
1. Programmed I/O
 Programmed I/O operations are the result of I/O instructions written in the computer program. Usually, the transfer is to
and from a CPU register and peripheral.
 In the programmed I/O method, the CPU stays in a program loop until the I/O unit indicates that it is ready for data transfer.
 This is a time-consuming process since it keeps the processor busy needlessly. It can be avoided by using an interrupt facility.
An example of data transfer from an I/O device through an interface into the CPU is shown in *MM Fig. 11-10.

 The device transfers bytes of data one at a time as they are available then the device places it in the I/O bus and enables its
data valid line. The interface accepts the byte into its data register and enables the data accepted line.
 The interface sets a bit in the status register as a "flag" bit (F). The device can now disable data valid line, but it will not
transfer another byte until data accepted line is disabled by the interface.

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A flowchart of the program that must be written for the CPU is shown in *MM Fig. 11-11. It is assumed that the device is sending
a sequence of bytes that must be stored in memory. The transfer of each byte requires three instructions:
i. Read the status register.
ii. Check the status of the flag bit and branch to step 1 if not set or to step 3 if set.
iii. Read the data register.

2. Interrupt-initiated I/O
 We can improve the efficiency of CPU by using an interrupt facility and special commands to inform the interface to issue an
interrupt request signal when the data are available from the device.
 In the meantime the CPU can proceed to execute another program. The interface meanwhile keeps monitoring the device.
 When the interface determines that the device is ready for data transfer, it generates an interrupt request to the CPU.
 Upon detecting the external interrupt signal, the CPU momentarily stops the task it is processing, branches to a
service program to process the I/O transfer, and then returns to the task it was originally performing.

3. Direct memory access (DMA)

 The transfer of data between a fast storage device is often limited by the speed of the CPU. Removing the CPU from the path
and letting the peripheral device manage the memory buses directly would improve the speed of transfer. This transfer
technique is called Direct Memory Access (DMA).
 During DMA transfer, the CPU is idle and has no control over the memory buses.
 A DMA controller takes over the buses to manage the transfer directly between the I/O device and memory.

Figure 11-16 CPU bus signals for DMA transfer

 The bus request (BR) input is used by the DMA controller to request the CPU to relinquish control of buses.
 When this input is active, the CPU terminates the execution of the current instruction and places the address bus, the
data bus and the read and write lines into a high-impedance state and activates the bus grant (BG) output to
acknowledge the external DMA controller.
 The DMA that originated the bus request can now take control of the buses to conduct memory transfers without
processor intervention.
 When the DMA terminates the transfer, it disables the bus request line. The CPU disables the bus grant, takes control
of the buses, and returns to its normal operation.

In DMA bus transfer, a block sequence consisting of a number of memory words is transferred in a continuous burst while the
DMA controller is master of the memory buses. E.g. transfer needed for magnetic disks.
Cycle stealing
An alternative technique called cycle stealing allows the DMA controller to transfer one data word at a time, after which it must
return control of the buses to the CPU. The CPU merely delays its operation for one memory cycle to allow the direct
memory I/O transfer to “steal” one memory cycle.

DMA Controller
Following *MM Fig 11-17 shows the block diagram of a typical DMA controller. The registers in the DMA are selected by the
CPU through the address bus by enabling the DS (DMA select) and RS (register select) inputs.
 When BG = 0, the CPU can communicate with the DMA registers through the data bus.
 When BG = 1, the CPU has relinquished the buses and the DMA can communicate directly with the memory by
specifying an address and activating the RD or WR control.
 In addition to the usual circuits of an interface unit, it needs an address register, a set of address lines (both for direct
communication with the memory) and a word count register (to specify number of words to be transferred).
 The control register specifies the mode of transfer.
 The DMA communicates with the external peripheral through the request and acknowledgement lines.
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Figure 11-17 Block diagram for DMA controller

 The CPU initializes the DMA by sending the following information through the data bus:
1. The starting address of the memory block for read or for write
2. The word count (number of words in the memory block)
3. Control to specify the mode of transfer (read or write)
4. A control to start the DMA transfer

DMA Transfer
 When the peripheral device sends a DMA request, the DMA controller activates the BR line, informing the CPU to
relinquish the buses.
 The CPU responds with its BG line, informing the DMA that its buses are disabled.

 Then DMA puts its current value of address register into the address bus.
 Since RD and WR lines are bidirectional, the direction of transfer depends on the status of the BG line i.e.
 When BG = 0, the RD and WR lines are input lines allowing the CPU to communicate with the internal DMA
registers.
 When BG = 1, the RD and WR lines are output lines from the DMA controller to the random access memory.
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 When the peripheral device receives a DMA acknowledge, it puts a word in the data bus (for write) or receives a word
from the data bus (for read).
 The peripheral unit can then communicate with memory through the data bus for direct transfer between the two units
while the CPU is momentarily disabled.

Input Output Processor (IOP)

 An Input Output Processor (IOP) may be classified as a processor with direct memory access capability that
communicates with I/O devices.
 The IOP is similar to a CPU except that it is designed to handle the details of I/O processing.
 Unlike the DMA controller that must be set up entirely by the CPU, the IOP can fetch and execute its own instructions to
facilitate I/O transfers.
The block diagram of a computer with the two processors is shown in *MM Fig. 11-19. In this, the memory unit occupies the
central position and can communicate with each processor by means of direct memory access.

 The CPU is responsible for processing data whereas IOP provides a path for transfer of data between various
peripheral devices and memory unit.
 In most computer systems, the CPU is the master while the IOP is a slave processor. The CPU is assigned the task of
initiating all operations, but I/O instructions are executed in the IOP.

 CPU instructions provide operations to start an I/O transfer and also to test I/O status conditions needed for making decisions
on various I/O activities. The IOP, in turn, typically asks for CPU attention by means of an interrupt.
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Data Transmission
 The transfer of data between two units may be done in parallel or serial.

 In parallel data transmission, each bit of the message has its own path and the total message is transmitted at the same
time. This means that an n-bit message must be transmitted through n separate conductor paths.

 In serial data transmission, each bit in the message is sent in sequence one at a time.

Serial Communication
 A data communication processor communicates with each terminal through a single pair of wires for transferring data and
control information. Transferring information from sender to receiver one bit at a time is known as serial communication.
 The incoming data word is stored in the buffer on the sender side then it is bit-wise taken and sent through a single
communication channel in a serial manner.
 On the receiver end, again there is a buffer to store the incoming bits and so on.
Advantage- Only single communication line required for transferring any number of bits of data word
Disadvantage- The speed of data transfer is decreased.

Figure- Serial Communication

There are three different modes of serial communication i.e.
a. Simplex
 This method is a unidirectional or one-way communication method i.e. Only one of two devices on a link can
transmit the data, the other can only receive.
 If a sender transmits, then the receiver can only receive the data.
 Examples- Radio, Television, etc.
b. Half Duplex
 In this method, each of the sender and receiver can transmit the data but not at the same time.
 When one is sending the data then the other can only receive and vice versa.
 Example- Walkie-talkie.
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c. Duplex
 In this, both the sender and receiver can transmit and receive the data simultaneously at the same time.
 This method is used when communication in both directions is required all the time.
 Example- Smartphone.

In order to work efficiently with serial devices, the clock is the primary source. The clock signal for each serial device is different
and it is categorized as synchronous transmission and asynchronous transmission.

Synchronous transmission
 In synchronous transmission, the sender and receiver share a common clock frequency and bits are transmitted
continuously at the rate dictated by the clock pulses.
 Data is sent in the form of blocks or frames. There is no gap present between data. It is more efficient and more reliable
than asynchronous transmission to transfer a large amount of data.
 Synchronization signals are transmitted periodically between the two units to keep their clocks in step with each other.

Asynchronous transmission
 In asynchronous transmission, binary information is sent only when it is available and the line remains idle when there
is no information to be transmitted.
 The technique (used in many interactive terminals) employs special bits that are inserted at both ends of the character code.
 With this technique, each character consists of three parts: a start bit, the character bits, and stop bits.
 The convention is that the transmitter rests at the 1-state when no characters are transmitted. The first bit, called the
start bit, is always a 0 and is used to indicate the beginning of a character. The last bit called the stop bit is always a 1.

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An example of this format is shown in the above Figure. A transmitted character can be detected by the receiver from knowledge
of the transmission rules as under:
1. When a character is not being sent, the line is kept in the 1-state.
2. The initiation of a character transmission is detected from the start bit, which is always 0.
3. The character bits always follow the start bit.
4. After the last bit of the character is transmitted, a stop bit is detected when the line returns to the 1-state for at
least one bit time.

As an illustration, consider the serial transmission of a terminal whose transfer rate is 10 characters per second. Each transmitted
character consists of a start bit, eight information bits, and two stop bits, for a total of 11 bits.
Baud Rate
The baud rate is defined as the rate at which serial information is transmitted and is equivalent to the data transfer in bits per
second. E.g. Ten characters per second with an 11-bit format, has a transfer rate of 110 baud.

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that control signals be transmitted between the
communicating units to indicate the time at which data is being transmitted. This can be done in one of the two ways-

1. Strobe Control
2. Handshaking

1. Strobe Control
The strobe control method of asynchronous data transfer employs a single control line to time each transfer. The strobe may be
activated by either the source or the destination unit.

*MM Figure 11-3(a) shows a source-initiated transfer.

As shown in the timing diagram of *MM Fig. 11-3(b), the source unit first places the data on the data bus. After a brief delay to
ensure that the data settle to a steady value, the source activates the strobe pulse. The information on the data bus and the
strobe signal remain in the active state for a sufficient time period to allow the destination unit to receive the data.

*MM Fig 11-4 shows a destination initiated transfer i.e. data transfer initiated by the destination unit.
In this case the destination unit activates the strobe pulse, informing the source to provide the data. The source unit responds by
placing the requested binary information on the data bus. The data must be valid and remain in the bus long enough for the
destination unit to accept it.
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The disadvantage of the strobe method is that the source unit that initiates the transfer has no way of knowing whether the
destination unit has actually received the data item that was placed in the bus. Similarly, a destination unit that initiates the
transfer has no way of knowing whether the source unit has actually placed the data on the bus.

2. Handshaking
The handshake method solves this problem by introducing a second control signal that provides a reply to the unit that initiates the
transfer. The basic principle of the two-wire handshaking method of data transfer is as follows:
i. Source initiated handshaking
ii. Destination initiated handshaking
Figure 11-5 shows the source initiated handshaking data transfer procedure when initiated by the source. The two handshaking
lines are data valid, which is generated by the source unit, and data accepted, generated by the destination unit. The timing
diagram shows the exchange of signals between the two units.

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Disadvantage: This scheme allows arbitrary delays from one state to the next and permits each unit to respond at its own data
transfer rate. The rate of transfer is determined by the slowest unit.

The destination-initiated transfer using handshaking lines is shown in *MM Fig. 11-6. Note that the name of the signal
generated by the destination unit has been changed to ready for data to reflect its new meaning.
The source unit in this case does not place data on the bus until after it receives the ready for data signal from the destination unit.
From there on, the handshaking procedure follows the same pattern as in the source-initiated case.

The handshaking scheme provides a high degree of flexibility and reliability because the successful completion of a data
transfer relies on active participation by both units. If one unit is faulty, the data transfer will not be completed.

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IBM 370 I/O Channel
 The I/O processor in the IBM 370 computer is called a channel.
A typical computer system configuration includes a number of channels with each channel attached to one or more I/O devices.

There are three types of channels: multiplexer, selector, and block-multiplexer.

 The multiplexer channel can be connected to a number of slow- and medium-speed devices and is capable of operating with
a number of I/O devices simultaneously.
 The selector channel is designed to handle one I/O operation at a time and is normally used to control one high-speed device.
 The block-multiplexer channel combines the features of both the multiplexer and selector channels. It provides a connection
to a number of high-speed devices, but all I/O transfers are conducted with an entire block of data as compared to a
multiplexer channel, which can transfer only one byte at a time.

NOTE: The CPU communicates directly with the channels through dedicated control lines and indirectly through reserved storage
areas in memory.

Standard Communication Interfaces

Communication interfaces are essential for communicating with various subsystems of the embedded system with external world.
They are of two types:
1. Onboard communication interfaces: A group of different communicating channels for interconnecting various
integrated circuits and other peripherals within the given embedded system is referred to as Onboard (i.e. Device or
Board level) communication interface.
E.g.
 I2C- stands for Inter-Integrated Circuit. It is a bus interface connection protocol incorporated into devices
for serial communication. It was originally designed by Philips Semiconductor in 1982.
 SPI- a serial peripheral interface (SPI) is an interface that enables the serial (one bit at a time) exchange of
data between two devices, one called a master and the other called a slave.
 UART- A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous
serial communication in which the data format and transmission speeds are configurable.
 1-Wire- is a voltage-based digital system that works with two contacts, data and ground, for half-duplex
bidirectional communication.
2. External communication interfaces: A group of different communicating channels which interconnects various
embedded systems with various external devices is referred to as external (i.e. product level) communication interface.
E.g.
 Wired or wireless media

 Bluetooth - (a short-range wireless technology standard that is used for exchanging data between fixed
and mobile devices over short distances)
 RS-232 - (standard communication protocol for connecting computers and their peripheral devices to
enable serial data exchange)
 RS422 - (a simplex multi-drop standard, which means only one driver and up to ten receivers can be
attached to a bus)
 USB - (Universal Serial Bus is an industry standard that establishes specifications for cables, connectors
and protocols for connection, communication and power supply between computers, peripherals and other
computers)
 Ethernet - (Ethernet is a family of wired computer networking technologies commonly used in LANs,
MANs and WANs. It was commercially introduced in 1980 and first standardized in 1983 as IEEE 802.3).

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