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 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Basic Electrical Properties of MOS and Bi CMOS circuits

ID-VDS Characteristics of MOS Transistor :

The graph below shows the ID Vs VDS characteristics of an n- MOS transistor for several values of
VGS .It is clear that there are two conduction states when the device is ON. The saturated state and
the non-saturated state. The saturated curve is the flat portion and defines the saturation region. For
Vgs < VDS + Vth, the nMOS device is conducting and I D is independent of VDS. For Vgs > VDS +
Vth, the transistor is in the non-saturation region and the curve is a half parabola. When the transistor
is OFF (Vgs < Vth), then ID is zero for any VDS value.

The boundary of the saturation/non-saturation bias states is a point seen for each curve in the graph as
the intersection of the straight line of the saturated region with the quadratic curve of the non-
saturated region. This intersection point occurs at the channel pinch off voltage called VDSAT. The
diamond symbol marks the pinch-off voltage VDSAT for each value of VGS. VDSAT is defined as
the minimum drain-source voltage that is required to keep the transistor in saturation for a given VGS
.In the non-saturated state, the drain current initially increases almost linearly from the origin before
bending in a parabolic response. Thus the name ohmic or linear for the non- saturated region.
The drain current in saturation is virtually independent of VDS and the transistor acts as a current
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

source. This is because there is no carrier inversion at the drain region of the channel. Carriers are
pulled into the high electric field of the drain/substrate pn junction and ejected out of the drain
terminal.

Drain-to-Source Current IDS Versus Voltage VDS Relationships :

The working of a MOS transistor is based on the principle that the use of a voltage on the gate induce
a charge in the channel between source and drain, which may then be caused to move from source to
drain under the influence of an electric field created by voltage Vds applied between drain and
source. Since the charge induced is dependent on the gate to source voltage Vgs then Ids is dependent
on both Vgs and Vds.
Let us consider the diagram below in which electrons will flow source to drain .So,the drain current
is given by
Charge induced in channel (Qc) Ids =-Isd = Electron transit time(τ) Length of the channel Where the
transit time is given by τsd = ------------------------------
Velocity (v)
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

But velocity v= µEds

Where µ =electron or hole mobility and Eds = Electric field also , Eds = Vds/L
so,v = µ.Vds/L and τds = L2 / µ.Vds

The typical values of µ at room temperature are given below.

Non-saturated Region :
Let us consider the Id vs Vd relationships in the non-saturated region .The charge induced in the
channel due to due to the voltage difference between the gate and the channel, Vgs (assuming
substrate connected to source). The voltage along the channel varies linearly with distance X from the
source due to the IR drop in the channel .In the non-saturated state the average value is Vds/2. Also
the effective gate voltage Vg = Vgs – Vt where Vt, is the threshold voltage needed to invert the
charge under the gate and establish the channel.
Hence the induced charge is Qc = Eg εins εoW. L
Where
Eg = average electric field gate to channel
εins = relative permittivity of insulation between gate and channel εo=permittivity
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Here D is the thickness of the oxide layer. Thus

So, by combining the above two equations ,we get

or the above equation can be written as

In the non-saturated or resistive region where Vds < Vgs – Vt and

Generally ,a constant β is defined as

So that ,the expression for drain –source current will become

The gate /channel capacitance is

 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Hence we can write another alternative form for the drain current as

Some time it is also convenient to use gate –capacitance per unit area ,Cg So,the drain current is

This is the relation between drain current and drain-source voltage in non-saturated region.
Saturated Region
Saturation begins when Vds = Vgs - V, since at this point the IR drop in the channel equals the
effective gate to channel voltage at the drain and we may assume that the current remains fairly
constant as Vds increases further. Thus

or we can also write that

or it can also be written as

or

The expressions derived above for Ids hold for both enhancement and depletion mode devices. Here
the threshold voltage for the nMOS depletion mode device (denoted as Vtd) is negative.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

MOS Transistor Threshold Voltage Vt :

The gate structure of a MOS transistor consists, of charges stored in the dielectric layers and in the
surface to surface interfaces as well as in the substrate itself. Switching an enhancement mode MOS
transistor from the off to the on state consists in applying sufficient gate voltage to neutralize these
charges and enable the underlying silicon to undergo an inversion due to the electric field from the
gate. Switching a depletion mode nMOS transistor from the on to the off state consists in applying
enough voltage to the gate to add to the stored charge and invert the 'n' implant region to 'p'.
The threshold voltage Vt may be expressed as:

where QD = the charge per unit area in the depletion layer below the oxide Qss = charge density at
Si: SiO2 interface
Co =Capacitance per unit area.
Φns = work function difference between gate and Si
ΦfN = Fermi level potential between inverted surface and bulk Si
For polynomial gate and silicon substrate, the value of Φns is negative but negligible and the
magnitude and sign of Vt are thus determined by balancing the other terms in the equation. To
evaluate the Vt the other terms are determined as below.

Body Effect :
Generally while studying the MOS transistors it is treated as a three terminal device. But, the body of
the transistor is also an implicit terminal which helps to understand the characteristics of the
transistor. Considering the body of the MOS transistor as a terminal is known as the body effect. The
potential difference between the source and the body (Vsb) affects the threshold
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

voltage of the transistor. In many situations, this Body Effect is relatively insignificant, so we can
(unless otherwise stated) ignore the Body Effect. But it is not always insignificant, in some cases it
can have a tremendous impact on MOSFET circuit performance.

Body effect - nMOS device

Increasing Vsb causes the channel to be depleted of charge carriers and thus the threshold voltage is

raised. Change in Vt is given by ΔVt = γ.(Vsb)1/2 where γ is a constant which depends on substrate
doping so that the more lightly doped the substrate, the smaller will be the body effect
The threshold voltage can be written as

Where Vt(0) is the threshold voltage for Vsd = 0

For n-MOS depletion mode transistors ,the body voltage values at different V DD voltages are given
below.
VSB = 0 V ; Vsd = -0.7VDD (= - 3.5 V for VDD =+5V ) VSB = 5 V ; Vsd = -0.6VDD (= - 3.0 V for
VDD =+5V )
nMOS INVERTER :
An inverter circuit is a very important circuit for producing a complete range of logic circuits. This is
needed for restoring logic levels, for Nand and Nor gates, and for sequential and memory circuits of
various forms .
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

A simple inverter circuit can be constructed using a transistor with source connected to ground and a
load resistor of connected from the drain to the positive supply rail VDD· The output is taken from
the drain and the input applied between gate and ground .
But, during the fabrication resistors are not conveniently produced on the silicon substrate and even
small values of resistors occupy excessively large areas .Hence some other form of load resistance is
used. A more convenient way to solve this problem is to use a depletion mode transistor as the load,
as shown in Fig. below.

The salient features of the n-MOS inverter are

 For the depletion mode transistor, the gate is connected to the source so it is always on .
 In this configuration the depletion mode device is called the pull-up (P.U) and the enhancement mode
device the pull-down (P.D) transistor.
 With no current drawn from the output, the currents Ids for both transistors must be equal.
nMOS Inverter transfer characteristic.
The transfer characteristic is drawn by taking Vds on x-axis and Ids on Y-axis for both enhancement
and depletion mode transistors. So,to obtain the inverter transfer characteristic for
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Vgs = 0 depletion mode characteristic curve is superimposed on the family of curves for the
enhancement mode device and from the graph it can be seen that , maximum voltage across the
enhancement mode device corresponds to minimum voltage across the depletion mode transistor.

From the graph it is clear that as Vin(=Vgs p.d. transistor) exceeds the Pulldown threshold voltage
current begins to flow. The output voltage Vout thus decreases and the subsequent increases in Vin
will cause the Pull down transistor to come out of saturation and become resistive.
CMOS Inverter:
The inverter is the very important part of all digital designs. Once its operation and properties are
clearly understood, Complex structures like NAND gates, adders, multipliers, and microprocessors
can also be easily done. The electrical behavior of these complex circuits can be almost completely
derived by extrapolating the results obtained for inverters. As shown in the diagram below the CMOS
transistor is designed using p-MOS and n-MOS transistors.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

In the inverter circuit ,if the input is high .the lower n-MOS device closes to discharge the capacitive
load .Similarly ,if the input is low,the top p-MOS device is turned on to charge the capacitive load
.At no time both the devices are on ,which prevents the DC current flowing from positive power
supply to ground. Qualitatively this circuit acts like the switching circuit, since the p-channel
transistor has exactly the opposite characteristics of the n-channel transistor. In the transition region
both transistors are saturated and the circuit operates with a large voltage gain. The C-MOS transfer
characteristic is shown in the below graph.
Considering the static conditions first, it may be Seen that in region 1 for which Vi,. = logic 0, we
have the p-transistor fully turned on while the n-transistor is fully turned off. Thus no current flows
through the inverter and the output is directly connected to VDD through the p-transistor.

Hence the output voltage is logic 1 . In region 5 , V in = logic 1 and the n-transistor is fully on while
the p-transistor is fully off. So, no current flows and logic 0 appears at the output.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

In region 2 the input voltage has increased to a level which just exceeds the threshold voltage of the
n-transistor. The n-transistor conducts and has a large voltage between source and drain; so it is in
saturation. The p-transistor is also conducting but with only a small voltage across it, it operates in
the unsaturated resistive region. A small current now flows through the inverter from VDD to VSS. If
we wish to analyze the behavior in this region, we equate the p-device resistive region current with
the n-device saturation current and thus obtain the voltage and current relationships.
Region 4 is similar to region 2 but with the roles of the p- and n-transistors reversed.However, the
current magnitudes in regions 2 and 4 are small and most of the energy consumed in switching from
one state to the other is due to the larger current which flows in region 3.
Region 3 is the region in which the inverter exhibits gain and in which both transistors are in
saturation.
The currents in each device must be the same ,since the transistors are in series. So,we can write that

Since both transistors are in saturation, they act as current sources so that the equivalent circuit in this
region is two current sources in series between V DD and Vss with the output voltage coming from
their common point. The region is inherently unstable in consequence and the changeover from one
logic level to the other is rapid.
Determination of Pull-up to Pull –Down Ratio (Zp.u}Zp.d.)for an nMOS Inverter driven by
another nMOS Inverter :
Let us consider the arrangement shown in Fig.(a). in which an inverter is driven from the output of
another similar inverter. Consider the depletion mode transistor for which Vgs = 0 under all
conditions, and also assume that in order to cascade inverters without degradation the condition
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Fig.(a).Inverter driven by another inverter.

For equal margins around the inverter threshold, we set Vinv = 0.5V DD · At this point both
transistors are in saturation and we can write that

where Wp.d , Lp.d , Wp.u. and Lp.u are the widths and lengths of the pull-down and pull-up
transistors respectively.
So,we can write that
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

The typical, values for Vt ,Vinv and Vtd are

Substituting these values in the above equation ,we get

Here

So,we get

This is the ratio for pull-up to pull down ratio for an inverter directly driven by another inverter.
Pull -Up to Pull-Down ratio for an nMOS Inverter driven through one or more Pass
Transistors
Let us consider an arrangement in which the input to inverter 2 comes from the output of inverter 1
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

but passes through one or more nMOS transistors as shown in Fig. below (These transistors are called
pass transistors).

The connection of pass transistors in series will degrade the logic 1 level / into inverter 2 so that the
output will not be a proper logic 0 level. The critical condition is , when point A is at 0 volts and B is
thus at VDD. but the voltage into inverter 2at point C is now reduced from VDD by the threshold
voltage of the series pass transistor. With all pass transistor gates connected to VDD there is a loss of
Vtp, however many are connected in series, since no static current flows through them and there can
be no voltage drop in the channels. Therefore, the input voltage to inverter 2 is
Vin2 = VDD- Vtp where Vtp = threshold voltage for a pass transistor.
Let us consider the inverter 1 shown in Fig.(a) with input = V DD· If the input is at VDD , then the
pull-down transistor T2 is conducting but with a low voltage across it; therefore, it is in its resistive
region represented by R1 in Fig.(a) below. Meanwhile, the pull up transistor T1 is in saturation and is
represented as a current source.
For the pull down transistor

Since Vds is small, Vds/2 can be neglected in the above expression.

 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

So,

Now, for depletion mode pull-up transistor in saturation with Vgs = 0

The product 1R1 = Vout1So,

Let us now consider the inverter 2 Fig.b .when input = VDD- Vtp.
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Whence,

If inverter 2 is to have the same output voltage under these conditions then V out1 = Vout2. That is

I1R1=I2R2 , therefore

Considering the typical values

Therefore
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits

From the above theory it is clear that, for an n-MOS transistor

(i). An inverter driven directly from the output of another should have a Zp.u/ Zpd. ratio of ≥
4/1.
(ii).An inverter driven through one or more pass transistors should have a Zp.u./Zp.d ratio of ≥8/1
ALTERMTIVE FORMS OF PULL –UP
Generally the inverter circuit will have a depletion mode pull-up transistor as its load. But there are
also other configurations .Let us consider four such arrangements.
(i).Load resistance RL : This arrangement consists of a load resistor as apull-up as shown in the
diagram below.But it is not widely used because of the large space requirements of resistors
produced in a silicon substrate.

nMOS depletion mode transistor pull-up : This arrangement consists of a depletion mode
transistor as pull-up. The arrangement and the transfer characteristic are shown below.In this type
of arrangement we observe
(a) Dissipation is high , since rail to rail current flows when Vin = logical 1.
(b) Switching of output from 1 to 0 begins when Vin exceeds Vt, of pull-down device.
Unit-2 VLSI Circuit Design Processes

MOS LAYERS
MOS design is aimed at turning a specification into masks for processing silicon to meet the
specification. We have seen that MOS circuits are formed on four basic layers
 N-diffusion
 P-diffusion
 Poly Si
 Metal
which are isolated from one another by thick or thin (thinox) silicon silicon dioxide insulating
layers. The thin oxide (thinox) mask region includes n-diffusion, p-diffusion, and transistor
channels. Polysilicon and thinox regions interact so that a transistor is formed where they cross
one another.
STICK DIAGRAMS

A stick diagram is a diagrammatic representation of a chip layout that helps to abstract a model
for design of full layout from traditional transistor schematic. Stick diagrams are used to convey
the layer information with the help of a color code.
“A stick diagram is a cartoon of a layout.”
The designer draws a freehand sketch of a layout, using colored lines to represent the various
process layers such as diffusion, metal and polysilicon. Where polysilicon crosses diffusion,
transistors are created and where metal wires join diffusion or polysilicon, contacts are formed.
For example, in the case of nMOS design,
 Green color is used for n-diffusion
 Red for polysilicon
 Blue for metal
 Yellow for implant, and black for contact areas.
Monochrome encoding is also used in stick diagrams to represent the layer information.

4
Unit-2 VLSI Circuit Design Processes

Stick Diagrams –NMOS Encoding

NMOS ENCODING

5
Unit-2 VLSI Circuit Design Processes

CMOS ENCODING

6
Unit-2 VLSI Circuit Design Processes

Stick Diagrams – Some Rules

Rule 1:

When two or more ‘sticks’ of the same type cross or touch each other that represents
electrical contact.

Rule 2:
When two or more “sticks” of different type cross or touch each other there is no electrical
contact. (If electrical contact is needed we have to show the connection explicitly)

7
Unit-2 VLSI Circuit Design Processes

Rule 3:

When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

Rule 4:

In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All PMOS must lie
on one side of the line and all NMOS will have to be on the other side.

8
Unit-2 VLSI Circuit Design Processes

nMOS Design Style :

To understand the design rules for nMOS design style , let us consider a single metal, single

polysilicon nMOS technology.

The layout of nMOS is based on the following important features.

 n-diffusion [n-diff.] and other thin oxide regions [thinox] (green) ;

 polysilicon 1 [poly.]-since there is only one polysilicon layer here (red);

 metal 1 [metal]-since we use only one metal layer here (blue);

 implant (yellow);

 contacts (black or brown [buried]).

A transistor is formed wherever poly. crosses n-diff. (red over green) and all diffusion wires

(interconnections) are n-type (green).When starting a layout, the first step normally taken is to

draw the metal (blue) VDD and GND rails in parallel allowing enough space between them for the

other circuit elements which will be required. Next, thinox (green) paths may be drawn between

the rails for inverters and inverter based logic as shown in Fig. below. Inverters and inverter-

based logic comprise a pull-up structure, usually a depletion mode transistor, connected from the

output point to VDD and a pull down structure of enhancement mode transistors suitably

interconnected between the output point and GND. This is illustrated in the Fig.(b). remembering

that poly. (red) crosses thinox (green)wherever transistors are required. One should consider the

implants (yellow) for depletion mode transistors and also consider the length to width (L:W)

ratio for each transistor. These ratios are important particularly in nMOS and nMOS- like

circuits.

9
Unit-2 VLSI Circuit Design Processes

1
Unit-2 VLSI Circuit Design Processes

CMOS Design Style:

The CMOS design rules are almost similar and extensions of n-MOS design rules except the
Implant (yellow) and the buried contact (brown). In CMOS design Yellow is used to identify p
transistors and wires, as depletion mode devices are not utilized. The two types of transistors 'n'
and 'p', are separated by the demarcation line (representing the p-well boundary) above which all
p-type devices are placed (transistors and wires (yellow). The n-devices (green) are consequently
placed below the demarcation line and are thus located in the p-well as shown in the diagram
below.

Diffusion paths must not cross the demarcation line and n-diffusion and p-diffusion wires must

not join. The 'n' and 'p' features are normally joined by metal where a connection is needed. Their

geometry will appear when the stick diagram is translated to a mask layout. However, one must not forget

to place crosses on VDD and Vss rails to represent the substrate and p-well connection respectively. The

design style is explained by taking the example the design of a single bit shift register. The design begins

with the drawing of the VDD and Vss rails in parallel and in metal and the creation of an (imaginary)

demarcation line in-between, as shown in Fig.below. The n-transistors are then placed below this line and

thus close to Vss, while p-transistors are placed above the line and below VDD In both cases, the

transistors are conveniently placed with their diffusion paths parallel to the rails (horizontal in the

diagram) as shown in Fig.(b). A similar approach can be taken with transistors in symbolic form.

1
Unit-2 VLSI Circuit Design Processes

Fig. CMOS stick layout design style (a,b,c,d)

The n- along with the p-transistors are interconnected to the rails using the metal and
connect as Shown in Fig.(d). It must be remembered that only metal and poly-silicon can cross
the demarcation line but with that restriction, wires can run-in diffusion also. Finally, the
remaining interconnections are made as appropriate and the control signals and data inputs are
added as shown in the Fig.(d).

1
Unit-2 VLSI Circuit Design Processes

Stick Diagrams:

1
Unit-2 VLSI Circuit Design Processes

Examples of Stick Diagrams

CMOS Inverter

14
Unit-2 VLSI Circuit Design Processes

Contd….

Fig. CMOS NAND gate

15
Unit-2 VLSI Circuit Design Processes

Design Rules and Layout

In VLSI design, as processes become more and more complex, need for the designer to
understand the intricacies of the fabrication process and interpret the relations between the
different photo masks is really troublesome. Therefore, a set of layout rules, also called design
rules, has been defined. They act as an interface or communication link between the circuit
designer and the process engineer during the manufacturing phase. The objective associated with
layout rules is to obtain a circuit with optimum yield (functional circuits versus non-functional
circuits) in as small as area possible without compromising reliability of the circuit. In addition,
Design rules can be conservative or aggressive, depending on whether yield or performance is
desired. Generally, they are a compromise between the two. Manufacturing processes have their
inherent limitations in accuracy. So the need of design rules arises due to manufacturing
problems like –
• Photo resist shrinkage, tearing.
• Variations in material deposition, temperature and oxide thickness.
• Impurities.
• Variations across a wafer.
These lead to various problems like :
• Transistor problems:
Variations in threshold voltage: This may occur due to variations in oxide thickness, ion-
implantation and poly layer. Changes in source/drain diffusion overlap. Variations in
substrate.
• Wiring problems:
Diffusion: There is variation in doping which results in variations in resistance,
capacitance. Poly, metal: Variations in height, width resulting in variations in resistance,
capacitance. Shorts and opens.
• Oxide problems:
Variations in height.
Lack of planarity.

• Via problems:
Via may not be cut all the way through.

16
Unit-2 VLSI Circuit Design Processes

Undersize via has too much resistance.

Via may be too large and create short.
To reduce these problems, the design rules specify to the designer certain geometric constraints
on the layout artwork so that the patterns on the processed wafers will preserve the topology and
geometry of the designs. This consists of minimum-width and minimum-spacing constraints and
requirements between objects on the same or different layers. Apart from following a definite set
of rules, design rules also come by experience.
Why we use design rules?
• Interface between designer and process engineer
• Historically, the process technology referred to the length of the silicon channel
between the source and drain terminals in field effect transistors.
• The sizes of other features are generally derived as a ratio of the channel length,
where some may be larger than the channel size and some smaller.
For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the
gate terminal may be only 50 nm.

17
Unit-2 VLSI Circuit Design Processes

Design rules define ranges for features

Examples:
• min. wire widths to avoid breaks
• min. spacing to avoid shorts
• minimum overlaps to ensure complete overlaps
– Measured in microns
– Required for resolution/tolerances of masks
Fabrication processes defined by minimum channel width
– Also minimum width of poly traces
– Defines “how fast” a fabrication process is
Types of Design Rules
The design rules primary address two issues:
1. The geometrical reproduction of features that can be reproduced by the maskmaking and
lithographical process, and
2. The interaction between different layers.
There are primarily two approaches in describing the design rules.
1. Linear scaling is possible only over a limited range of dimensions.
2. Scalable design rules are conservative .This results in over dimensioned and less dense
design.
3. This rule is not used in real life.
1. Scalable Design Rules (e.g. SCMOS, λ-based design rules):
In this approach, all rules are defined in terms of a single parameter λ. The rules are so chosen
that a design can be easily ported over a cross section of industrial process ,making the layout
portable .Scaling can be easily done by simply changing the value of.
The key disadvantages of this approach are:
2. Absolute Design Rules (e.g. μ-based design rules ) :
In this approach, the design rules are expressed in absolute dimensions (e.g. 0.75μm) and
therefore can exploit the features of a given process to a maximum degree. Here, scaling and
porting is more demanding, and has to be performed either manually or using CAD tools .Also,
these rules tend to be more complex especially for deep submicron.

18
Unit-2 VLSI Circuit Design Processes

The fundamental unity in the definition of a set of design rules is the minimum line width .It
stands for the minimum mask dimension that can be safely transferred to the semiconductor
material .Even for the same minimum dimension, design rules tend to differ from company to
company, and from process to process. Now, CAD tools allow designs to migrate between
compatible processes.

• Lambda-based (scalable CMOS) design rules define scalable rules based on λ

(which is half of the minimum channel length)
– classes of MOSIS SCMOS rules: SUBMICRON, DEEPSUBMICRON
• Stick diagram is a draft of real layout, it serves as an abstract view between the
schematic and layout.
• Circuit designer in general want tighter, smaller layouts for improved performance
and decreased silicon area.
• On the other hand, the process engineer wants design rules that result in a
controllable and reproducible process.
• Generally we find there has to be a compromise for a competitive circuit to be
produced at a reasonable cost.
• All widths, spacing, and distances are written in the form
• λ = 0.5 X minimum drawn transistor length
• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting outmask
• If design rules are obeyed, masks will produce working circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area to be contacted

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 Unit-2 VLSI Circuit Design Processes

DESIGN RULES FOR WIRES (nMOS and CMOS)

TRANSISTOR DESIGN RULES (nMOS, pMOS and CMOS)

20
Unit-2 VLSI Circuit Design Processes

21
Unit-2 VLSI Circuit Design Processes

22
Unit-2 VLSI Circuit Design Processes

CONTACT CUTS

When making contacts between poly-silicon and diffusion in nMOS circuits it should be
remembered that there are three possible approaches--poly. to metal then metal to diff., or
aburied contact poly. to diff. , or a butting contact (poly. to diff. using metal). Among the three
the latter two, the buried contact is the most widely used, because of advantage in space and a
reliable contact. At one time butting contacts were widely used , but now a days they are
superseded by buried contacts.
In CMOS designs, poly. to diff. contacts are always made via metal. A simple process is
followed for making connections between metal and either of the other two layers (as in Fig.a),
The 2λ. x 2λ. contact cut indicates an area in which the oxide is to be removed down to the
underlying polysilicon or diffusion surface. When deposition of the metal layer takes place the
metal is deposited through the contact cut areas onto the underlying area so that contact is made
between the layers.
The process is more complex for connecting diffusion to poly-silicon using the butting
contact approach (Fig.b), In effect, a 2λ. x 2λ contact cut is made down to each of the layers to
be joined. The layers are butted together in such a way that these two contact cuts become
contiguous. Since the poly-silicon and diffusion outlines overlap and thin oxide under poly
silicon acts as a mask in the diffusion process, the poly-silicon and diffusion layers are also
butted together. The contact between the two butting layers is then made by a metal overlay as
shown in the Fig.

23
Unit-2 VLSI Circuit Design Processes

Fig.(a) . n-MOS & C-MOS Contacts

Fig.(b). Contacts poly-silicon to diffusion

24
Unit-2 VLSI Circuit Design Processes

In buried contact basically, layers are joined over a 2λ. x 2λ. area with the buried
contact cut extending by 1λ, in all directions around the contact area except that the contact cut
extension is increased to 2λ. in diffusion paths leaving the contact area. This helps to avoid the
formation of unwanted transistors. So this buried contact approach is simpler when compared to
others. The, poly-silicon is deposited directly on the underlying crystalline wafer. When
diffusion takes place, impurities will diffuse into the poly-silicon as well as into the diffusion
region within the contact area. Thus a satisfactory connection between poly-silicon and diffusion
is ensured. Buried contacts can be smaller in area than their butting contact counterparts and,
since they use no metal layer, they are subject to fewer design rule restrictions in a layout.

Other design rules

 Double Metal MOS process Rules

 CMOS fabrication is much more complex than nMOS fabrication
 2 um Double metal, Double poly. CMOS/BiCMOS Rules
 1.2um Double Metal single poly.CMOS rules

CMOS Lambda-based Design Rules:

The CMOS fabrication process is more complex than nMOS fabrication. In a CMOS
process, there are nearly 100 actual set of industrial design rules. The additional rules are
concerned with those features unique to p-well CMOS, such as the p-well and p+ mask and the
special 'substrate contacts. The p-well rules are shown in the diagram below

In the diagram above each of the arrangements can be merged into single split contacts.

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Unit-2 VLSI Circuit Design Processes

From the above diagram it is also clear that split contacts may also be made with separate cuts.

The CMOS rules are designed based on the extensions of the Mead and Conway
concepts and also by excluding the butting and buried contacts the new rules for CMOS design
are formed. These rules for CMOS design are implemented in the above diagrams.

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Unit-2 VLSI Circuit Design Processes

µM CMOS Design rules

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Layout Diagrams for NMOS and CMOS Inverters and Gates

Basic Gate Design

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Layout & Stick Diagram of CMOS Inverter

2 input NAND gate

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2 input NOR gate

Scaling of MOS circuits

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