PLDs
PLDs
PROM
GAL
FPGA PLA
electronic devices
GAL20V8
GAL16V8 GAL22V10
Architecture:
16 total pins. Architecture: Architecture:
8 configurable outputs. 20 total pins. 22 total pins.
Programmable AND OR logic gates 8 configurable outputs. 10 configurable outputs.
matrix. Reprogrammability: Reprogrammability:
Reprogrammability: EEPROM technology. EEPROM reprogrammable,
EEPROM technology. ideal for iterative designs.
History
1948 Walter Brattain, John Bardeen and William Shockley
invented the Transistor; they received the Nobel Prize in
1956.
1959 Jack Kilby develops the C.I. I.T. laser.
1962 The TTLS and MOS laser appears.
1963 CMOS technology is created.
1964-1966 The PLD ler is born.
1969 The PLA ler is born.
History
1970 ROM Memory is born.
1971 Intel offers EPROM Technology.
1978 PAL is created in a project headed by John Birkner at
AMD.
1980 The first JEDEC format is proposed.
1981 FPLA is registered.
History
1982 The software race to support PLDS
begins. Thus, BEE, ABEL, CUPL, etc. are born.
ABEL, CUPL, etc.
1983 The GALs created by Lattice appear and
the PLAN software makes its appearance.
1995 Lattice announces new technologies for
the GAL, managing to work with voltages
from 3.3 volts and speeds of 286 Mhz.
GAL Device Architecture
Hardware Requirements