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2.(a) List and briefly define the main structural components of a

computer.
Answer

Main Structural Component of a Computer System

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The main elements associated with a computer system are as follows:

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1. Central Processing Unit (CPU)

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2. Main Memory

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3. Secondary Storage Devices
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4. Input and Output (I/O) Devices
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5. Busses
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1. Central Processing Unit (CPU): The CPU serves as the core processing unit of
a computer. It executes instructions fetched from memory by performing
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arithmetic, logical, control, and input/output operations. The CPU contains the
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Arithmetic Logic Unit (ALU), responsible for mathematical and logical

operations, and the Control Unit, managing the execution of instructions.
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2. Main Memory: Also known as RAM (Random Access Memory), main memory
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provides temporary storage for data and instructions that the CPU is acti actively
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using. It allows fast access to information but is volatile, meaning it loses its
content when the power is turned off. Main memory holds the operating
system, applications, and data being actively processed.
3. Secondary Storage Devices: These devices offer non-volatile, long-term
storage for data that needs to be retained even when the computer is
powered off. Examples include Hard Disk Drives (HDDs), Solid-State Drives
(SSDs), optical drives, USB flash drives, and external hard drives. They store the
operating system, applications, user files, and other data.
4. Input and Output (I/O) Devices: Input devices allow users to interact with
the computer system by providing data or commands. Examples include
keyboards, mice, touchscreens, scanners, and microphones. Output devices

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present processed information to users. Examples include monitors, printers,

speakers, and projectors.
5. Buses: Buses are communication channels that transfer data and signals
between different hardware components within the computer. They consist of
multiple lines or wires that carry address, data, and control signals. Buses
include the address bus (transfers memory addresses), data bus (transfers
data), and control bus (manages signals for coordinating actions between
components).

These main elements work together to facilitate the complete computing process.
The CPU processes instructions and data fetched from memory, which may be
temporarily stored in main memory or accessed from secondary storage devices.
Input devices enable users to provide
rovide instructions or data, and output devices

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present processed information. Buses enable communication and data transfer

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between these components, ensuring seamless operation of the computer system.

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(b) Discuss the design and logic of a microprogram seq
sequence.

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The address is used by a microprogram sequencer to decide which
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microinstruction has to be performed next. Microprogram sequencing is the
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name of the total procedure. The addresses needed to step through a

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control microprogram are created by a sequencer, also known as a

microsequencer.
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The control main job is to communicate with the memory,

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input/output device, and ALU on how to respond to or carry out a set of

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instructions. Processing is not done within the Control unit itself. It only
directs and manages the task. It serves as the supervisor,
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regulating all operations including retrieving instructions from main

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memory and putting them to use.

Micro Instructions Sequencer
Micro Instructions Sequencer is a combination of all hardware for selecting
the next micro-instruction address. The micro-instruction in control memory
contains a set of bits to initiate micro-operations in computer registers and
other bits to specify the method by which the address is obtained.

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Control Address Register(CAR) : Control address register
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receives the address from four different paths. For receiving the
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addresses from four different paths, Multiplexer is used.

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Multiplexer : Multiplexer is a combinational circuit which contains

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many data inputs and single data output depending on control or

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select inputs.
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Branching : Branching is achieved by specifying the branch

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address in one of the fields of the micro instruction. Conditional

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branching is obtained by using part of the micro-instruction to

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select a specific status bit in order to determine its condition.

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Mapping Logic : An external address is transferred into control

memory via a mapping logic circuit.
Incrementer : Incrementer increments the content of the control
address register by one, to select the next micro-instruction in
sequence.
Subroutine Register (SBR) : The return address for a subroutine is
stored in a special register called Subroutine Register whose value
is then used when the micro-program wishes to return from the
subroutine.
Control Memory : Control memory is a type of memory which
contains addressable storage registers. Data is temporarily stored

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in control memory. Control memory can be accessed quicker than

main memory.

2. Consider processor hypothetical 32-bit 22-bit micro-

having 32-bit instructions composed of two fields-the first
byte contains the opcode and the remainder the immediate
operand or an operand address.
(a) What in the maximum directly addressable bytes)?
memory capacity (in
(b) Discuss the impact on the system speed if the

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microprocessor bus has-

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(i) a 32-bit local address bus and a 16-bit
bit local data bus, or

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ii) a 16-bit local address bus and a 16-bit
bit local data bus.

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(c) How many bits its are needed for the program counter and
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the instruction register?
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a)
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There are 32-bit

bit microprocessors with 3232-bit instruction
From left side first 8 bits are opcode
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Then operand = 24 bits

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So that maximum directly addressable memory capacity = 2^24

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= 16777216
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(b)the
b)the impact on the system speed if the microprocessor bus has
1.) a 32-bit
bit local address bus and a 16-bit
16 local data bus:
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As per given local address bus is 32

32-bit,and we also have 32-bit instruction,
the entire address can be decoded once.
And given that data bus is 16-bits, to fetch 32-bit instruction we need two
cycles.

(2)
local address bus is 16-bit,and we have 32-bit instruction, sp that to fetch
the instruction it takes two cycles.
Local data bus also 16-but, again it takes two cycles.
Totally 4 cycles.

(c) No.of operands = 24 bits

Since operands are 24 bits, program counter needs atlease 24 bits.
Instruction register stores present instruction, hence it needs 32-bits

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4. (a) A set-associative cache has a block size of four 16-bit

words and a set size of 2. The cache can accommodate a total
of 4096 words. The main memory size that is cacheable is 64K
32 bits. Design the cache structure and show how the
processor's addresses are interpreted.

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(B)Explain two techniques for enhancing the performance of

computers with multiple execution pipelines.
1. Superscalar Execution:
Definition: Superscalar architecture involves having multiple execution units
within the CPU that can execute multiple instructions per clock cycle. This
architecture identifies independent instructions within a program and
executes them simultaneously, taking advantage of available execution units.
Instruction Level Parallelism (ILP): Superscalar processors analyze
instructions to find independent operations that can be executed
concurrently. This requires sophisticated hardware to detect

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dependencies and hazards between instructions to ensure correct

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execution.

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Dynamic Scheduling: Hardware-based based techniques like out-of-order
out

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execution and instruction reordering are used to optimize execution.

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Instructions are dynamically scheduled for execution based on available
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resources, dependency resolution, and other factors. This helps in
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mitigating
ng pipeline stalls caused by dependencies.
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Issue Width: The number of instructions that can be issued

simultaneously is referred to as the issue width. Superscalar processors
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typically have varying degrees of issue width, allowing multiple

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instructions to execute in parallel, further enhancing performance.

2. Simultaneous Multithreading (SMT):
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Definition: SMT, also known as Hyper

Hyper-Threading in Intel processors, allows
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multiple threads from the same or different processes to execute concurrently

on a single CPU core. It improves performance by utilizing idle CPU resources.
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Thread Level Parallelism (TLP): SMT takes advantage of unused CPU

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resources during the execution of a single thread to simultaneously

execute instructions from another thread. This allows the CPU to
maintain a higher level of utilization, increasing overall throughput.
Resource Sharing: In SMT, resources like execution units, caches, and
pipelines are shared between threads. This sharing enables the
processor to handle multiple threads efficiently by interleaving their
instructions and utilizing otherwise idle resources.
Improved Throughput: SMT enhances performance by maximizing
CPU utilization. By allowing multiple threads to execute simultaneously
on a single core, it improves overall throughput, especially in scenarios
where there might be idle execution units during the execution of a
single thread.

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Both superscalar execution and simultaneous multithreading focus on leveraging

parallelism to enhance performance in modern processors. They achieve this by
either executing multiple instructions from a single thread concurrently (superscalar
execution) or by allowing multiple threads to run simultaneously on a single core
(simultaneous multithreading), aiming to make better use of available hardware
resources and improving overall throughput.

5. (a) Calculate (72530-13250) using ten's

complement arithmetic. Assume rules similar to
those for two's complement arithmetic.

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(B) List and briefly explain five important

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instruction set design issues.

1. Operand Addressing Modes:
Operand addressing modes determine how the CPU accesses operands (data)
for instructions. Different modes include:
Register Mode: Operands are in CPU registers, enabling fast access.
Immediate Mode: Operand data is part of the instruction itself.
Direct Mode: Operands are directly referenced by memory addresses.
Indirect Mode: Memory address of the operand is stored in a register
or memory location.
2. Instruction Formats:

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Instruction formats define the structure of machine instructions, including

opcode (operation code), operand addresses, and other necessary fields.
Common formats include:
Fixed-Length: All instructions have the same length, simplifying
decoding but potentially wasting space.
Variable-Length: Instructions vary in length, allowing for more
compact code but making decoding more complex.
3. Types and Sizes of Operands:
Instruction sets support various data types (integers, floating-point numbers,
characters) and sizes (8-bit, 16-bit, 32-bit, etc.). Design decisions involve
defining supported data types, their sizes, and operations that can be
performed on them.
4. Instruction Set Completeness and Orthogonality:

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Completeness refers to having a sufficient range of instructions to perform

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various operations. Orthogonality means that operations are defined

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consistently across all instruction types and that each instruction perfo
performs a

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single, well-defined operation.

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5. Instruction Pipelining and Parallelism: er
Instruction set design impacts the potential for instruction
instruction-level parallelism
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and pipelining. Features like instruction reordering, multiple execution units,
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and support for concurrent

current operations influence how effectively instructions
can be executed in parallel.
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Each of these design issues significantly impacts the efficiency, performance, and
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usability of an instruction set architecture. Design choices aim to balance complexity

complexity,
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ease of programming, hardware efficiency, and performance to create a versatile and

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effective instruction set for a given CPU architecture.

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6. The x86 architecture includes an instruc

instruc- tion called decimal adjust after addition (DAA).
DAA performs the following sequence of instructions:
if((AL AND OFH)>9) OR (AF = 1) then AL + 6
AF1;
else
A F leftarrow0 ;
endif; if (AL > 9FH) OR (CF = 1) then AL leftarrow AL + 60H ;
C F leftarrow1 ;
elsed prac

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C F leftarrow O bebige dredi uot lo

endif. 2010
"H" indicates hexadecimal. AL is an 8-bit register that holds the result of addition of two
unsigned 8-bit integers. AF is a flag set if there is a carry from bit 3 to bit 4 in the result of an
addition. CF is a flag set if there Es a carry from bit 7 to bit 8. Explain the Function performed
by the DAA instruction.

The DAA instruction is used to adjust the sum of two packed BCD values
by creating a packed BCD result. The DAA instruction is used after an ADD
instruction that performs binary addition of two 2-digit packed BCD values
and stores the result in the AL register. The result of AL register is then
adjusted by the DAA instruction to get a 2-digit
digit packed BCD result.

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Based on the result of ADD instruction stored in the AL register DAA

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instruction adjusts the result.

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7. A non-pipelined processor has a clock rate of 2.5 GHz and an average

CPI of 4. An upgrade to the processor introduces a five-stage pipeline.
However, due to internal pipeline delays, such as latch delay, the clock
rate of the new processor has to be reduced to 2 GHz.

What is the speedup achieved for a typical program?

What is the MIPS rate for each processor?

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8.(a)
(a) Briefly explain the two basic approaches used to minimize register
register-
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memory operations
rations on RISC machines.
Compiler technology has also become more sophisticated, so that the
RISC use of RAM and emphasis on software has become ideal.

It is recognized that the wider the semantic gap, the

larger the number of undesirable consequences.
These include
(a) execution inefficiency,
(b) excessive machine program size, and
(c) increased compiler complexity.
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conventional response of computer architects has been

to add layers of complexity to newer architectures.
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instructions together with increasing the number of
addressing modes.

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ion
Set Computers (CISCs).
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instruction set has a number of disadvantages.
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an increased size of the control unit, and increased logicc

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delays.

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RISCs Design Principles
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statements), rather than complex operations, ar
are
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substantial and should be optimized.

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careful attention should be paid to the sequenci

sequencing of
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instructions. This is particularly true when it is know

known
that pipelining is indispensable to use
use.
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operations and therefore a mechanism should b be

devised to make the communication of parameter
parameters
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among g the calling and the called procedures cause theth

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least number of instructions to execute

execute.
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for storing and accessing local scalar variables.

8(B) A computer has 16 registers, an ALU with 32 operations and a

show with 8 operations, all connected to a common bus system.
i) Formulate a control word for a micro-operation.
ii) Show the bits of the control word that specify the micro-operation R4
< R5 + R6.

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9. Let a be the percentage of a program code that can be executed

simultaneously by n processors in a computer system. Assume that the
remaining code must be executed sequentially by a single processor. Each
processor has an execution rate of xMIPS.

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(a) Derive an expression for the effective MIPS rate when using the system
for exclusive execution of this program, in terms of n, a and x.
(b) If n= 16 and x=4 MIPS, determine the value of that will yield a system
performance of 40 MIPS.

Given data:

Given the software program execution as follows:

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x MIPS (Million Instructions per Second)

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ty

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