BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.

2006] June 30, 2007 at 13:42 589 (1)

Sec. 11.10 Chapter Summary 589

 If the two poles of a circuit are far from each other, the “dominant-pole approximation” can
be made to find a simple expression for each pole frequency.
 The CB and CG stages do not suffer from Miller effect and achieve a higher speed than
CE/CS stages, but their lower input impedance limits their applicability.
 Emitter and source followers provide a wide bandwidth. Their output impedance, however,
can be inductive, causing instability in some cases.
 To benefit from the higher input impedance of CE/CS stages but reduce the Miller effect, a
cascode stage can be used.
 The differential frequency response of differential pairs is similar to that of CE/CS stages.

Problems

1. In the amplifier of Fig. 11.60, RD = 1 k and CL = 1 pF. Neglecting channel-length

VDD

RD
Vout
V in M1 CL

Figure 11.60

modulation and other capacitances, determine the frequency at which the gain falls by 10%
( 1 dB).
2. In the circuit of Fig. 11.61, we wish to achieve a ,3-dB bandwidth of 1 GHz with a load
VCC

R1
Vout
V in Q1 CL

Figure 11.61

capacitance of 2 pF. What is the maximum (low-frequency) gain that can be achieved with
a power dissipation of 2 mW? Assume VCC = 2:5 V and neglect the Early effect and other
capacitances.
3. Determine the ,3-dB bandwidth of the circuits shown in Fig. 11.62. Assume VA = 1 but
 > 0. Neglect other capacitances.
4. Construct the Bode plot of jVout =Vin j for the stages depicted in Fig. 11.62.
5. A circuit contains two coincident (i.e., equal) poles at !p1 . Construct the Bode plot of
jVout =Vin j.
6. An amplifier exhibits two poles at 100 MHz and 10 GHz and a zero at 1 GHz. Construct the
Bode plot of jVout =Vin j.
7. An ideal integrator contains a pole at the origin, i.e., !p = 0. Construct the Bode plot of
jVout =Vin j. What is the gain of the circuit at arbitrarily low frequencies?
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590 Chap. 11 Frequency Response

VCC VCC
VDD VDD
Q2 Q2 Vb M2 V in M1
RB
Vout Vout Vout Vout
V in Q1 CL V in Q1 CL V in M1 CL M2 CL

(a) (b) (c) (d)

Figure 11.62

8. An ideal differentiator provides a zero at the origin, i.e., !z = 0. Construct the Bode plot of
jVout =Vin j. What is the gain of the circuit at arbitrarily high frequencies?
9. Figure 11.63 illustrates a cascade of two identical CS stages. Neglecting channel-length mod-
VDD

RD RD
X
Vout
V in M1 CL M2 CL

Figure 11.63

ulation and other capacitances, construct the Bode plot of jVout =Vin j. Note that Vout =Vin =
(VX =Vin )(Vout =VX ).
10. In Problem 9, derive the transfer function of the circuit, substitute s = j! , and obtain an
expression for jVout =Vin j. Determine the ,3-dB bandwidth of the circuit.
11. Consider the circuit shown in Fig. 11.64. Derive the transfer function assuming  > 0 but

VDD

Vout
V in M1 CL

Figure 11.64

neglecting other capacitances. Explain why the circuit operates as an ideal integrator if  ! 0.
12. Due to a manufacturing error, a parasitic resistance Rp has appeared in series with the source
of M1 in Fig. 11.65. Assuming  = 0 and neglecting other capacitances, determine the input
and output poles of the circuit.
13. Repeat Problem 12 for the circuit shown in Fig. 11.66.
14. Repeat Problem 12 for the CS stage depicted in Fig. 11.67.
15. Derive a relationship for the figure of merit defined by Eq. (11.8) for a CS stage. Consider
only the load capacitance.
16. Apply Miller’s theorem to resistor RF in Fig. 11.68 and estimate the voltage gain of the
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Sec. 11.10 Chapter Summary 591

VDD
RD
Vout
Vb CL
RP
RS
V in
C in

Figure 11.65

VDD
RD
Vout

RP CL
Vb
RS
V in
C in

Figure 11.66

VDD

RD
Vout
RS
V in M1 CL
C in
RP

Figure 11.67

circuit. Assume VA = 1 and RF is large enough to allow the approximation vout =vX =
,gmRC .
17. Repeat Problem 16 for the source follower in Fig. 11.69. Assume  = 0 and RF is large
enough to allow the approximation vout =vX = RL =(RL + gm ,1 ) .
18. Consider the common-base stage illustrated in Fig. 11.70, where the output resistance of Q1
is drawn explicitly. Utilize Miller’s theorem to estimate the gain. Assume rO is large enough
to allow the approximation vout =vX = gm RC .
19. Using Miller’s theorem, estimate the input capacitance of the circuit depicted in Fig. 11.71.
Assume  > 0 but neglect other capacitances. What happens if  ! 0?
20. Repeat Problem 19 for the source follower shown in Fig. 11.72.
21. Using Miller’s theorem, explain how the common-base stage illustrated in Fig. 11.73 provides
a negative input capacitance. Assume VA = 1 and neglect other capacitances.
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592 Chap. 11 Frequency Response

VCC
RC
RF
Vout
RB
V in Q1
X

Figure 11.68

VDD
RS X
V in M1
Vout
RF
RL

Figure 11.69

VCC
RC

Vout

rO Vb
Q1
V in
RB X

Figure 11.70

VDD

CF

M1

C in

Figure 11.71

22. Use Miller’s theorem to estimate the input and output poles of the circuit shown in Fig. 11.74.
Assume VA = 1 and neglect other capacitances.
23. Repeat Problem 22 for the circuit in Fig. 11.75.
24. For the bipolar circuits depicted in Fig. 11.76, identify all of the transistor capacitances and
determine which ones are in parallel and which ones are grounded on both ends.
25. For the MOS circuits shown in Fig. 11.77, identify all of the transistor capacitances and de-
termine which ones are in parallel and which ones are grounded on both ends.
26. In arriving at Eq. (11.49) for the fT of transistors, we neglected C and CGD . Repeat the
derivation without this approximation.
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 593 (1)

Sec. 11.10 Chapter Summary 593

VDD

M1
CF
C in

Figure 11.72

VCC
RC

C1 Vb
Q1

C in

Figure 11.73

VCC
RC
CF
Vout
RB
V in Q1

Figure 11.74

VCC
RC
Q2
RB
V in Q1

Vout
CF

Figure 11.75

27. It can be shown that, if the minority carriers injected by the emitter into the base take F
seconds to cross the base region, then Cb = gm F .
(a) Writing C = Cb + Cje , assuming that Cje is independent of the bias current, and using
Eq. (11.49), derive an expression for the fT of bipolar transistors in terms of the collector bias
current.
(b) Sketch fT as a function of IC .
28. It can be shown that CGS  (2=3)WLCox for a MOSFET operating in saturation. Using Eq.
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 594 (1)

594 Chap. 11 Frequency Response

VCC
I1
VCC VCC
Vout
VCC
Q2 Q2 V b1
RB Q1
Vout Vout Q3 V b3

V in Q1 CL V in Q1 CL V in Q2

(a) (b) (c)

Figure 11.76

VDD
VDD VDD RE
Vb M2 V in M2 V in M2
Vout
Vout Vout
M1 V b1
V in M1 Vb M1

RS
(a) (b) (c)

Figure 11.77

(11.49), prove that

2fT = 23 Ln2 (VGS , VTH ): (11.180)

Note that fT increases with the overdrive voltage.

29. Having solved Problem 28 successfully, a student attempts a different substitution for gm :
2ID =(VGS , VTH ), arriving at
2ID
2fT = 32 WLC 1 :
ox VGS , VTH
(11.181)

This result suggests that fT decreases as the overdrive voltage increases! Explain this apparent
discrepancy between Eqs. (11.180) and (11.181).
30. Using Eq. (11.49) and the results of Problems 28 and 29, plot the fT of a MOSFET (a) as a
function of W for a constant ID , (b) as a function of ID for a constant W . Assume L remains
constant in both cases.
31. Using Eq. (11.49) and the results of Problems 28 and 29, plot the fT of a MOSFET (a) as a
function of VGS , VTH for a constant ID , (b) as a function of ID for a constant VGS , VTH .
Assume L remains constant in both cases.
32. Using Eq. (11.49) and the results of Problems 28 and 29, plot the fT of a MOSFET (a) as a
function of W for a constant VGS , VTH , (b) as a function of VGS , VTH for a constant W .
Assume L remains constant in both cases.
33. In order to lower channel-length modulation in a MOSFET, we double the device length. (a)
How should the device width be adjusted to maintain the same overdrive voltage and the same
drain current? (b) How do these changes affect the fT of the transistor?
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Sec. 11.10 Chapter Summary 595

34. We wish to halve the overdrive voltage of a transistor so as to provide a greater voltage head-
room in a circuit. Determine the change in the fT if (a) ID is constant and W is increased, or
(b) W is constant and ID is decreased. Assume L is constant.
35. Using Miller’s theorem, determine the input and output poles of the CE and CS stages de-
picted in Fig. 11.29(a) while including the output impedance of the transistors.
36. The common-emitter stage of Fig. 11.78 employs a current-source load to achieve a high gain

VCC

Vout
RS
V in Q1

Figure 11.78

(at low frequencies). Assuming VA < 1 and using Miller’s theorem, determine the input and
output poles and hence the transfer function of the circuit.
37. Repeat Problem 36 for the stage shown in Fig. 11.79.

VCC

Vb Q2
Vout
RS
V in Q1

Figure 11.79

38. Assuming  > 0 and using Miller’s theorem, determine the input and output poles of the
stages depicted in Fig. 11.80.
VDD VDD VDD
RS
M2 M2 V in M2
Vout Vout Vout
RS RS
V in M1 V in M1 Vb M1

(a) (b) (c)

Figure 11.80

39. In the CS stage of Fig. 11.29(a), RS = 200 , RD = 1 k , ID1 = 1 mA, CGS = 50 fF,
CGD = 10 fF, CDB = 15 fF, and VGS , VTH = 200 mV. Determine the poles of the circuit
using (a) Miller’s approximation, and (b) the transfer function given by Eq. (11.70). Compare
the results.
40. Consider the amplifier shown in Fig. 11.81, where VA = 1. Determine the poles of the cir-
cuit using (a) Miller’s approximation, and (b) the transfer function expressed by Eq. (11.70).
Compare the results.
41. Repeat Problem 40 but use the dominant-pole approximation. How do the results compare?
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596 Chap. 11 Frequency Response

VCC

Vout
RS
V in Q1

Figure 11.81

42. The circuit depicted in Fig. 11.82 is called an “active inductor.” Neglecting other capacitances

R1
Z in
M1
C1

Figure 11.82

and assuming  = 0, compute Zin . Use Bode’s rule to plot jZin j as a function of frequency
and explain why it exhibits inductive behavior.
43. Determine the input and output impedances of the stage depicted in Fig. 11.83 without using
Miller’s theorem. Assume VA = 1.
VCC

Q1
Z out
Z in

Figure 11.83

44. Compute the transfer function of the circuit shown in Fig. 11.84 without using Miller’s theo-

VDD

M2
RS
V in Vout

M1

Figure 11.84

rem. Assume  > 0.

45. Calculate the input impedance of the stage illustrated in Fig. 11.85 without using Miller’s
theorem. Assume  = 0.
46. Determine the transfer function of the circuits shown in Fig. 11.86. Assume  = 0 for M1 .
47. Consider the source follower shown in Fig. 11.87, where the current source is mistakenly
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 597 (1)

Sec. 11.10 Chapter Summary 597

VDD

M2
Vout

M1
Z in

Figure 11.85

VDD VDD VDD

M2 Vb M2
Vout
Vout Vout

M1 Vb M1 Vb M1 Vb M2
RS RS RS
V in V in V in

(a) (b) (c)

Figure 11.86

VDD

M1

C in
M2

Figure 11.87

replaced with a diode-connected device. Taking into account only CGS 1 , compute the input
capacitance of the circuit. Assume  6= 0.
48. Determine the output impedance of the emitter follower depicted in Fig. 11.88, including C .
Sketch jZout j as a function of frequency. Assume VA = 1.

VCC
RB
V in Q1

Z out

Figure 11.88

49. In the cascode of Fig. 11.89, Q3 serves as a constant current source, providing 75% of the
bias current of Q1 . Assuming VA = 1 and using Miller’s theorem, determine the poles of
the circuit. Is Miller’s effect more or less significant here than in the standard cascode topology
of Fig. 11.48(a)?
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598 Chap. 11 Frequency Response

VCC

V b2 RC
Q3
Vout
V b1 Q2

V in Q1
RB

Figure 11.89

50. Due to manufacturing error, a parasitic resistor Rp has appeared in the cascode stage of Fig.
11.90. Assuming  = 0 and using Miller’s theorem, determine the poles of the circuit.
VDD
RD
Vout
Vb M2

RS
V in M1 RP

Figure 11.90

51. In analogy with the circuit of Fig. 11.89, a student constructs the stage depicted in Fig. 11.91
but mistakenly uses an NMOS device for M3 . Assuming  V= 0 and using Miller’s theorem,
DD
V b2 M3 RD
Vout
V b1 M2

V in M1
RG

Figure 11.91

compute the poles of the circuit.

Design Problems
52. Using the results obtained in Problems 9 and 10, design the two-stage amplifier of Fig. 11.63
for a total voltage gain of 20 and a ,3-db bandwidth of 1 GHz. Assume each stage carries a
bias current of 1 mA, CL = 50 fF, and n Cox = 100 A=V .
2

53. We wish to design the CE stage of Fig. 11.92 for an input pole at 500 MHz and an output pole
VCC
RC

RB Vout
V in Q1

Figure 11.92
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Sec. 11.10 Chapter Summary 599

at 2 GHz. Assuming IC = 1 mA, C = 20 fF, C = 5 fF, CCS = 10 fF, and VA = 1, and

using Miller’s theorem, determine the values of RB and RC such that the (low-frequency)
voltage gain is maximized. You may need to use iteration.
54. Repeat Problem 53 with the additional assumption that the circuit must drive a load capaci-
tance of 20 fF.
55. We wish to design the common-base stage of Fig. 11.93 for a ,3-dB bandwidth of 10 GHz.
VCC
RC

Vout
Vb
RS Q1
V in

Figure 11.93

Assume IC = 1 mA, VA = 1, RS = 50 , C = 20 fF, C = 5 fF, and CCS = 20 fF.

Determine the maximum allowable value of RC and hence the maximum achievable gain.
(Note that the input and output poles may affect the bandwidth.)
56. The emitter follower of Fig. 11.94 must be designed for an input capacitance of less than 50
VCC

V in Q1
Vout

RL

Figure 11.94

fF. If C = 10 fF, C = 100 fF, VA = 1, and IC = 1 mA, what is the minimum tolerable
value of RL ?
57. An NMOS source follower must drive a load resistance of 100 with a voltage gain of 0.8.
If ID = 1 mA, n Cox = 100 A=V , Cox = 12 fF/m2 , and L = 0:18 m, what is the
2

minimum input capacitance that can be achieved? Assume  = 0, CGD  0, CSB  0, and
CGS = (2=3)WLCox.
58. We wish to design the MOS cascode of Fig. 11.95 for an input pole of 5 GHz and an output
VDD
RD
Vout
Vb M2

RG
V in M1

Figure 11.95

pole of 10 GHz. Assume M1 and M2 are identical, ID = 0:5 mA, CGS = (2=3)WLCox,
Cox = 12 fF/m2 , n Cox = 100 A=V2 ,  = 0, L = 0:18 m, and CGD = C0 W , where
C0 = 0:2 fF=m denotes the gate-drain capacitance per unit width. Determine the maximum
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600 Chap. 11 Frequency Response

allowable values of RG , RD , and the voltage gain. Use Miller’s approximation for CGD1 .
Assume an overdrive voltage of 200 mV for each transistor.
59. Repeat Problem 58 if W2 = 4W1 so as to reduce the Miller multiplication of CGD1 .

SPICE Problems
In the following problems, use the MOS device models given in the Appendix A. For bipolar
transistors, assume IS;npn = 5  10,16 A, npn = 100, VA;npn = 5 V, IS;pnp = 8  10,16
A, pnp = 50, VA;pnp = 3:5 V. Also, SPICE models the effect of charge storage in the base
by a parameter called F = Cb =gm . Assume F (tf ) = 20 ps.
60. In the two-stage amplifier shown in Fig. 11.96, W=L = 10 m=0:18 m for M1 -M4 .
VDD = 1.8 V

M2
M3
Vout
V in M1
M4

Figure 11.96

(a) Select the input dc level to obtain an output dc level of 0.9 V.

(b) Plot the frequency response and compute the low-frequency gain and the ,3-dB band-
width.
(c) Repeat (a) and (b) for W = 20 m and compare the results.
61. The circuit of Fig. 11.97 must drive a load capacitance of 100 fF.
VCC = 2.5 V
1 kΩ 1 kΩ
Vout
5 kΩ
V in Q1 Q2

Figure 11.97

(a) Select the input dc level to obtain an output dc level of 1.2 V.

(b) Plot the frequency response and compute the low-frequency gain and the ,3-dB band-
width.
62. The self-biased stage depicted in Fig. 11.98 must drive a load capacitance of 50 fF with
a maximum gain-bandwidth product (= midband gain  unity-gain bandwidth). Assuming
R1 = 500 and L1 = 0:18 m, determine W1 , RF , and RD .
VDD = 1.8 V
RD

RF
100 pF R 1 Vout
V in M1 CL

Figure 11.98

63. Repeat Problem 62 for the circuit shown in Fig. 11.99. (Determine RF and RC .)
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Sec. 11.10 Chapter Summary 601

VCC = 2.5 V
RC
Q1
100 pF R 1
Vout
V in Q 1 1 mA
CL

RF

Figure 11.99

64. The two-stage amplifier shown in Fig. 11.100 must achieve maximum gain-bandwidth prod-
uct while driving CL = 50 fF. Assuming M1 -M4 have a width of W and a length of 0.18 m,
determine RF and W .
VDD = 1.8 V

M2 M4
1 kΩ RF
V in Vout
1 pF
M1 M3

Figure 11.100