Computer architecture laboratory(pcc-cs492)

MAULANA ABUL KALAM AZAD UNIVERSITY OF

TECHNOLOGY, WEST BENGAL

Hooghly Engineering & Technology College

Vivekananda Road, Pipulpati, Hooghly-712103

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Architecture Laboratory

(PCC-CS492)

Name: DIGDORSHEE GHOSAL

University Registration No: 201760100110042
University Roll No: 17600120036
Year: 2nd, Semester: 4th
Class roll-38
VISION AND MISSION OF THE CSE DEPARTMENT
Vision
Attainment of excellence as a computer engineer so as to prove themselves as outstanding
professional with complete expertise and knowledge in Computer Science & Engineering and its
applications so that they may prove a valuable resource for industry and society at large, maintaining
all moral and ethical values.

Mission
To excel in professional carrier and higher education by accruing applied knowledge in
Mathematics, Computation, Basic Principles of Science Engineering with capable
communication.
To create a strong teaching and research environment through excellent Computer Science &
Engineering education.
Computation, Basic Principles of Science Engineering with capable communication.
To analyze real life problems and projects in developing economically feasible and socially
acceptable solution

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Computer architecture laboratory(pcc-cs492)

Decoder
The combinational circuit that change the binary information into 2N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output lines define
the 2N-bit code for the binary information. In simple words, the Decoder performs the reverse
operation of the Encoder. At a time, only one input line is activated for simplicity. The produced 2N-
bit output code is equivalent to the binary information.

There are various types of decoders which are as follows:

2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and A1 and E and four outputs, i.e.,
Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 2 to 4 line decoder are given below.
Block Diagram:

Truth Table:

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The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
Logical circuit of the above expressions is given below:

3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there is a
total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2. This
circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these
four outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are given
below.

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Computer architecture laboratory(pcc-cs492)

Block Diagram:

Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2

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Y6=A0'.A1.A2
Y7=A0.A1.A2
Logical circuit of the above expressions is given below:

4 to 16 line Decoder
In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2 ,……, Y16 and four inputs, i.e.,
A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed using either 2 to 4 decoder or 3 to 8
decoder. There is the following formula used to find the required number of lower-order decoders.
Required number of lower order decoders=m2/m1
m1 = 8
m2 = 16

Required number of 3 to 8 decoders= =2

Block Diagram:

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Computer architecture laboratory(pcc-cs492)

Truth Table:

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Computer architecture laboratory(pcc-cs492)

The logical expression of the term A0, A1, A2,…, A15 are as follows:
Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'

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Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3
Logical circuit of the above expressions is given below:

Multiplexer

A multiplexer is a combinational circuit that has 2n input lines and a

single output line. Simply, the multiplexer is a multi-input and
single-output combinational circuit. The binary information is

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received from the input lines and directed to the output line. On the
basis of the values of the selection lines, one of these data inputs
will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2n input
lines. So, there is a total of 2N possible combinations of inputs. A
multiplexer is also treated as Mux.

There are various types of the multiplexer which are as follows:

2×1 Multiplexer:

In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1
selection line, i.e., S0 and single outputs, i.e., Y. On the basis of the
combination of inputs which are present at the selection line S0,
one of these 2 inputs will be connected to the output. The block
diagram and the truth table of the 2×1 multiplexer are given
below.

43.6M

706

Hello Java Program for Beginners

Block Diagram:

Truth Table:

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Computer architecture laboratory(pcc-cs492)

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

4×1 Multiplexer:

In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1,
A2, and A3, 2 selection lines, i.e., S0 and S1 and single output, i.e.,
Y. On the basis of the combination of inputs that are present at the
selection lines S0 and S1, one of these 4 inputs are connected to the
output. The block diagram and the truth table of the 4×1
multiplexer are given below.

Block Diagram:

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Computer architecture laboratory(pcc-cs492)

Truth Table:

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

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8 to 1 Multiplexer

In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1,
A2, A3, A4, A5, A6, and A7, 3 selection lines, i.e., S0, S1and S2 and
single output, i.e., Y. On the basis of the combination of inputs that
are present at the selection lines S0, S1, and S2, one of these 8
inputs are connected to the output. The block diagram and the
truth table of the 8×1 multiplexer are given below.

Block Diagram:

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Computer architecture laboratory(pcc-cs492)

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+
S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.S1.S3.A7

Logical circuit of the above expression is given below:

8 ×1 multiplexer using 4×1 and 2×1 multiplexer

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Computer architecture laboratory(pcc-cs492)

We can implement the 8×1 multiplexer using a lower order

multiplexer. To implement the 8×1 multiplexer, we need two 4×1
multiplexers and one 2×1 multiplexer. The 4×1 multiplexer has 2
selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has
only 1 selection line.

For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1
multiplexer produces one output. So, in order to get the final
output, we need a 2×1 multiplexer. The block diagram of 8×1
multiplexer using 4×1 and 2×1 multiplexer is given below.

16 to 1 Multiplexer

In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A0, A1,

…, A16, 4 selection lines, i.e., S0, S1, S2, and S3 and single output,
i.e., Y. On the basis of the combination of inputs that are present at
the selection lines S0, S1, and S2, one of these 16 inputs will be
connected to the output. The block diagram and the truth table of
the 16×1
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Computer architecture laboratory(pcc-cs492)

Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

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Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3

+A4.S0'.S1.S2'.S3'+A5.S0 '.S1.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0
.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S2.S3 '+A11.S0.S1'.S2.S3+A12
S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

Logical circuit of the above expression is given below:

16×1 multiplexer using 8×1 and 2×1 multiplexer

We can implement the 16×1 multiplexer using a lower order

multiplexer. To implement the 8×1 multiplexer, we need two 8×1

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multiplexers and one 2×1 multiplexer. The 8×1 multiplexer has 3

selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has
only 1 selection line.

For getting 16 data inputs, we need two 8 ×1 multiplexers. The

8×1 multiplexer produces one output. So, in order to get the final
output, we need a 2×1 multiplexer. The block diagram of 16×1
multiplexer using 8×1 and 2×1 multiplexer is given below.

Data Flow Modeling

In this modeling style, the flow of data through the entity is expressed
using concurrent (parallel) signal. The concurrent statements in VHDL
are WHEN and GENERATE.
Besides them, assignments using only operators (AND, NOT, +, *, sll,
etc.) can also be used to construct code.
Finally, a special kind of assignment, called BLOCK, can also be
employed in this kind of code.
In concurrent code, the following can be used −

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 Operators
 The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
 The GENERATE statement;
 The BLOCK statement
Behavioral Modeling
In this modeling style, the behavior of an entity as set of statements is
executed sequentially in the specified order. Only statements placed
inside a PROCESS, FUNCTION, or PROCEDURE are sequential.
PROCESSES, FUNCTIONS, and PROCEDURES are the only sections
of code that are executed sequentially.
However, as a whole, any of these blocks is still concurrent with any
other statements placed outside it.
One important aspect of behavior code is that it is not limited to
sequential logic. Indeed, with it, we can build sequential circuits as well
as combinational circuits.
The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES
are also restricted and they are supposed to be used in sequential code
only. VARIABLE can never be global, so its value cannot be passed out
directly.

Structural Modeling
In this modeling, an entity is described as a set of interconnected
components. A component instantiation statement is a concurrent
statement. Therefore, the order of these statements is not important.
The structural style of modeling describes only an interconnection of
components (viewed as black boxes), without implying any behavior of
the components themselves nor of the entity that they collectively
represent.
In Structural modeling, architecture body is composed of two parts − the
declarative part (before the keyword begin) and the statement part
(after the keyword begin).

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1) 4x1 mux by switch case with enable pin:

2) 4x1 mux by buses in data flow model:

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3) 4x1 mux by 2x1 mux:

4)mux web form:

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Conclusion:
The adder forms the basis for all of the arithmetic functions in the ALU.
Subtraction, multiplication, and division all are implemented using
algorithms which are based on the adder. The adder is therefore a stand
in for all of the other types of functions performed by the ALU.

Despite the appearance that addition is more complex, it can be

implemented as a Boolean function consisting only of AND, OR, and XOR
gates. These simple Boolean functions are implemented in circuits called
half adders and full adders. It is when these functions are chained
together so that the carry from each previous function is used in the
next function that the adder can add larger numbers.

The implementation of the full adder circuit is more complex than the
other circuits which have been looked at so far. It required 3 different
chips, 2 outputs, and 5 gates that had to be connected. This circuit
required some degree of carefulness and forethought to implement and
debug it.

The adder was the first circuit implemented in this text that is a
component, and it has been encapsulated as an IC. The 7482 (2-bit
binary full adder) and 7483 (4-bit binary full adder) IC chips are
implementations of this circuit.

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