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Module 1-ASIC Design Methodology & Design Flow: Building A Chip

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6 views61 pages

Module 1-ASIC Design Methodology & Design Flow: Building A Chip

Uploaded by

rishiraj.dutta2024
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 1- ASIC Design

Methodology & Design Flow


Implementation Strategies for Digital ICs: Custom IC
Design- Cell-based Design Methodology - Array based
implementation approaches - Traditional and Physical
Compiler based ASIC Flow.

Dr A Prathiba
Building a Chip CNVD
VIT Chennai
An example ASIC diagram. Image used courtesy of Intel
Figure 1 shows an ASIC that combines a standard digital signal processor (DSP) core
with additional circuitry required for the customer’s intended application.
The Custom Approach

Intel 4004

Courtesy Intel
Transition to Automation and Regular
Structures

Intel 4004 (‘71)


Intel 8080 Intel 8085

Intel 8286 Intel 8486


Courtesy Intel
Levels of abstraction
Levels of abstraction
How a chip is built

• Definition and Planning


• Design and Verification (Frontend)
• Logic Synthesis (Frontend and Backend)
• Physical Design (Backend)
• Signoff and Tapeout
• Silicon Validation

• Don’t forget package &board design,


software design, test plan, etc., etc., etc.
Definition & Planning

Definition and Planning


• Marketing Requirements Document (MRD)
• ChipArchitecture Design and Verification
• Define bus structures, connectivity
Logic Synthesis
• Partition Functionality
• High-Level System Model (Bandwidths, Power, Freq.) Physical Design
• System partitioning (HW vs SW, #Cores, Memories…)
• Design Documents Signoff and Tapeout

• Floorplan/Board Requirements Silicon Validation


• Process and fab
• Project kick-off – transfer to implementation
Design and Verification

• RTL(Register Transfer Level) Design Definition and Planning

• Integration/Development of IPs Design and Verification


• RTLLint/Synthesability checks
Logic Synthesis
• Formal Verification
• Functional verification all the IPs: Physical Design
• Unit level
Signoff and Tapeout
• Sub-system level
• Chip (SOC) level Silicon Validation
• Hard IP
• IP provided as pre-existing layouts with:
• Timing models
• Layout abstracts
• Behavioural models
(Verilog/VHDL)
• Sometimes with Spice models,
full-layouts
• This is the standard delivery format for custom digital blocks
• RAMs, ROMs, PLLs, Processors
• Soft IP
• RTL Code
• Can be encrypted
• Instantiated just like any other RTL block
• Sometimes with behavioral models
Design and Verification - Prototyping

• Different levels of verification:


• Specification driven testing
• Bug driven testing
• Coverage driven testing
Source: mouser.c om
• Regression
• FPGAPrototyping:
• Synthesize to FPGA
• Speeds up testing
where possible.
• Hardware Emulation:
• Big servers that can
emulate the entire
design.
Source: C adence
Logic Synthesis

Definition and Planning


• Inputs: • Synthesis
• Technology library file • Converting RTL code into a generic logic Design and Verification
netlist
• RTL files
• Constraint files (SDC) • Mapping Logic Synthesis
• DFT definitions • Mapping generic netlist into standard cells
from the core library Physical Design
• Output:
• Gate-level netlist • Optimization
Signoff and Tapeout
• To meet Timing / Area / Power constraints

module DFF(Clk, D, Q); Silicon Validation


input Clk;
input D; • Post Synthesis checks
output Q;
always @(posedge Clk) • Gate-level simulation
Q <= D; • Formal verification (Logic Equivalence)
endmodule • Static Timing Analysis (STA)
• Power/Area estimation
Physical Design (Backend)

• Floorplan Definition and Planning


• I/ORing
Design and Verification
• Power Plan
• Placement Logic Synthesis

• Clock Tree Physical Design


Synthesis
• Route Signoff and Tapeout

• DRC, LVS, Silicon Validation


Antennas, EM
• LEC, Post-layout
Physical Design – Backend Flow

• Physical Implementation Inputs

Front-End Vendors Foundry


Spec Standard Cells Device Models

Architecture Memory Compiler Techfile

RTL I/Os Design Rules

Verification Hard IPs

Physical Design
(Backend)
Physical Design – Backend Flow

RTL
Synthesizer Gate Level
SDC
Standard Cells and ATPG GTL with Scan
Macros

Scan Chains Placer Placed Design

Floorplan CTS
Design with
Clock Tree
Power Grid,
Special Routing
Router Routed Design
Clock Definitions
Extraction, STA, DRC,
LVS, Density, Antennas, GDSII
Caps, Power/EM
Signoff and Tapeout

Definition and Planning

• Parasitic Extraction Design and Verification

• STAwith SI Logic Synthesis


• DRC/LVS/ERC/DFM
• Post-layout Gate-level Simulation
• PowerAnalysis
• DFT
• Logic Equivalence
ASIC
Design Flow
ASIC Design Flow
FPGA Vs ASIC Design Flow
ASIC Design Flow
with
Cadence EDA Tools
Types of ASICs
The designer manually controls the number and width of the vertical power rails
connected to the standard-cell blocks during physical design.
Programmable
Logic Devices
(PLDs)
Examples of
PLD
Types of PLDs
- PLA and PAL

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