Module 02

Processor Organization and

Architecture
By
Mrs Sudeshna Baliarsingh
Dept. of IT
Reference book:
1. B. Govindarajulu, Computer Architecture and Organization:
Design Principles and Applications.

2. J. Hayes, Computer Architecture and Organization, McGraw

Hill.
 Processor Organization and Architecture
1. CPU Architecture
2. Instruction Formats
3. Basic Instruction Cycle with Interrupt Processing
4. Instruction Interpretation and Sequencing
5. Control Unit: Soft Wired (Microprogrammed) and Hardwired
Control Unit
6. Microinstruction Sequencing and Execution
7. Micro Operations
8. Concepts of Nano Programming
9. Introduction to Parallel Processing Concepts
10. Flynn’s Classifications
11. Instruction Pipelining
12. Pipeline Hazards
CPU Architecture 8086
 Instruction Formats
If a programmer is using a high-level language, such as Pascal or Ada, very
little of the architecture of the underlying machine is visible. One boundary
where the computer designer and the computer programmer can view
the same machine is the machine instruction set. From the designer’s
point of view, the machine instruction set provides the functional
requirements for the processor

You must be conscious that a program written in a high-level language

cannot be executed directly by the CPU. As a result, each software is first
converted to binary format. The high-level program is translated by the
compiler into its corresponding low-level instruction, which contains the
numbers 0 and 1. These commands are computer-organized machine
orders that the processor can carry out immediately.
The operation of the processor is determined by the instructions it
executes, referred to as machine instructions or computer
instructions. The collection of different instructions that the
processor can execute is referred to as the processor’s
instruction set.

Instruction Representation

It is difficult for both the programmer and the reader of textbooks to deal with binary
representations of machine instructions. Thus, it has become common practice to use a
symbolic representation of machine instructions.
1. Instruction includes a set of operational codes, operands, opcode, and
addressing mode.

2. Instruction length is the most fundamental issue of the format design. The longer
the instruction, the longer will be the time taken to fetch the instruction.

3. The number of bits is directly proportional to the memory range. i.e., the larger
the range requirement, the more number bits will be required.

4. If a system supports the virtual memory, then the memory range that needs to be
addressed by the instruction will be larger than the physical memory.

5. Instruction length should be equal to or the multiple of data bus length.

Opcodes are represented by abbreviations, called
mnemonics, that indicate the operation. Common examples
include

ADD Add
SUB Subtract
MUL Multiply
DIV Divide
LOAD Load data from memory
STOR Store data to memory

Operands are also represented symbolically.

Ex: ADD AX,BX
What are the Different Types of Instruction Fields?

A computer performs a task based on the instructions provided.

Instructions in computers are comprised of groups called fields. These
fields contain different information for computers which are all written in 0s
and 1s. Each field has a different significance or meaning, based on
which a CPU decides what to perform. The most common fields are:

● The operation field- specifies the operation to be performed, like

addition.
● Address field -which contains the location of the operand, i.e., register
or memory location.
● Mode field -which specifies how operand is to be founded.
Computer instructions can be any length and comprise any number of addresses. The internal
layout of a computer’s registers determines how many address spaces it has. The majority of
computers fit into one of three categories:
1. Single Accumulator Organization
All the operations on a system are performed with an implied
accumulator register. The instruction format in this type of computer
uses one address field.
For example, the instruction for arithmetic addition is defined by an
assembly language instruction ‘ADD.’

Where X is the operand’s address, the ADD instruction results in the

operation.
AC ← AC + M[X].

AC is the accumulator register, M[X] symbolizes the memory word

located at address X.
2. General Register Organization
The general register type computers employ two or three address fields
in their instruction format.
Each address field specifies a processor register or a memory.

An instruction symbolized by ADD R1

This instruction has two address fields: register R1 and memory

address X.
What is Instruction Format?

The forms for the instructions are a series of bits (0 and 1). When these pieces are
combined, they form fields. The CPU receives precise information about the operation and
location of the data from each field of the machine.

The bit configuration for an instruction is also specified by the instruction format. It may have
a variety of locations and be of varying lengths. The address elements in the instruction format
change depending on how the CPU’s registers are set up. The CPU’s supported file formats
rely on the Instructions Set Architecture the processor has put in place.
Depending on the multiple address fields, the instruction is categorized as follows:

● Zero address instruction

● One address instructions
● Two address instruction
● Three address instruction
1. Zero Address Instruction
Zero-address instructions are a concept used primarily in stack-based computer
architectures. Zero-address instructions do not explicitly specify any operands
within the instruction itself. Instead, they operate entirely on the data present
in a stack, which is a last-in, first-out (LIFO) data structure.
Or
Instead, they operate on data stored in registers or memory locations implicitly
defined by the instruction. For example, a zero-address instruction might simply add
the contents of two registers together without specifying the register names.

All operations are performed on the top elements of the stack.

For instance, to add two numbers, both numbers must first be pushed onto
the stack. The ADD instruction would then pop these two values from the
stack, add them, and push the result back onto the stack.
One address can be a register name or memory address.

• SINGLE ACCUMULATOR ORGANIZATION

• It uses AC register for all data manipulation

• Instruction: ADD X
Microoperation: AC AC + M[X]
Two address registers or two memory
locations are specified
• Assumes that the destination address is the
same as that of the first operand.
• Instruction: ADD R1, R2
Microoperation: R1 R1 + R2
• Memory addresses for the two operands and
Instruction: ADD R1, R2, R3
one destination need to be specified. Microoperation: R1 R2 + R3
• It is also called General register organization.
Write the program to evaluate the expression X =A [B+C(D+E)]/ F(G+H) using the zero
address instructions and one address instructions.
Solution :Program using zero address instructions
PUSH D ; TOS←D PUSH G ; TOS←G
PUSH E ; TOS←E PUSH H ; TOS←H
ADD ; TOS←(D+E) ADD ; TOS←G+H
PUSH C ; TOS←C PUSH F ; TOS←F
MUL ; TOS←C×(D+E) MUL ; TOS←F× (G + H)
PUSH B ; TOS←B DIV ; TOS A[B+C× (D+ E)]/F× (G + H)
ADD ; TOS←B+C×(D+E) POP X ; M [X] ← TOS

PUSH A ; TOS←A
MUL ; TOS←A[B+C×(D+E)]
Program using one address instructions
Write the program to evaluate the
LOAD H ; AC← M[H]
expression X =A [B+C(D+E)]/ F(G+H) using
ADD G ; AC←AC + M[G]
the zero address instructions and one
MUL F ; AC←AC*M[F]
address instructions.
STORE T ; M[T]←AC
LOAD D ; AC← M[D]
ADD E ; AC←AC + M[E]
ADD B ; AC←AC + M[B]
MUL A ; AC←AC* M[A]
DIV T ; AC←AC/M[T]
STORE Χ ; M[X] ← AC
Example 3 X = A×B+C×C

Explain how the above expression will be executed in one address, two address and three address processors in
an accumulator organization.

Solution :

Using one address instruction Using two address instructions Using three address instructions

LOAD A ; AC← M[A] MOV A, R1 ; R1←M[A] MUL A, B, R1 ;

R1←M[A]*M[B]
MUL B ; AC←AC* M[B] MUL B, R1 ; R1←R1*M[B]
MUL C, C, R2 ;
STORE T ; M[T] ←AC MOV C, R2 ; R2←M[C] R2←M[C]+M[C]

LOAD C ; AC← M[C] MUL C, R2 ; R2←R2*M[C] Add R1, R1, X ; M[X]

←R1*R2
MUL C ; AC←AC* M[C] ADD R2, R1 ; R1←R1+R2

ADD T ; AC←AC + M[T] MOV R1, X ; M[T]←R1

STORE X ; M[X] ← AC
Basic Instruction Cycle with Interrupt Processing
Instruction Cycle
A program residing in the memory unit of the computer consists of a sequence of instructions.
The program is executed in the computer by going through a cycle for each instruction.
Each instruction cycle in turn is subdivided into a sequence of sub-cycles or phases.
Instruction Cycle:
In the basic computer each instruction cycle consists of the following phases:

Fetch an instruction from memory

2. Decode: Decode the instruction Decode
3. Operand Fetch: Read the effective address from memory if the instruction has a indirect address Operand
4. Execute: Execute the instruction

Upon the completion of step 4, the control goes back to step I to fetch, decode and execute the next instruction.
This process continues indefinitely unless a HALT instruction is encountered.

To perform fetch, decode and execute cycles the processor has to perform set of microperations.
 Basic Instuction
Instuction cycle with Interrupt cycle
 Instruction execution and straight line sequencing
Instruction execution :
Instruction execution needs the following steps, which are

● PC (program counter) register of the processor gives the address of the instruction which needs to be
fetched from the memory.
● If the instruction is fetched then, the instruction opcode is decoded. On decoding, the processor
identifies the number of operands. If there is any operand to be fetched from the memory, then that
operand address is calculated.
● Operands are fetched from the memory. If there is more than one operand, then the operand fetching
process may be repeated (i.e. address calculation and fetching operands).
● After this, the data operation is performed on the operands, and a result is generated.
● If the result has to be stored in a register, the instructions end here.
● If the destination is memory, then first the destination address has to be calculated. Then the result is
then stored in the memory. If there are multiple results which need to be stored inside the memory, then
this process may repeat (i.e. destination address calculation and store result).
● Now the current instructions have been executed. Side by side, the PC is incremented to calculate the
address of the next instruction.
● The above instruction cycle then repeats for further instructions.
Instruction execution
Six steps are involved in execution of an instruction by CPU. However, not
all of them are required for all instructions.

1. Fetch instruction
2. Decode information
3. Perform ALU operation
4. Access memory
5. Update register file
6. Update the Program Counter (PC)
Instruction Execution and Straight Line Sequencing
• We have seen that instruction consists of opcode or opcode and operand/s or opcode and operand address.

• Every processor has some basic types of instructions such as data transfer instructions, arithmetic instructions,
logical instructions, branch instructions and so on.

• To perform a particular task on the computer, it is programmers job to select and write appropriate instructions
one after the other, i.e. programmer has to write instructions in a proper sequence. This job of programmer is
known as instruction sequencing.

• The instructions written in a proper sequence to execute a particular task is called program.

• Processor executes a program with the help of Program Counter (PC). PC holds the address of the instruction to
be executed next.

• To begin execution of a program, the address of its first instruction is placed into the PC. Then, the processor
control circuits use the information (address of memory) in the PC to fetch and execute instructions, one at a time,
in the order of increasing addresses. This is called straight-line sequencing.

• During the execution of instruction, the PC is incremented by the length of the current instruction in execution.
For example, if currently executing instruction length is 3 bytes, the PC is incremented by 3 so that it points to the
instruction to be executed next.
Straight line sequencing:
MOV AX,[A]
Straight line sequencing means the instruction of a
program is executed in a sequential manner ADD AX,[B]
(i.e. every time PC is incremented by a fixed offset). And no
branch address is loaded on the PC. MOV [C],AX
Example –

Here, programs and data are stored in the same memory, i.e. von Neumann
architecture.
The program starts executing at address i and follows the instructions sequentially.
The straight line sequencing means no jumps, loops, or branches are involved, so
the instructions are executed one after the other as they appear in memory.
First Instruction: MOV AX, [A]

This instruction moves the data stored at memory location A into the AX register.
Second Instruction: ADD AX, [B]

This instruction adds the data stored at memory location B to the content of the
AX register.
Third Instruction: MOV [C], AX

This instruction moves the content of the AX register (which now holds the sum
of values from locations A and B) into memory location C.
Control Unit: Soft Wired (Microprogrammed)
and Hardwired Control Unit
● The control unit (CU) is a crucial component of a computer's central
processing unit (CPU), responsible for directing the operation of the
processor.

● It interprets the instructions in the machine code and generates the

necessary control signals to execute these instructions.

● To execute an instruction, the control unit of the CPU must generate the
required control signal in the proper sequence.

● There are two approaches used for generating the control signals in proper
sequence as Hardwired Control unit and the Micro-programmed control
unit.
Basically the control unit converts each machine language instruction into a
series of control signals which activate the control points in datapath.

The Figure 6.26 shows the input and output of the control unit. There are two
ways to design a control unit:

1. Hardwired -In a hardwired control unit, the digital circuits generate the
control signals

2. (Softwired) Microprogrammed-In a microprogrammed control unit, the

control signals are stored as bit patterns in a read only memory, inside the
control unit.

The hardwired control unit is the conventional design technique whereas

microprogrammed control unit is relatively a modern technique.
 Hardwired Control Unit
A hardwired control unit consist of a collection of combinational circuits to generate
various control signals.

Figure 6.27 shows an overall block diagram of the hardwired control unit.

The clock is a periodic signal that gives timing reference.

The opcode identifies the current instruction.

The CPU status flags indicate the present status of CPU such as overflow, carry etc.
In addition, special situations like ‘waiting for MFC’ {(Wait for
Memory-Function-Completed)} are also included in these.

Using these three types of inputs, the combinational circuits in the control unit generate
the relevant control signals.
The timing pulses T1, T2, T3 etc.
have definite time delays.

They are used as time reference

signals.

For a given instruction, the

required microoperations are time
sequenced using the timing
pulses.
For example, for LDA instruction, if reading
from memory is done in T1.

Then storing in accumulator can be done in Memory Address Register

T2. Memory Data Register
Memory Read

The signal combination of ‘LDA’ and ‘T1’ can

be used as the control signal for reading from
the memory.

Another signal combination of ‘LDA’ and ‘T2’ For generating some of the control signals, status of the
can be used as the control signal for storing in CPU flags is used.
the accumulator.
For example, for JZ ( Jump, if the accumulator is zero)
Figure 6.29 shows how two gates generate instruction, the zero flag is used along with T1 and JZ as
shown in Fig. 6.30. The control signal is generated, if the
these control signals during the execution of
zero flag is 1.
the LDA instruction.

This concept is used for generating all the

control signals.
 The principle of operation of the hardwired control unit
The principle of operation of the
hardwired control unit is shown in Fig.
6.28.

Each dot represents a circuit that generates

one or more control signals.

Each vertical line represents an

instruction.

Each horizontal line represents a timing

pulse train.
ADD-Addition
SUB- Subtraction
NOOP-No-Operation, HALT- Stops Execution
BUN- Branch Unconditionally
The hardwired control unit has circuits for the following:

1. Identifying the instruction from the opcode and generating relevant

signals such as ADD, NOOP, HALT etc. At a given time, one of the instruction
signals corresponding to the opcode is active and others are inactive.

2. Maintaining time reference by generating a sequence of timing pulses.

3. Generating a set of control signals corresponding to the microoperations

to be done for the current instruction at proper time intervals.

4. After completing the execution of one instruction, generation of control

signals necessary for fetching the next instruction.

5. Handling special sequences such as reset sequence, interrupt sequence

and abnormal situation handling.
Advantages of Hardwired Control Unit

1. A hardwired control unit works fast.

2. The combinational circuits generate the control signals based on the input signals status.
3. As soon as the required input signal combination occurs, immediately the output (control signal)
is generated by a combinational circuit.
4. The delay between the output generation to input availability depends on the number of gates in
the circuit path and propagation delay of each gate in the path.
5. If there are two gate levels and each gate has 5 hs propagation delay, the time taken for the
control signal generation is 10 hs.
Disadvantages of Hardwired Control Unit
1. If the CPU has a large number of control points, the control unit design becomes very complex.
2. It is tedious to design the pulse distributor circuitry (combinational circuits) since several signal
combinations have to be kept track of during designing.
3. The design does not give any flexibility.
4. If any modification is required, it is extremely difficult to make the correction.
5. Design modification becomes necessary under the following situations:
(a) There is a design mistake in the original design.
(b) A new feature (e.g. a new instruction) is to be added to an existing design.
(c) A new hardware component (e.g. memory) of higher speed is available, which will
improve the performance.
 Microprogrammed Control Unit
Microprogramming is a modern concept used for designing a control unit. It can be used for designing
control logic for any digital system.

Some common applications are I/O controllers such as disk controller, and peripheral devices such as
printer and hard disk drive.

The philosophy of microprogramming is based on ‘reading stored control patterns.

The microoperations are executed when the corresponding control signals are made active.

Each instruction needs a specific set of microoperations (Fig. 6.39) in an order (time sequence).

The control signals needed for an instruction and the time sequence can be stored in the memory known
as control memory.

By fetching the control memory words one-by-one, the control signals can be generated. The control
memory is a read only memory.

Any common activity occurring in control unit such as interrupt handling, instruction fetch etc. can be
translated into control memory words.
The control unit can only read from the control memory but cannot modify the contents.
In a simplest form, each bit in the control memory word can be reserved for a control
signal; thus, separate bits for all control signals can be used.

If the bit is 1, the corresponding control signal is activated. If the bit is 0, the control
signal is not activated. When a control memory word is fetched from the control memory,
some bits may be 1 and others 0.

The control signals corresponding to ‘1’ bits are generated. Thus, multiple
microoperations are executed simultaneously.

Each control memory word is known as a microinstruction.

The reader needs to be very careful in writing microinstructions manually.

However, there are powerful software tools such as cross assemblers for developing
micoprograms which simplify the task.
The control unit fetchs these microinstructions from control memory
one-by-one.

As soon as a microinstruction is loaded in the microinstruction register, the

control signals which are indicated as ‘1’ in the microinstruction register, are
activated.

As a result, the relevant microoperations are performed.

 Issues in Microprogrammed Control Unit
The Control Memory Address Register (CMAR) is also known as a microprogram counter.

The CMDR is a control memory data register.

It is also known as microinstruction register.

The following issues have to be resolved in a microprogrammed CU:

1. There is a separate execute microprogram for each instruction such as—ADD, SUB, LDA, etc. After the
instruction fetch is over, how does the execute microprogram gets control?

2. After the completion of any execute microprogram, how does control goes to fetch microprogram?

3. After the power-on, how does the control unit start the appropriate microprogram ?

4. Frequently, certain microinstructions have to be skipped and the control unit has to branch on the basis of
certain status in the CPU.
For example, the carry flag or zero flag status dictates the exact action required after the completion of an arithmetic
operation. Similarly, the IE flag status decides the action path to be followed on sensing the interrupt request. Hence, we
need a mechanism for conditional branching.

5. Assigning a bit to each control signal leads to a long width of the control memory word. This makes it
expensive. Hence, we need techniques to reduce the length of microinstruction.
6. Many micro operations of certain instructions are
common.

For example, the actions required for ADDB and SUBB

instructions differ only in one aspect.
The ADD instruction uses B whereas the SUB instruction
uses complement of B.
Otherwise, all the micro instructions are same including
addition.

Having totally separate execute microprograms for each

instruction, increases the size (number of locations) of
the control memory.

We need some technique for combining such

microinstructions.

The ADD and SUB instruction can have a common

execute microprogram and one should handle both these
requirements by a single microroutine so as to reduce
the control memory capacity.
Advantages of Microprogrammed Control Unit

1. The design of microprogram control unit is less complex as compared to the hardwired control unit.

Often people say that microprogramming is a systematic way of designing the control unit. However, it should be
noted that even the hardwired CU is designed systematically, but it is more complex. The design of a hardwired CU
needs the knowledge of digital electronics, whereas the design of a microprogrammed CU can be done without it.

2. The microprogrammed control unit is flexible since modification is easy as it involves simply changing the
contents of control memory. This simplifies design correction, design enhancement and modification.

3. The meaning of a given CPU’s instruction set can be easily modified by changing the microprograms without
affecting the datapath.

This facility is used to emulate another system using the present system. Emulation of a future system under the
planning stage is also possible by modifying the microprograms of an existing system. This helps in evaluating the
performance of a system in advance.

4. The debugging and maintenance of a microprogrammed CPU is easy.

The microinstructions can be executed one-by-one in a diagnostic mode, simultaneously monitoring the contents of
registers, counters, flags etc. Similarly, autodiagnostics is possible with the help of microdiagnostics.
Disadvantages of Microprogrammed Control Unit

1. A microprogrammed CU is slow.

The microinstructions are stored in the control memory. Fetching them takes time.

Since one instruction cycle is covered by several (varying from 3 to 20) microinstructions, total
instruction cycle of a microprogrammed CU is more.

2. For a small CPU with very limited hardware resources, a microprogrammed CU is

expensive as compared to a hardwired CU.
 Questions For Practice
Out of Syllabus
1. Write down the microoperations needed for the following instruction: EXCHANGE
R1, R3

2. A processor has following hardware configuration: (a) No. of registers = 8 (b) ALU
operations: arithmetic 8, logic 8 (c) Shifter : 4 operations (d) Bus: single bus Design
the microinstruction format for this CPU.

3. A control unit’s microinstruction has 9 bits for specifying the microoperations.

Assume that it is divided into two fields: one having 5 bits and the other with 4 bits.
How many different micro operations are possible in the CPU?

4. A microprogrammed CPU has 1 K words in control memory. Each instruction needs

8 microinstructions. Assuming that the opcode in the micro instruction is of 5 bits
length, propose a mapping scheme to generate control memory address for the
opcode.
Summary of Hardwired and Soft-wired
Control Design
Hardwired Control Unit:
The control hardware can be viewed as a state machine that changes from one state to
another in every clock cycle, depending on the contents of the instruction register, the
condition codes, and the external inputs. The outputs of the state machine are the control
signals. The sequence of the operation carried out by this machine is determined by the
wiring of the logic elements and hence named “hardwired”.

● Fixed logic circuits that correspond directly to the Boolean expressions are used to
generate the control signals.
● Hardwired control is faster than micro-programmed control.
● A controller that uses this approach can operate at high speed.
● RISC architecture is based on the hardwired control unit

Micro-programmed Control Unit –

The control signals associated with operations are stored in special memory units
inaccessible by the programmer as Control Words.
Control signals are generated by a program that is similar to machine language programs.
The micro-programmed control unit is slower in speed because of the time it takes to fetch
micro instructions from the control memory.
 ● Microinstruction Sequencing and Execution
● Micro Operations
● Concepts of Nano Programming

Differentiate between micro-operation and micro-instruction.

Instructions present in control memory are called microinstructions, whereas the atomic
operations that execute a particular microinstruction are called micro-operation.
 Microprogramming

The control unit is responsible for initiating the sequence of microoperations

that comprise instructions.

–When these control signals are generated by hardware, the control unit is
hardwired.

–When these control signals originate in data stored in a special unit and
constitute a program on the small scale, the control unit is microprogrammed.
 Control Memory
The control function specifying a microoperation is a binary variable whose
active state could be either 1 or 0.
–In the variable’s active state, the micro operation is executed.
–The string of control variables which control the sequence of microoperations is
called a control word.

• The microoperations specified in a control word is called a microinstruction.

–Each microinstruction specifies one or more microoperations that is performed.

• The control unit coordinates stores microinstruction in its own memory (usually
ROM) and performed the necessary steps to execute the sequences of
microinstructions (called microprograms).
 The Microprogrammed Control Unit

In a microprogrammed processor, the control unit consists of

–Control address register(CAR)–contains the address of the next microinstruction to

be executed.

–Control data register(CDR)–contains the microinstruction to be executed.

–The sequencer–determines the next address from within control memory

–Control memory–where microinstructions are stored.

 Addressing Sequencing (continued)
• When instruction execution is finished, control must be return to the
fetch routine.

This is done using an unconditional branch.

• Addressing sequencing capabilities of control memory include:

–Incrementing the CAR

–Unconditional and conditional branching (depending on status
bit).
–Mapping instruction bits into control memory addresses
–Handling subroutine calls and returns.
 Mapping
The next step is to generate the micro operations that executed
the instruction.

–This involves taking the instruction’s opcode and

transforming it into an address for the the instruction’s
microprogram in control memory.

This process is called mapping.

Microinstruction
Code:

1100 1010 0011 0001 10 01

 Micro Operations
● In computer central processing units, micro-operations (also known as micro-ops) are the functional or
atomic, operations of a processor.

● These are low level instructions used in some designs to implement complex machine instructions.
● They generally perform operations on data stored in one or more registers.

● They transfer data between registers or between external buses of the CPU, also performs arithmetic and
logical operations on registers.

● In executing a program, operation of a computer consists of a sequence of instruction cycles, with one
machine instruction per cycle.

● Each instruction cycle is made up of a number of smaller units – Fetch, Indirect, Execute and Interrupt
cycles.

● Each of these cycles involves series of steps, each of which involves the processor registers.

● These steps are referred as micro-operations. the prefix micro refers to the fact that each of the step is
very simple and accomplishes very little.
 Concepts of Nano
Programming

(a) conventional microprogram - one level; (b) corresponding nanoprogram - two levels.

This nano programming technique is used to reduce the width of

microinstructions, making the control memory more efficient while still providing
the necessary control signals through a second-level decoding process.
This example illustrates how nanoprogramming can significantly reduce the size of the Control Memory (CM)
needed to store a microprogram by leveraging the fact that many microinstructions are repeated.

Original Microprogram:
● The original microprogram has a size of 4096 x 100 bits.
○ 4096: Number of microinstructions.
○ 100 bits: Width of each microinstruction.

Total size of CM without nano programming:

● CM Size = 4096 x 100 bits = 409,600 bits.

Nano programming Approach:

● The key observation here is that the original microprogram consists of only 128 different
microinstructions.(although the microprogram contains 4096 microinstructions in total, only 128 of these are
unique or distinct. )
○ If we store these 128 unique microinstructions in a separate memory (nano-memory), each of size 100
bits, then the size of this nano-memory would be:
■ Nano-memory Size = 128 x 100 bits = 12,800 bits.
Instead of storing the full 100-bit microinstruction in the CM, we can store a reference (address) to the nano-memory
where the actual microinstruction is stored.

● Since there are 128 unique microinstructions, 7 bits are enough to uniquely identify each microinstruction
(log2(128) = 7).

Now, the CM only needs to store these 7-bit references (addresses) instead of the full 100-bit microinstructions:

● CM Size = 4096 x 7 bits = 28,672 bits.

Total CM size using Nanoprogramming:

● Total CM Size (including nano-memory) = 28,672 bits (CM) + 12,800 bits (nano-memory) = 41,472 bits.

Memory Savings Calculation:

● Without Nanoprogramming: The required CM size is 409,600 bits.
● With Nanoprogramming: The total CM size is 41,472 bits.
 Introduction to Parallel Processing Concepts
Parallel processing is a computing technique
when multiple streams of calculations or
data processing tasks co-occur through
numerous central processing units (CPUs)
working concurrently.
For reference:
https://www.spicewor
ks.com/tech/iot/articl
es/what-is-parallel-pr
ocessing/
The capability of the processor varies in these different types.

The execution unit is indicated as a processor (PR) since it is more complex than a traditional
execution unit.

● The SISD is a traditional uniprocessor. There is a single control unit and a single execution
unit. Hence, it has one instruction and one data stream.

● The SIMD has one control unit that handles multiple execution units. Each execution unit
has a separate data stream.

● The array processor and Multi-Media Extension (MMX) in Pentium

are examples of this type. Basically, while executing a single instruction, simultaneously
multiple data paths operate on multiple data elements.

● The MISD involves multiple control units but a single execution unit. Such a system is not
practically feasible.

● The MIMD refers to multiple control units and multiple execution units. Multiprocessors
and parallel processors are examples of this type.
● A single processor takes data
from a single address in
memory and performs a
single instruction on the data
at a time
● The original Von Neumann
Architecture was SISD.
● Pipelining can be
implemented, but only one
instruction will be executed
at a time.
● All single processor systems
are SISD
1. Single Instruction, Single Data (SISD)
● In the type of computing called Single Instruction, Single Data (SISD), a single processor is
responsible for simultaneously managing a single algorithm as a single data source.

● A computer organization having a control unit, a processing unit, and a memory unit is
represented by SISD. It is similar to the current serial computer.

● Instructions are carried out sequentially by SISD, which may or may not be capable of
parallel processing, depending on its configuration.

● Sequentially carried-out instructions may cross over throughout their execution phases.

● There may be more than one functional unit inside a SISD computer.

● However, one control unit is in charge of all functional units. Such systems allow for
pipeline processing or using numerous functional units to achieve parallel processing.
2. Single Instruction, Multiple Data (SIMD)
● Computers that use the Single Instruction, Multiple Data (SIMD) architecture have multiple
processors that carry out identical instructions.

● However, each processor supplies the instructions with its unique collection of data.

● SIMD computers apply the same algorithm to several data sets. The SIMD architecture has
numerous processing components.

● All of these components fall under the supervision of a single control unit.

● While processing numerous pieces of data, each processor receives the same instruction
from the control unit.

● Multiple modules included in the shared subsystem aid in simultaneous communication with
every CPU.

● This is further separated into organizations that use bit-slice and word-slice modes.
2. Multiple Instruction, Single Data (MISD)
● Multiple processors are standard in computers that use the Multiple
Instruction, Single Data (MISD) instruction set.
● While using several algorithms, all processors share the same input data.
MISD computers can simultaneously perform many operations on the
same batch of data.

● As expected, the number of operations is impacted by the number of

processors available.

● The MISD structure consists of many processing units, each operating

under its instructions and over a comparable data flow.

● One processor’s output becomes the input for the following processor. This
organization’s debut garnered little notice and wasn’t used in architecture.
2. Multiple Instruction, Single Data (MISD)

Here, M = Memory Modules, P = Processor Units, and CU = Control Unit

Example
The experimental Carnegie-Mellon computer C.mmp (in 1971)
3. Multiple Instruction, Multiple Data (MIMD)
● Multiple Instruction, Multiple Data, or MIMD, computers are characterized by
the presence of multiple processors, each capable of independently
accepting its instruction stream.
● These kinds of computers have many processors. Additionally, each CPU
draws data from a different data stream.
● A MIMD computer is capable of running many tasks simultaneously.
● Although MIMD computers are more adaptable than SIMD or MIMD
computers, developing the sophisticated algorithms that power these
machines is more challenging.
● Since all memory flows are changed from the shared data area transmitted
by all processors, a MIMD computer organization incorporates interactions
between the multiprocessors.
● The multiple SISD operation is equivalent to a collection of separate SISD
systems if the many data streams come from various shared memories.
Pipelining is a
technique where
multiple
instruction stages
(or segments)
are overlapped
during execution.
This is similar to
an assembly line
in a factory
where different
stages of
production occur
simultaneously
for different
items.
Registers in the
Pipeline

Imagine that we
want to evaluate
the following
expression for
seven sets of
values: Ai*Bi+ Ci,
for i= 1, 2, 3, …, 7