Intel 8255 PPI

• Intel microprocessors can transfer data between

external devices such as input and output devices
through ports.
• In normal conditions a register can act as an I/O port.
However, having a separate register and configuring
it for input and output operation becomes difficult
and tedious.
• Intel has designed a separate IC 8255 with the
objective of interfacing input and output devices
with Intel microprocessors.
 Intel 8255 PPI

• 8255 is used on a range of several I/O cards that plug into

available slots in the personal computer (PC).

• This chip can perform both digital input and output (DIO)
operations from the processor in a preprogrammed
manner.
 8255 – common applications

• Turning on or off an electronic switch such as a

bipolar junction transistor (BJT), a metal oxide
semiconductor field effect transistor (MOSFET), or an
insulated gate bipolar transistor (IGBT).
• Controlling movement by use of DC/AC/stepper
motors
• Detecting the position using proximity sensors and
interfacing different sensors (temperature, flow,
pressure or level, etc.) through an analog to digital
converter (ADC)
 8255 – common features

• Three 8-bit ports named as A, B, and C are present.

• Port C has been divided to two groups of 4 bits each

as port C upper (PCU) and port C lower (PCL). Each of
them can be programmed independently for input
and output operation.

• All the ports can be programmed for simple I/O or

handshake I/O for the data transfer in I/O modes.
 8255 – common features

• Each port C bit can be set/reset individually in bit

set/reset (BSR) mode.

• Port A bits and PCU bits are grouped as group A (GA).

• Port B bits and PCL bits are grouped as group B (GB).

8255 internal block diagram
8255 Operating modes
8255 I/O Control Word Format
8255 I/O Control Word Format Contd..

The most significant bit (MSB) D7 is set to 1 to indicate that the

chip is configured in I/O mode. The bits D6 and D5 are used to
select the operating modes of group A to one of the following
three basic modes:

(a) Mode 0—Basic I/O (bits D6 and D5 are both 0)—Ports A, B,

and C can be operated as inputs or outputs. This mode uses
simple I/O operation and no interrupts are used. The outputs
written to the ports are latched and available at any time. Inputs
available at the port pins are buffered through port latches.
 8255 I/O Control Word Format

(b) Mode 1—Strobed or handshake I/O (bits D5 and D6 are 0 and

1, respectively)—Port A is configured in mode 1 but upper port C
is used for handshaking and control of data transfer in port A.
Input and output data are latched.
(c) Mode 2—Bidirectional bus (bits D5 and D6 are 1 and X,
respectively)— Port A is bidirectional (both input and output)
and port C is used for handshaking. Port B cannot be
programmed to this mode.
8255 BSR Control Word Format
 8255 BSR Control Word Format
• In BSR mode, any of the eight bits of port C can be set or reset
using a single control word written to the control register.

• This feature helps the programmer to control the port C pin

outputs individually.

• This feature is also used in the mode 1 and mode 2 I/O

operations wherein the individual ports of port C can be
controlled by the programmer to indicate the status and
control.
Intel Timer IC
8253/8254
 Intel Timer IC 8253
• In software programming of the 8086, it has been shown that
a delay subroutine can be programmed to introduce a
predefined time delay.
• The delay is achieved by decrementing a count value in a
register using instructions. The disadvantage of this software
approach is that the processor is locked in the delay loop and
precious processor time is lost in counting.
• This can be overcome by using hardware timer and interrupts.
 Intel Timer IC 8253

• IC 555 can be used to generate the timing signals, but only at a

fixed time interval. This cannot be easily interfaced with the
microprocessor.
• Intel finally produced programmable timer devices namely IC
8253 and IC 8254.
• These ICs can be programmed to generate different types of
delay signals and also count external signals.
 IC 8253 features
Following is the list of major features of the IC 8253.

(a) Generation of accurate time delay

(b) Three independent 16-bit down counters called channels
(c) Six different programmable operating modes
(d) Timer or counter operation
(e) Counting in binary or BCD
(f) Capability to interrupt the processor.
(g) Single +5 V supply
(h) Can operate in DC and AC up to 2.6 MHz
Internal block diagram of IC 8253
Waveform of counter operation in
mode 0
Waveform of counter operation in
mode 1
Waveform of counter operation in
mode 2
Waveform of counter operation in
mode 3
Waveform of counter operation in
mode 4
Waveform of counter operation in
mode 5
Serial Communication
8251
 Serial Communication
• Serial communication is sending and receiving information bit
by bit. For short range communication, parallel data transfer is
preferred as it is the fastest means.
• While transferring data over long distances, parallel
communication requires numerous wires and complex error
handling/data recovery mechanisms.
• For parallel data transmission of eight bits at a time, both the
receiver and the transmitter side equipments need eight
differential amplifiers and related hardware.
 Serial Communication

• This results in complex circuitry and becomes costlier for long

distance transmission.
• Thus, serial communication is preferred for long range
communication and it can be easily implemented using a
single wire or a pair of wires.
 Key terminologies in serial
communication
The terms mainly used in serial data systems are simplex, half-
duplex, and full-duplex.
a) In simplex data transmission, data can be transferred only in
one direction. Examples for this type of systems are radio,
television, etc.
b) In half-duplex transmission, the communication can take
place in either direction between two systems but only in
one direction at a time. An example of half-duplex
transmission is a two way radio system, where one user
always listens while the other talks. This is possible by
turning off the receiver circuitry during transmission.
 Key terminologies in serial
communication
c) In full-duplex communication, both the receiver and the transmitter
can send and receive data at the same time. A normal telephone
conversation is an example of a full-duplex system.
d) For asynchronous transmission, each data character has a bit to
identify its start and one or two stop bits to identify its end.
e) Baud rate is the rate at which serial data is being transferred and in
general, it is measured in bits/second.
f) RS-232C is a standard that describes the function of the signal and
handshake pins for serial data transfer. A major problem with RS-232C
is that it can only transmit data reliably for about 50 ft (16.4 m) at its
maximum rate of 20,000 Bd.
 8251 USART
• The 8251 is a universal synchronous asynchronous receiver
transmitter (USART) used for serial data communication.
• As a peripheral device of a microcomputer system, the 8251
receives parallel data from the CPU and transmits the same in a
serial form.
• This device also receives serial data from outside, converts them
into parallel data, and sends them to the CPU.
• 8251 can support both synchronous and asynchronous
transmission formats and is programmable.
8251 USART Block Diagram
8259 Programmable
Interrupt Controller
(PIC)
 8259 Programmable Interrupt
Controller
• Interrupts are used in a system to handle routines such as reading
ASCII characters from a keyboard, detecting and performing an
emergency operations such as sounding a fire alarm.
• For this, the processor’s maskable or non-maskable interrupts are
used. However, the processor has limited number of hardware
interrupts.
• For applications that use interrupts from multiple sources, the
processor can use external device called programmable interrupt
controller (PIC) or priority interrupt controller.
 8259 Features
• The main features of the 8259 are the following:
a) It supports eight interrupt inputs from the
peripherals and issues a single interrupt signal to the
processor.
b) It supports cascading of eight 8259As and
multiplexes 64 interrupt sources into one.
c) It can set priorities for the interrupts, mask the interrupt
sources, and provide different interrupt vector
addresses.
8259 Internal Block Diagram
 8259 Internal Block Diagram
• The three registers of the 8259 are as follows
a) Interrupt mask register (IMR)
b) Interrupt request register (IRR)
c) In-service register (ISR)
• IMR maintains a mask of interrupts to enable or disable specified
interrupts.
• IRR maintains a list of the current interrupts that are pending
acknowledgement.
• ISR maintains a list of the interrupts that are pending to be sent
an end of interrupt (EOI).
 Operating Modes of 8259
• Fully Nested Mode: After initialization, the 8259A operates in
fully nested mode so it is called default mode. In this mode,
IR0 has highest priority and IR7 has lowest priority.

• Automatic Rotation Mode: In this mode, a device, after being

serviced, receives the lowest priority.

• Specific Rotation: In the Automatic Rotation mode, the interrupt

request last serviced is assigned the lowest priority, whereas in
the Specific Rotation mode, the lowest priority can be assigned to
any interrupt input (IR0 to IR7) thus fixes all other priorities.

© Oxford University Press 2013. All rights reserved.

 8237 DMA Controller
• DMA stands for direct memory access. It is one of the ways to
accomplish high-speed data transfers, directly between memory
and peripheral devices.
• The DMA is a method of data transfer between memory and I/O
devices without the intervention of microprocessor.
• This method is often used when large block of data is to be
transferred.
• DMA data transfer is controlled by using a separate DMA
controller.
 8237 DMA Controller Features

• The main features of the 8237 are

a) Four independent DMA channels.
b) Enable and disable control of individual requests.
c) Possibility for memory-to-memory transfer.
d) Address increment or decrement.
e) Cascading and expandable to any number of DMA
channels.
8237 DMA Controller Block Diagram
 8237 DMA Operating Modes
• Single bit Data Transfer Mode: One single bit has been
transferred.

• Block Data Transfer Mode : N- bit has been transferred..

• Demand Data Transfer Mode: Data Transfer rate decided by

user.
© Oxford University Press 2013. All rights reserved.