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UNIVUSITY, NADlAD
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lsne1111·111111... : .. T. .. •• 2 IV . . . Ma.CM OS ~ DESIGN
... . :.,. 112 m4
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:h ..t carry lhcir w1
J. , . _ luilable dala, if requirod wi np .
a. mcntioo than dea rly.
4. Dn w nal lkctchcs wbcRvcr IICC
fflalY·
Q,l Da u dln cted .
CO i U (a) Elc ctro ~i~ ruli o~ ~b lcm in a give
n FET is con trol led by \12\
(a) spc c,fy mg m,mmum width (\)
of MOSFET device.
(b) spe cify ing minimwn wid th
of an inte rco nne ct
(c) usin g Cop per (CU ) ru; Cl intC
TConnecting mat eria l in plac e of
(d) all of obovc Alu min um (Al ).
COl N (b) Ma tch the following!\ of
fin t col um n wit h sec ond col
as a refucn cc. um n by con sid erin g nFE T
(3)
{~~ ·nucsho\d v~\tagc incr ease
s
{~~1 Gate capa.c\\ance (Ccm) increases (a) due to cha nne l leng th mo dul
(b) due to incr eas e in VsBn voltage
atio n
(m) Lcrr < L"'r"e&1 __ __ (c) due to redu ctio n in Vs.on vol
tage
CO\ d) due to red ucti on in lox
N \c) F
·\g. \ (a) and (b) sho ws MO S e) due to positiv
tran sistors with vari ous bias ely bias ed bulk terminal
conditions. Assume that (2)
~Tn_=\V _and Bn = \00 µA.N
l.. Stat e the operating regi on of
1ust\ficat1on. MO SFE Ts alon g with

r-1'2..°o µA

-1 ~ -5 V
fi~ lW
CO2 U (d) How TG as a switch is diff F~ 10 0
erent from an ideal switch?
CO2 A (e) Draw logic diagram for func (l)
CO2 A tion OAI31.
(f) Ans wer the followings with (l)
reference to standard CM OS implem
(Co nsid er VD D =5 V, Vth n = \Vth entation of OA.13 \
p\ = 0.7V).
(i) Draw standard CMOS schema
tic that realizes the above function.
(ii) What is the minimum and max (l)
imum value for an output voltage
(iii) If we interchange Voo and GND ? (l)
, keeping other transistors as it is, wha
range of output voltage? t is the ('2.)
Q.l Attempt Any TWO from the followi
CO2 ng questions.
A {A) Obtain CMOS Schema \ll\
ticthat realize the logic function~ l AB
prepare Silicon Layout for the sam (CD+E) 1- Also (6)
CO2 R e using stick diagram. ·
(B) Explain Pass Characteristics
of nFET, pFET and Transmission
CO2 A {q Show implementation ofXNOR2 Gate as a switch. (6)
logic using TGs. Reduce Number
by eliminating the redundant one from of Transistors (6)
Q.3
the transistor level schematic.
Attempt the following questions.
COl A {A) An nFE Tw ith L '=0.5 µm with Lo=0.05 µm is built in proces , [121
and V, = 0. 7 V. The gate-source vol s where k'n = JOO µAIV2 (6)
11 tage and drain-source voltage are
VDSn=VaSn=Vvv=3.3 V. (l) Calcula set to a value of
te the required channel width to
resistance of Rn=750 ohm. (2) Cal obtain a fixed
culate the amount of current flow
nFET. through the

Paa • 1 of 2
 (I) An nFE1' process
cot is describ
A X = 4 µm, W = 6 µm , L ed by the fo\\o\\llng p ~ e \e ~ \r k, ==
= OA µm , Lo =0.02 µm
, Vrn 150 µA/V2, Cox=
l.10 ff/µm1 , Voo= 3.3 V, - 0. ,
0
CJ = 0.86 ff! µm 2, Cjsw= ,
Obtain \he RC mode\ of 0.24 ff!µ m.
the g,ven FET.
OR
Q.3 A\\tm\)t t\, c (o\\owin~ questions .
CO\
I\ V~) li) f ot the
nFE1 sho\.vn in the follo · · -.:· · llll
N ei \e ct channel leng wing figure , the thre~h · · y : (4)
the nFET . ~ii) When th
th modulation effects. old voltage ~T n I$
(i) Detenrune the
operating reg1o~ of
?-? . :
e drain vo \tage Vo= 1.3
be 0.5 mA . lf Vo V, the drain current
is adjusted to be 2J V Io was found to
by changing the va
determine the new valu lues of R and Voo,
e of lo.

G~
1:=
(ii) H ow scaling lead
COl A s to im
provement in power
(B) A n nFET proc di ss ip at io n in th e CM
ess is described by th O S ci rc ui ts?
The voltages are mea e paramet ers k'n = 110 µAIV2 (2)
sured to be Vasn = an d Vin =+ 0. 70V.
aspect ratio of 4 ha 2V and Vsan = 0V (6)
s a drain current of . (a) A FE T with
source voltage Vvsn 34 0 µA flo w in g th an
. Assume that nFET ro ug h it. Fi nd th e
aspect ratio of a sim is in non-saturation re gi on drain-
ilar device from 4 to . (b) In cr ea se th e
ob ta in ed va lu e of V 6 an d ca lc ul at e th
Blooms Taxon~my lev
osn. e dr ai n cu rr en t for
an
els : R-Remembering
, U- Understanding,
A-Applying, N- An a\y
zin g, E- Evaluating,
C-Creating
 DHARMSINH DESAI UN IVE
RS ITY , NADIAD
ll'ACULTY OF TE CH NO
SE CO ND SE SSI ON AL EX LO GY
AM INA TIO N
SU BJE CT : (EC -40 9) CM
OS VL SI DE SIG N
: B. Te ch. Sem eat er IV ·
Sea t No. · :
: 06/02/2024
Da y : Tu llld ay
: 1 ho ur 15 mi n
Ma x.M ark i : 36
INSTR,UCUQNS: ,
I. Figures to the right indica
te maximum marks for that
2. Cbe symbols used cany question.
their usual meanings.
3. Assume suitable data,
if required & mention them
4. Draw neat sketches wh clearly.
erever necessary.
Q.1
C0 3 N
Do as directed.
(a) The threshold volta ·
ge for each transistor for giv 11 l \
-
work as an inverter, Vi must en figure is 0.7 V. Fo r thi s
take the values circuit to (\ )
(a) 1 V and O V (b) -1 V
and 1 V (c) 0 V and 1 V (d)
above 1 V and -1 V (e) none of

C0 3 \l (b) Power dissipat~on of a giv

en CM OS bas ed circuitry dep end s on
(a) Sup p\y vo\ tag e (b) Fre
que ncy of inp ut pul se (c} c I>
(e) No ne of abo ve Siz e of FET s (d) All of abo
C0 1 E (c) Assume that Bo ole ve
an expression F = (a. (b +c+
siz e of al\ the tran sist ors arc d)) · is imp lem ent ed by CM
sam e. Also ass um e tha t mo OS lolliC anJ ,~ (:,
Ide ntif y the i/p com bin atio
C03 A (d) Apply 3.3 V square wav e
n wh ich can produc e sm alle
bility of e lectron and hul c!I
st swi tch ing de lay in the cin
lite equ al.
:uit.
•
inp ut
approx ima\cd outp ut wa vef onn \0 an inverter hav ing lr""lt"" \ 00p!'I. Druw op cd cu 11ml
VDo is of3 .3 V.
s for input sig nal freq uen
cy of I tit l:t and 40 \ \J..
;\ ,,u mc
I:) •
C0 4 V (e) 'fbe logica l efTon for n input NO
R log ic is calculated usin
(a) (2n + l)/3 g (ai\\um c r • 2)
(b) (n+2)/3 , Il
c·04 V (f) The Swi1ching rime of a C MO S c(c) l2n -l )/3 {d) n(n + l \/2
ircuit dep end s upo n _ _
(a) Nwnbct of inp uts (b) Tra _
nsi sto r sca ling fac tor (c) \. \ l
C0 (I) Dr fan -out (d ) A\\ of thc1e .
4 A aw a BiCMOS Driver for NO
R2.
C0 4 A (b) Dr aw (i) SlWldard CMOS and (b) pse \.~,
udo nMOS, sch em atic for
\'-l\;\C f .., - \;\ •\\ \'\. '-~'
Q.2 Anc:mpl Any TWO from lht
fo llowing que stio ns .
COJ A (A) Drow the sd1~ma1i c for the cir
cuit that impk m~nt f :: \(P+Q _ \\! \
Determine the sizes of th~ transi ) (R+s +·1·+\ l)\' .
stors for the CMOS ba ~d c\f\ \l~)
tlutt it hus approxi rmu dy the :\,\\{)' form u.,,n~ ~,-:h
sum~ l, umi lt us lUl itw~r\cr ,,
nMOS : 0.S um/0.25 um , pMOS ,th th~ f,,\h\" ,,\~ ~'-'";
: \ .5 umJ0.25 um .
C03 t (B) V l .>l "a

'\ w.
T,
L_l _

O nd

... . u n
 For the above cin:uirty, assume Wn= l.S 49µm, Cox= 3 ft7µm
m2, µn= 500 cm2N-sec,
Jlr 200 crrr/V-sec, VTn= 0.6V, VTp= -0.7V, VDD
Voo for 0,0 to 1,1 transitions in inputs. =3.3V. Find Wp to set VM=l/2
C03 V (q
(I) What is unit transistor? How it is useful in CMO
J; S based circuit designing.
(2) Find the ratio On/Op needed to obtain an
inverter midpoint voltage of
VM = 1.25 V with a power supply voltage of 3.3 V.
Vrp .. .0.82 V. Assume that VTn = 0.6 V and
R
(3) State two possible solutions to avoid latch-up in
CMOS circuits. (1)
Q.3 Attem pt the following questions.
C04
N (A) Cons ider the logic cascade shown in the
Figure below. (Assume symmetric gates
[12J
with r =2) (8)
( 1) Estimate the normalized delay from input to outpu
t.
(2) Suggest architectural change (if any) in the logic
delay . cascade to achieve the optimum
(3) Find the relative size of each stage needed to optim
chain. ize the delay through the

C.L

C04 E (B) An inverter is characterized by the

switching times (a) tr= 430 + 3.68 CL ps and (b)
tf = 300 + 2.56 CL ps. A 3 Inverter cascade is built (4)
using the abov e unit, with the
outpu t capacitance for each NOT gate is 45.tF. Find
the wors t-cas e delay throu gh the
chain.
OR
Q.3 Attempt the following questions.
C04 N (A) An 8-input AND gate is to be designed . . . .
to drive ~ load of 200 fF but ~s hm1 t~ to an mput
capacitance of 20 ff. The options are (ffigure- - 1) NAN (8)
D8 - INV ( ~ - u) NAN D4 -
NOR2 and ( ~ - iii) NAND2 - NOR 2 - NAN D2
- INV. Whic h is best option, if speed
is the criteria. Justify.
C04 E (B) Cons ider a CMO S proce ss that is chara
cteriz ed by VDD = 5V, Vthn = IVthpl = 0.8V,
\20 µ.A/V 2 and k'p = 55 µA/V 2 • A pseud o nMO S k'n = (4)
inver ter is designed using (W/L )n = 4, find
the (W/L)p in order to achie ve VoL = 0.3V.

Blooms Taxonomy levels : R-Remembering, U- Under

standing, A-Applying, N-An alyzin g, E- Evalu ating.
C-Cre ating
 Mi ? r •-...UNIVDSITY,NADIAD
•M.'Ul.'IYCWDC:BNou>GY
'llla D R ONAL DAMINAnON
sow -T: (BC - , CMOS V1B1 DESIGN

Zsrcnfnedee : a. Ted i. Sea ,.._. IV Seat No.

Data : 1911312024 l>IIJ :1'1aesclay
Time : 1 IINr 15 •la Mu. Mar ks :36

I~ : I'. If I I : .
1. Pigu na to the ripl indicate maximum marks
for that question.
2. rhc aymbols Uled carry their usual meanings.
clearly.
3. Auu mc suitable data. if n:quired cl mention lhcm
-------~•·
· -------------
ecc.ss,uy==~
•-.:4-:-....,·0nt~-:w~neat=~•:e:t~cl:1e:;•;:w;:.:-he~re,:1t1er;:~n
. . • . lll1
.I Dou dlrKted. ssion F • (ab+cd+ej) usmg (2.)
implement SOP expre
OS N (I) How many transistors are required to
NOR gates bnscd dynamic CMOS PLA?
(a) 16 (b) 17 (c) 18 (d) 14 (c) none of above
t5 E (2) A dynamic RAM cell which holds SY has
stored voltage does not fall by more than 0.5V.
to be refreshed every 10 ms, so that the (2)
If the cell has a constant leak.age
the cell is
current of 0.1 pA, then the storage capa12citance of 15 .
9 F (d) 4 x l 0· F (e) none ~f ~bov.e
(a) 1 x \0.(, F (b) 2 x lQ· F (c) 2 x 10· mic (2 )
data synchroruzat1on m dyna
cos u (3) How fo\\owing circuitry can be hel pful to maintain .
logic cascade? Discuss circuit operation in brief
Yoo

D
Q

• •

'":"'" -:-
1 fault in B path, then ( l,i
C04 E (4) In an OR gate, ifoutpu A and Bare two inputs and there is struck at
---- .--·-wliarwm-be-the t logic? --
( l)
C06 U (S) Explain IDDQ Testi ng? (2)
+ C].
C04 A (6) Draw CPL to reali ze~ [AB wha t is the (2)
chips for 1000 hours and 8 of them fail, then
C06 E (7) Ifwe operate 10,000 FPGA
reliability in terms of FIT? {.U:i
Q.2 Attempt.Any TWO from the following questions. (6)
ements XOR3.
C04 A (A) Draw DCVSL Logic that impl Dyn amic (6)
ain the problem in view of Logi c Casc ade of
C04 U (B) What is Mon oton icity ? Expl
NAND2. How the problem is addressed ? re l belo w.
S@l fault at the Pin Location B shown in Figu
C06 E (q Find Test Vector to detect '(6)
E
A
B

C
D

Q.3 Attempt ti.~f~U~winc questions. . -- •

follow· ifi ·
cos A (A) Consider SRAM memory chip with du mg spec cations .. Size ~f memory chip is lj_
256K >< 8 which is internally havin 1 core arrangement with stonn g capacity of one i I
word (8-bit) / each row. g a
Answer followings with reference to above :
(l) How storage cells are arranged • abo
m :ve memory chip? How many
Paaa 1 or 2
r
~ --
-~~..::~~ :::::=:---=---
-·- ---- -- - - -- ~
- ·- =-=====~~~~~::,::=~,
-·-- :"'--, __
~
.....,. <=._.,

required to access 8-bit of data from memory chip? -

(li) If two words are stored in each row then how many row address & column address bits
are required?
.
~
(iii) If eight words are stored in each row then how many row address & column address
bits are required?
cos u (B) Why row driver circuitry is required in SRAM chip? Draw the circuity and discus~ that (6)
how it can keep logic '1' continuously on the word line signal of selecced row. What ts the
role of EN signal? ·
OR
Q.3 Attempt the follo"'ing questions. [12]
cos U (A) (1) Compare 6T SRAM bit-cell with 1T DR.AM bit-cell in terms of (i) Area (6)
occupancy--(ii) .Storage_mechanism (iii) Number . of bit-lines (iv) Speed of write :..'.!=
operation. · ·
U (2) Draw the sense amplifier circuitry and discuss its circuit operation in brief with ~

cos A (B)
reference to read-] operation of SRAM memory.
Design a special FET based E 2 PROM that can able to store following information. (6)
.,....,
-....
A.I
Row 0 1 2 3 4
:]
-
---
Number
Data 01011011 10101111 11110101 10110000 00101000
Blooms Taxonomy levels : R-Remembering, U- Understanding, A-Applying, N-Analyzing, E- Evaluating, C-Creating